JP4291476B2 - Microprocessor - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a microprocessor, and more particularly to a microprocessor that configures a highly reliable system by controlling a redundant storage device under a hot standby system.
[0002]
[Prior art]
Conventionally, a redundant system of storage devices has been realized by connecting two storage devices (0-system storage device, 1-system storage device) and a microprocessor via an interface circuit composed of a gate array or the like.
[0003]
While the system is in operation, one of these two storage devices becomes an active (ACT) storage device and the other becomes a standby (SBY) storage device. Normally, various types of processing are executed by the ACT storage device. However, if any failure occurs in the ACT storage device, the processing is continued by switching to the SBY storage device. In order to shorten the switching time between the two storage devices in such an emergency, during normal processing, the data is written to the ACT storage device and the same data is also written to the SBY storage device. A so-called “hot standby method” that holds the same data is widely used.
[0004]
By the way, in a redundant storage system, a microprocessor is generally
・ Transfer data to the outside via the bus line.
• Performs various data transfer operations as a bus master.
-One-to-one data transfer with one bus slave specified by an address or the like is performed.
Will play a role.
[0005]
[Problems to be solved by the invention]
However, conventionally, when a dual storage device is controlled by a microprocessor under the hot standby system, there are the following problems.
[0006]
As described above, the microprocessor basically performs a one-to-one data transfer operation with a bus slave specified by an address or the like via a bus line. However, in the dual storage system using the hot standby method, a one-to-two data transfer operation between the microprocessor and the two storage devices (ACT storage device and SBY storage device) must be realized. For this reason, conventionally, a circuit for controlling waiting (timing) for data transfer with two storage devices has to be provided outside the microprocessor, leading to an increase in system scale.
[0007]
By the way, even if the storage device is duplicated, the entire memory space is not usually duplicated. For example, read-only memories that store firmware and registers of input / output devices allocated to the memory space are often not duplicated from the viewpoint of saving memory space. Only data that needs to be duplicated is subjected to data transfer waiting control as described above, and written to both of the two storage devices. On the other hand, data that does not require duplication is written in one storage space. As described above, when data duplication is selectively performed, it is necessary to determine whether the data needs to be duplicated in the system. In this regard, conventional microprocessors have not been able to cope with the duplication of storage devices, so it has been necessary to determine whether or not the data transfer requires duplication by an external circuit. However, in recent years, the operating speed of a system including a bus line has been remarkably improved, and the control of a redundant storage device by an external circuit has become a bottleneck in improving the efficiency and speed of data transfer.
[0008]
The present invention has been made in view of the above problems, and an object of the present invention is to provide a microprocessor capable of efficiently controlling a duplicated storage device without providing an external circuit. It is in.
[0009]
[Means for Solving the Problems]
In order to solve the above-described problem, a microprocessor capable of controlling data transfer to N storage devices (N is an integer of 2 or more) is provided. In the microprocessor, the one-to-one data transfer mode for transferring predetermined data only to one storage device selected from the N storage devices, or N And an address conversion table including a multiple data transfer control flag for selecting one of the 1 to N data transfer modes for transferring predetermined data to all the storage devices. According to such a configuration, it is possible to smoothly switch between the 1 to N data transfer mode and the 1 to 1 data transfer mode without providing an external circuit. Therefore, the data transfer speed is increased, and a compact system incorporating the microprocessor is realized.
[0010]
As described in claim 2, it is also possible to perform predetermined data transfer in units of pages or blocks of each storage device.
[0011]
According to the third aspect of the present invention, by providing the input / output port of the control signal assigned to each of the N storage devices, it becomes possible to execute predetermined data transfer to the N storage devices in parallel. Data transfer will be faster.
[0012]
As described in claim 4, it is also possible to select one storage device from N storage devices based on a selection signal input from the outside or a set value of an internal register.
[0013]
According to a fifth aspect of the present invention, there is provided a microprocessor characterized in that, when the 1 to N data transfer mode is selected, data transfer is sequentially executed for each of the N storage devices. According to such a configuration, 1 to N data transfer is possible without providing a dedicated bus line for each of the N storage devices. Therefore, a compact system incorporating the microprocessor is realized.
[0014]
As described in claim 6, it is also possible to set the order of the storage devices to which data transfer is performed using a part of the bits of the address signal indicating the storage space address of each storage device. According to such a configuration, it is not necessary to prepare a new flag or the like for setting the order, and compatibility with a conventional microprocessor is maintained.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Exemplary embodiments of a microprocessor according to the present invention will be described below in detail with reference to the accompanying drawings. In the following description and the attached drawings, constituent elements having substantially the same function and configuration are denoted by the same reference numerals, and redundant description is omitted.
[0016]
(First embodiment)
The microprocessor 1 according to the first embodiment of the present invention includes an execution unit 3, an instruction address conversion unit 5, a data address conversion unit 7, and a bus interface unit 9, as shown in FIG.
[0017]
The execution unit 3 executes instructions such as arithmetic operation and condition determination.
[0018]
The instruction address conversion unit 5 converts the logical address sent from the execution unit 3 into a physical address. Then, the instruction is read from the storage device using the converted physical address and transferred to the execution unit 3. The instruction cache is provided in the instruction address conversion unit 5.
[0019]
The data address conversion unit 7 accesses the storage device based on the physical address obtained by converting the logical address sent from the execution unit 3 in accordance with the instruction of the execution unit 3. That is, data is read from the storage device and transferred to the execution unit 3, and data sent from the execution unit 3 is written to the storage device. The data cache is provided in the data address conversion unit 7.
[0020]
The bus interface unit 9 performs data transfer with the outside based on instructions from the instruction address conversion unit 5 and the data address conversion unit 7. The bus interface unit 9 is connected to a plurality of signal lines used for an interface with the outside and for transmitting the signal group 11. FIG. 1 shows only signal lines related to the data transfer operation of the microprocessor 1.
[0021]
The greatest feature of the microprocessor 1 according to the first embodiment is that a signal (TS, DV, TA, TE, TR) for controlling data transfer between the bus interface unit 9 and the storage device is 2 bits. It is in width. According to such a configuration, as described later, one-to-two data transfer between the microprocessor 1 and the two storage devices is possible.
[0022]
Next, each signal will be described in detail.
[0023]
TS (Transaction Start) [0: 1]
This signal notifies the storage device of the start of the transfer operation. TS [0] is for the 0-system storage device, and TS [1] is for the 1-system storage device.
[0024]
A (Address) [0:31]
This is a signal for transferring an address to two storage devices. In the microprocessor 1 according to the first embodiment, the width is 32 bits and A [0] is the most significant bit.
[0025]
BE (Byte Enable) [0: 3]
This is a signal for notifying which bit of the data bus D is used in the transfer operation being executed. For example, when the data bus D is 32 bits wide ([0:31]), the role of each bit of BE [0: 3] is as follows.
BE [0]: The current transfer operation uses the data bus D [0: 7].
BE [1]: The current transfer operation uses the data bus D [8:15].
BE [2]: The current transfer operation uses the data bus D [16:23].
BE [3]: The current transfer operation uses the data bus D [24:31].
[0026]
CMD (Command) [0: 2]
Indicates the mode of data transfer operation to be performed. The microprocessor 1 according to the first embodiment shows eight types of modes as described below.
000: Single read (read one word)
001: Single write (1 word write)
010: Burst read (4 words read)
011: Burst write (4 words write)
100: I / O read (one word read)
101: I / O write (1 word write)
110: Interrupt vector read (read one word)
111: Interrupt end notification (1 word write)
[0027]
D (Data) [0:31]
Used for data transfer. The microprocessor 1 according to the first embodiment has a width of 32 bits, and D [0] is the most significant bit.
[0028]
DV (Data Valid) [0: 1]
This signal indicates the timing at which TA [0: 1] can be asserted for each storage device. DV [0] is for the 0-system storage device, and DV [1] is for the 1-system storage device.
[0029]
TA (Transaction Acknowledge) [0: 1]
This is a signal for notifying the microprocessor 1 of completion of data transfer from each storage device. TA [0] is for the 0-system storage device, and TA [1] is for the 1-system storage device.
[0030]
TE (Transaction Error) [0: 1]
This signal is used to notify the microprocessor 1 from each storage device that an error has occurred during data transfer. Care is taken (confirmed) in the cycle in which the corresponding TA [0: 1] is asserted. TE [0] is for the 0-system storage device, and TE [1] is for the 1-system storage device.
[0031]
TR (Transaction Retry) [0: 1]
This signal requests the microprocessor 1 to re-execute the data transfer operation from each storage device. Care is taken in the cycle in which the corresponding TA [0: 1] is asserted. TR [0] is for the 0-system storage device, and TR [1] is for the 1-system storage device.
[0032]
The instruction address conversion unit 5 and the data address conversion unit 7 included in the microprocessor 1 according to the first embodiment have a function of supporting the virtual storage system. Conversion from a logical address to a physical address is performed using an address conversion table. The address translation table includes a set of page descriptors structured as shown in FIG. Here, the function of each field and each flag will be described.
[0033]
(1) Physical page number field
This field specifies the page number in the physical address. In this embodiment, the description is given in the case where the page size is 4 KB and the address is 32 bits, and the physical page number field is 20 bits.
[0034]
(2) Reserved field
In this embodiment, it is not used.
[0035]
(3) Cache control field
{Circle around (1)} Defines the operation of the cache memory when accessing the page specified in the physical page number field. In the present embodiment, each value set in this field defines the operation of the cache memory as follows.
00, 01: The page is not cached.
10: Cache the page in write-through mode.
11: Cache the page in copyback mode.
[0036]
(4) Protection attribute field
In the present embodiment, each value set in this field defines a protection attribute as follows.
000: Only data reading is permitted only in privileged mode.
001: Reading and writing of data are permitted only in privileged mode.
010: Permits reading of instructions and data only in privileged mode.
011: All access is permitted only in privileged mode.
100: All access is permitted in privileged mode. In other modes, only data reading is allowed.
101: All access is permitted in the privileged mode. In other modes, reading and writing of data are permitted.
110: All access is permitted in the privileged mode. In other modes, reading of instructions and data is permitted.
111: All accesses are permitted even in non-privileged mode (in all modes).
[0037]
(5) Access flag
Set when the page is first accessed.
[0038]
(6) Correction flag
Set on first write to the page.
[0039]
▲ 7 ▼ Page absence flag
Indicates that the page has been swapped out to auxiliary storage.
[0040]
(8) Redundant control flag
Specifies that a duplex data transfer operation (described later) is performed when accessing the page.
[0041]
The above is the page descriptor used when the microprocessor 1 according to the first embodiment converts a logical address into a physical address. This page descriptor is particularly characterized in that it has (8) duplex control flag.
[0042]
FIG. 3 shows the configuration of a system that includes the microprocessor 1 according to the first embodiment and has a dual storage device. A 0-system storage device M10 and a 1-system storage device M11 are connected to the microprocessor 1. Regarding TS, DV, TA, TE, and TR, the microprocessor 1 includes dedicated ports for the 0-system storage device M10 and the 1-system storage device M11. On the other hand, for A, BE, CMD, and D, the microprocessor 1 is provided with a common port for the 0-system storage device M10 and the 1-system storage device M11.
[0043]
The microprocessor 1 converts a logical address into a physical address and uses the physical address obtained by the conversion to access a storage device for the purpose of reading an instruction and reading / writing data. The microprocessor 1 can specify duplication when accessing the storage device. As described above, the duplex data transfer operation is designated by the (8) duplex control flag (see FIG. 2) in the page descriptor of the address translation table. In the page descriptor (page descriptor corresponding to the physical page to be accessed) used for address translation, (8) the duplex control flag is set, and the transfer operation to be executed is data for the storage device. In the write operation, the microprocessor 1 performs a duplicated data transfer operation and writes the same data to both the 0-system storage device M10 and the 1-system storage device M11. Hereinafter, the microprocessor 1 will be described with reference to a case where two types of write operations, that is, a single write operation for writing one word data to each storage device and a burst write operation for writing four words data, are possible.
[0044]
First, the single write operation will be described with reference to FIG. One of the 0-system storage device M10 and the 1-system storage device M11 responds first to the microprocessor 1 depending on its state (for example, whether or not it is in a refresh operation). From time T01 to time T07, the 0-system storage device M10 responds first and then the 1-system storage device M11 responds. From time T08 to time T14, the 1-system storage device M11 responds first. Then, the case where the 0-system storage device M10 responds is shown. Hereinafter, the operation of the microprocessor 1 will be described for each time.
[0045]
Time T01
The microprocessor 1 asserts TS [0: 1] to notify the 0-system storage device M10 and 1-system storage device M11 of the start of the data transfer operation, and uses A [0:31] to specify the address. Indicates which part of D [0:31] is used using BE [0: 3], and further indicates that the operation started using CMD [0: 2] is a single write operation. Show. Also, output of valid write data is started for the bits of D [0:31] specified by BE [0: 3]. Then, DV [0: 1] is asserted to indicate that TA [0: 1] is waiting for the 0-system storage device M10 and the 1-system storage device M11.
[0046]
Time T02
The microprocessor 1 waits for the assertion of TA [0: 1] by the 0-system storage device M10 or the 1-system storage device M11.
[0047]
Time T03
The 0-system storage device M10 asserts TA [0] to notify the completion of the write operation to the microprocessor 1 and indicates the completion status using TE [0] and TR [0].
[0048]
Time T04
Since the write operation to the 0-system storage device M10 is completed in the previous cycle (time T03) and TA [0] is asserted, DV [0] is negated and the data transfer operation to the 0-system storage device M10 is performed. Notify completion. The 1-system storage device M11 asserts TA [1] and notifies the microprocessor 1 of the completion of the write operation in the same manner as the 0-system storage device M10.
[0049]
Time T05
In the previous cycle (time T04), the write operation to the 1-system storage device M11 is completed and TA [1] is asserted, so DV [1] is negated and the data transfer operation to the 1-system storage device M11 is performed. Notify completion.
[0050]
Time T06, T07
This is a state in which the data write operation to the 0-system storage device M10 and the 1-system storage device M11, that is, the duplicated data transfer operation is completed.
[0051]
Time T08-T14
After time T08, as described above, the operation of the microprocessor 1 when the 1-system storage device M11 responds to the microprocessor 1 before the 0-system storage device M10 is shown. The storage device M10 performs substantially the same operation as the times T01 to T07 during which the storage device M10 responds before the first-system storage device M11.
[0052]
The above is the duplexed single write operation by the microprocessor 1. Next, a duplex burst write operation is shown in FIG.
[0053]
The operation of the microprocessor 1 from time T01 to time T04 is the same as the single write operation shown in FIG. In the burst write operation, another three words are transferred after time T05. The microprocessor 1 waits for a response from the 0-system storage device M10 and the 1-system storage device M11 for each word transfer.
[0054]
Furthermore, the single read operation of the microprocessor 1 according to the first embodiment is shown at times T01 to T07 in FIG. 6, the non-duplex single write operation is shown at times T08 to T14 in FIG. 6, and the non-duplex burst write operation is performed. FIG. 7 shows a burst read operation. 6 and 8, the 0-system storage device M10 is an ACT storage device, and the 1-system storage device M11 is an SBY storage device. On the other hand, in FIG. 7, the 1-system storage device M11 is an ACT storage device, and the 0-system storage device M10 is an SBY storage device. As shown in the figure, in the case of a single read operation, a burst read operation, a non-duplex single write operation, and a non-duplex burst write operation, the microprocessor 1 The transfer operation is executed only for the current ACT storage device. Note that either the 0-system storage device M10 or the 1-system storage device M11 is selected as the ACT storage device based on the signal from the outside of the microprocessor 1 or the setting of the internal register.
[0055]
According to the microprocessor 1 according to the first embodiment configured and operating as described above, two storage devices (the 0-system storage device M10 and the 1-system storage device M11) are connected to the microprocessor 1. Therefore, it is not necessary to provide a complicated control circuit for the outside, so that a faster data transfer operation is realized.
[0056]
In addition, since the number of necessary parts is reduced, a low-cost and highly reliable system is provided.
[0057]
Furthermore, it is possible to finely set the address range to be subjected to the duplex data transfer operation by software, and to make the double and non-duplicated areas coexist in the storage space. By executing processing that requires high reliability in a duplexed area and executing other processes in a non-redundant area, the cost performance of the system can be improved.
[0058]
(Second Embodiment)
A microprocessor 2 according to the second embodiment and a 0-system storage device M20 and a 1-system storage device M21 connected thereto are shown in FIG.
[0059]
The greatest feature of the microprocessor 1 according to the first embodiment is that signals (TS, DV, TA, TE, TR) for controlling data transfer between the bus interface unit 9 and each storage device are two. There is a bit width. According to this configuration, a so-called one-to-two data transfer operation between the microprocessor 1 and the two storage devices can be performed. On the other hand, the microprocessor 2 according to the second embodiment is substantially the same as the conventional microprocessor in the configuration of the signal lines drawn from the bus interface unit so as to be plug compatible with the conventional microprocessor. It is said. That is, the TS, DV, TA, TE, and TR signal lines that existed two by two in the microprocessor 1 according to the first embodiment are all one in the microprocessor 2 according to the second embodiment. Each signal line is connected to both the 0-system storage device M20 and the 1-system storage device M21.
[0060]
Furthermore, the microprocessor 2 according to the second embodiment uses the most significant bit A [0] of the address signal A to distinguish between the 0-system storage device M20 and the 1-system storage device M21 as follows: It can be accessed individually.
[0061]
The microprocessor 2 according to the second embodiment can access a physical address space of 4 Gbytes using a 32-bit width address in the same manner as the microprocessor 1 according to the first embodiment. . Here, the 0-system storage device M20 is assigned to the lower 2 Gbyte range of the 4 Gbyte address space, that is, the range accessed when the most significant bit A [0] of the address is 0, and the 4 Gbyte address The 1-system storage device M21 is assigned to the upper 2 Gbyte range of the space, that is, the range accessed when the most significant bit A [0] of the address is 1.
[0062]
The microprocessor 2 according to the second embodiment operates in substantially the same manner as the microprocessor 1 according to the first embodiment with respect to selection of the ACT storage device and designation of the duplex data transfer operation by the address conversion unit. However, in the duplex data transfer operation, the two differ as follows.
[0063]
When the duplex data transfer operation is designated, the bus interface unit 9 provided in the microprocessor 1 according to the first embodiment sends the control signals (TS, DV, TA, TE, TR) each having a 2-bit width. The transfer operation between the 0-system storage device M10 and the 1-system storage device M11 is executed in parallel.
[0064]
On the other hand, in the microprocessor 2 according to the second embodiment, since the control signals (TS, DV, TA, TE, TR) are each 1 bit, the 0-system storage device M20 and the 1-system storage device M21. The transfer operation between the two is executed serially. That is, when the duplex data transfer operation is designated, the microprocessor 2 first performs the SBY system with the ACT system storage device designated by the most significant bit A [0] of the address signal A as follows. A total of two data transfer operations are performed with the storage device. Note that, in the microprocessor 2 according to the second embodiment, the duplicated data transfer is performed only in the case of a data write operation as in the microprocessor 1 according to the first embodiment.
[0065]
(1) Based on the signal from the outside of the microprocessor 2 or the setting of the internal register, either the 0-system storage device M20 or the 1-system storage device M21 is selected as the ACT storage device. Then, the microprocessor 2 performs a data transfer operation with the selected ACT storage device. Here, when the 0-system storage device M20 is selected as the ACT storage device, the most significant bit A [0] of the address A is set to 0, and when the 1-system storage device M21 is selected as the ACT storage device, Bit A [0] is set to 1.
[0066]
(2) The value of the most significant bit A [0] of the address A is inverted. At (1), if bit A [0] is 0, it is inverted to 1, and if it is 1, it is inverted to 0. As a result, the data transfer destination storage device is switched, and a data transfer operation is performed between the microprocessor 2 and the new storage device. In the data transfer of (2), other than bit A [0], that is, A [1:31], TS [0], BE [0], CMD [0: 2], D [0:31], DV [0], TA [0], TE [0], TR [0] are set to the same values as in the data transfer in (1).
[0067]
As described above, according to the microprocessor 2 according to the second embodiment, the same effect as that of the microprocessor 1 according to the first embodiment can be obtained, and the microprocessor 2 is configured as a plug compatible with the conventional microprocessor. Therefore, it is possible to directly adopt the conventional circuit without changing the design of the peripheral circuit.
[0068]
The preferred embodiments of the present invention have been described with reference to the accompanying drawings, but the present invention is not limited to such embodiments. It will be obvious to those skilled in the art that various changes or modifications can be conceived within the scope of the technical idea described in the claims, and these are naturally within the technical scope of the present invention. It is understood that it belongs.
[0069]
For example, the microprocessor 1 according to the first embodiment shares address lines, data lines, etc. with respect to the 0-system storage device M10 and the 1-system storage device M11 for the purpose of reducing the number of signal lines. However, if the data bus width and the number of terminals of the microprocessor are sufficient, independent signal lines can be assigned to each storage device. That is, according to the first embodiment, the microprocessor 1 includes a bus interface unit that can be connected to a bus line dedicated to the 0-system storage device M10 and a bus line dedicated to the 1-system storage device M11. Data transfer may be performed by selecting any bus line.
[0070]
In the second embodiment, the case where a part of the address signal A (the most significant bit A [0]) is used to specify each of the 0-system storage device M20 and the 1-system storage device M21 has been described. However, if there is an available terminal on the microprocessor, it is also possible to assign that terminal for the selection signal of the storage device.
[0071]
【The invention's effect】
As described above, according to the present invention, an external circuit for controlling waiting for data transfer with a plurality of storage devices is not required, and a system scale can be reduced. In addition, it is possible to increase the efficiency and speed of data transfer with each storage device.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a microprocessor according to a first embodiment.
FIG. 2 is an explanatory diagram showing a structure of a page descriptor of an address conversion table included in the microprocessor of FIG. 1;
3 is a block diagram showing a connection relationship between the microprocessor of FIG. 1, the 0-system storage device, and the 1-system storage device. FIG.
4 is a timing chart showing a duplex single write operation between the microprocessor of FIG. 3, the 0-system storage device, and the 1-system storage device. FIG.
5 is a timing chart showing a duplex burst write operation between the microprocessor of FIG. 3, the 0-system storage device, and the 1-system storage device. FIG.
6 is a timing chart showing a single read operation and a non-redundant single write operation between the microprocessor of FIG. 3, the 0-system storage device, and the 1-system storage device. FIG.
7 is a timing chart showing a non-redundant burst write operation between the microprocessor of FIG. 3, the 0-system storage device, and the 1-system storage device. FIG.
8 is a timing chart showing a burst read operation between the microprocessor of FIG. 3, the 0-system storage device, and the 1-system storage device. FIG.
FIG. 9 is a block diagram showing a connection relationship between a microprocessor according to a second embodiment, a 0-system storage device, and a 1-system storage device;
[Explanation of symbols]
1: Microprocessor
2: Microprocessor
3: Execution unit
5: Instruction address converter
7: Data address converter
9: Bus interface section
11: Signal group
M10: 0 system storage device
M11: 1 system storage device
M20: 0 system storage device
M21: 1 system storage device

Claims (6)

A microprocessor capable of controlling data transfer to N (N is an integer of 2 or more) storage devices,
An address conversion table including a multiple data transfer control flag for selecting all or any of the N storage devices as a transfer destination of predetermined data;
Along with the predetermined data, a plurality of bits corresponding to each of the N storage devices are transferred,
A microprocessor in which a bit corresponding to a storage device selected as a transfer destination among the plurality of bits has a predetermined bit value .   2. The microprocessor according to claim 1, wherein the predetermined data is transferred in units of pages or blocks of each storage device.   3. The microprocessor according to claim 1, further comprising an input / output port for a control signal assigned to each of the N storage devices.   The one storage device is selected from the N storage devices based on a selection signal input from the outside or a set value of an internal register. The microprocessor described. The predetermined data is transferred to the N storage devices in an arbitrary order when all of the N storage devices are selected as transfer destinations. 3. The microprocessor according to 3 or 4.   6. The microprocessor according to claim 5, wherein the order of the storage devices to which the data transfer is performed is set using a part of bits of an address signal indicating the storage space address of each storage device.

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