JP4297863B2 - Power failure detection device, power supply switching device, uninterruptible power supply device, and power failure detection program - Google Patents

Description

  The present invention relates to a power failure detection device, a power supply switching device, an uninterruptible power supply device, and a power failure detection program.

  Conventionally, as a method of detecting a power failure, for example, there is a method as shown in Patent Document 1. In this method, as shown in FIG. 15A, the power supply voltage is full-wave rectified by a rectifier 1, smoothed by a low pass filter (LPF) 2 and converted into a DC voltage, and this DC voltage is predetermined. The reference voltage Vref is compared with the comparator 3 to detect the presence or absence of a power failure.

  As another method, as shown in FIG. 15B, limit values (indicated by broken lines) on the high (H: High) side and the low (L: Low) side with respect to the power supply voltage (curved line). There is a method of determining that a power failure has occurred when the power supply voltage deviates from these limits.

Japanese Utility Model Publication No. 3009726 (paragraph [0010], FIG. 3)

  By the way, in the method shown in FIG. 15A, it is necessary to use a low-pass filter 2 having a cutoff frequency of about several Hz. For this reason, there is a problem that the response speed until a power failure is detected is very slow.

  On the other hand, by using a notch filter (for example, a Twin-T filter) that cuts off twice the input frequency as the low-pass filter 2, the response speed can be increased. However, the response speed is still several ms. Can only be realized. For this reason, for example, it is difficult to use as a power failure detection device for a computer that requires power failure detection within 1 ms.

  In the method shown in FIG. 15B, the detection speed can be increased, but there is a problem that it is easily affected by waveform distortion and malfunctions.

  The present invention has been made based on the above circumstances, and the purpose thereof is to quickly detect the occurrence of a power outage and to reduce malfunctions, a power failure detection device, a power supply switching device, an uninterruptible power supply device, and a power failure. An object is to provide a detection program.

In order to achieve the above-described object, the power failure detection device of the present invention generates a first signal and a second signal having a predetermined phase difference by inputting a power supply voltage and shifting a phase , The first signal having the transfer function ωc / (s + ωc) and the first filter having the transfer function s / (s + ωc) are shifted so that the phase difference between the first signal and the second signal is 90 °. The output voltage obtained by applying the power supply voltage to the second filter is output as the first signal and the second signal, respectively, and the output signal from the second filter is multiplied by ωc / ω and output. A phase shift means having a constant multiplication means, an arithmetic means for executing an operation of squaring each of the first signal and the second signal output from the phase shift means, and an output of the arithmetic means; A power failure occurs when the threshold is below the specified threshold. Detection means for determining that the, and has a.

For this reason, while detecting the occurrence of a power failure quickly, a power failure detection device with few malfunctions can be provided. Further, the phase shift means shifts the phase so that the phase difference between the first signal and the second signal is 90 °, and the calculation means squares each of the first signal and the second signal. Since the detection means determines that a power failure has occurred when the output of the calculation means is less than or equal to a predetermined threshold, a low-pass filter with a low cutoff frequency can be eliminated. A power failure can be detected quickly. Further, the phase shift means outputs the output voltage obtained by applying the power supply voltage to the first filter having the transfer function ωc / (s + ωc) and the second filter having the transfer function s / (s + ωc). Since it outputs as a 1st signal and a 2nd signal, respectively, it can detect a power failure rapidly by setting (omega) c which is a cutoff angular frequency to a high angular frequency. In addition, since the phase shift means has constant multiplication means that outputs the output signal from the second filter multiplied by ωc / ω, it is possible to prevent ripples from occurring in the output of the arithmetic means.

Further, in the power failure detection device of another invention, in addition to the above-mentioned invention, the phase shift means changes the value of ω of the constant multiplication means in accordance with the frequency of the power supply voltage. For this reason, even when the frequency of the power supply fluctuates, it is possible to prevent ripples from occurring in the output of the arithmetic means.

Further, the power supply switching device of the present invention generates a first signal and a second signal having a predetermined phase difference by inputting a power supply voltage and shifting the phase, and the first signal and the second signal are generated. For the first filter having a transfer function ωc / (s + ωc) and the second filter having a transfer function s / (s + ωc) A phase having constant multiplying means for outputting the output voltage obtained by applying the power supply voltage as the first signal and the second signal, respectively, and further outputting the output signal from the second filter multiplied by ωc / ω. The shift means, the calculation means for executing the calculation of adding the first signal and the second signal output from the phase shift means by squaring each other, and the output of the calculation means is below a predetermined threshold value Detection to determine if a power outage has occurred In the case where the stage, that the power failure by the detection means has occurred is detected are those having a switching means for switching to another power source.

Therefore, it is possible to provide a power supply switching device that can quickly detect the occurrence of a power failure and has few malfunctions. Further, the phase shift means shifts the phase so that the phase difference between the first signal and the second signal is 90 °, and the calculation means squares each of the first signal and the second signal. Since the detection means determines that a power failure has occurred when the output of the calculation means is less than or equal to a predetermined threshold, a low-pass filter with a low cutoff frequency can be eliminated. A power failure can be detected quickly. Further, the phase shift means outputs the output voltage obtained by applying the power supply voltage to the first filter having the transfer function ωc / (s + ωc) and the second filter having the transfer function s / (s + ωc). Since it outputs as a 1st signal and a 2nd signal, respectively, it can detect a power failure rapidly by setting (omega) c which is a cutoff angular frequency to a high angular frequency. In addition, since the phase shift means has constant multiplication means that outputs the output signal from the second filter multiplied by ωc / ω, it is possible to prevent ripples from occurring in the output of the arithmetic means.

The uninterruptible power supply of the present invention generates a first signal and a second signal having a predetermined phase difference by inputting a power supply voltage and shifting the phase, and the first signal and the second signal The phase is shifted so that the phase difference between the two signals is 90 °, and the first filter having the transfer function ωc / (s + ωc) and the second filter having the transfer function s / (s + ωc) The output voltage obtained by applying the power supply voltage is output as the first signal and the second signal, respectively, and the output signal from the second filter is output by multiplying the output signal by ωc / ω. A phase shift means, a calculation means for performing a calculation of adding and summing the first signal and the second signal output from the phase shift means, and the output of the calculation means is less than a predetermined threshold value In some cases, it is determined that a power failure has occurred. And means, when the power failure by the detection means is detected to have occurred, those having a switching means for switching the power supply for the backup.

Therefore, it is possible to provide an uninterruptible power supply device that can quickly detect the occurrence of a power failure and has few malfunctions. Further, the phase shift means shifts the phase so that the phase difference between the first signal and the second signal is 90 °, and the calculation means squares each of the first signal and the second signal. Since the detection means determines that a power failure has occurred when the output of the calculation means is less than or equal to a predetermined threshold, a low-pass filter with a low cutoff frequency can be eliminated. A power failure can be detected quickly. Further, the phase shift means outputs the output voltage obtained by applying the power supply voltage to the first filter having the transfer function ωc / (s + ωc) and the second filter having the transfer function s / (s + ωc). Since it outputs as a 1st signal and a 2nd signal, respectively, it can detect a power failure rapidly by setting (omega) c which is a cutoff angular frequency to a high angular frequency. In addition, since the phase shift means has constant multiplication means that outputs the output signal from the second filter multiplied by ωc / ω, it is possible to prevent ripples from occurring in the output of the arithmetic means.

Further, the power failure detection program of the present invention generates a first signal and a second signal having a predetermined phase difference by inputting a power supply voltage and shifting the phase, and the first signal and the second signal The phase is shifted so that the phase difference between the two signals is 90 °, and the first filter having the transfer function ωc / (s + ωc) and the second filter having the transfer function s / (s + ωc) The output voltage obtained by applying the power supply voltage is output as the first signal and the second signal, respectively, and the output signal from the second filter is output by multiplying the output signal by ωc / ω. When the output of the phase shift means, the first signal output from the phase shift means, and the second signal are squared and added to each other, and the output of the calculation means is below a predetermined threshold Determines that a power outage has occurred Detecting means, so that causes a computer to function as a.

For this reason, while detecting the occurrence of a power failure quickly, a power failure detection program with few malfunctions can be provided. Further, the phase shift means shifts the phase so that the phase difference between the first signal and the second signal is 90 °, and the calculation means squares each of the first signal and the second signal. Since the detection means determines that a power failure has occurred when the output of the calculation means is less than or equal to a predetermined threshold, a low-pass filter with a low cutoff frequency can be eliminated. A power failure can be detected quickly. Further, the phase shift means outputs the output voltage obtained by applying the power supply voltage to the first filter having the transfer function ωc / (s + ωc) and the second filter having the transfer function s / (s + ωc). Since it outputs as a 1st signal and a 2nd signal, respectively, it can detect a power failure rapidly by setting (omega) c which is a cutoff angular frequency to a high angular frequency. In addition, since the phase shift means has constant multiplication means that outputs the output signal from the second filter multiplied by ωc / ω, it is possible to prevent ripples from occurring in the output of the arithmetic means.

  The present invention can quickly detect the occurrence of a power failure and provide a power failure detection device, a power supply switching device, an uninterruptible power supply device, and a power failure detection program with few malfunctions.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration example of a power failure detection apparatus according to the first embodiment of the present invention. As shown in this figure, the power failure detection apparatus according to the first embodiment of the present invention mainly includes phase shifters 50 and 51, a constant multiplier 52, multipliers 53 and 54, an adder 55, and a comparator 56. As a component. Note that the power failure detection device according to the embodiment of the present invention is based on the relationship shown in the following formula 1, and is generated by shifting the phase of the power supply voltage and having a phase difference of 90 ° (cos θ and sin θ). ) Is detected by taking advantage of the fact that the value obtained by squaring and adding each becomes “1”. That is, when the power supply voltage is a sine wave, an AC signal can be converted to a DC signal without delay if a signal having a phase shift of 90 ° with respect to the input signal can be generated without delay. For this reason, in the power failure detection apparatus according to the embodiment of the present invention, a signal having a phase shift of 90 ° is generated without delay, and a DC signal obtained by squaring and adding these signals is used to Detect outbreaks.

Here, the phase shifters 50 and 51 as the phase shift means have the transfer functions G ₁ and G ₂ shown in the equations (2) and (3), respectively, and as the phase characteristics, the equations (4) and It has the characteristic shown to Formula (5), and has the characteristic shown to Formula (6) and Formula (7) as a gain characteristic. Note that ω _c is a cutoff angular frequency, and is set to a value of about 20000 [rad / s], for example.

  Here, the output signals of the phase shifter 50 and the phase shifter 51 have a phase difference of π / 2 (= 90 °) as shown in the following formula (8). The output signal has a phase difference of 90 °.

Since the gain of the phase shifter 50 is larger than the gain of the phase shifter 51, the constant multiplying unit 52, which is a constant multiplying unit, corrects the output of the phase shifter 51 by λ times shown in Equation 9 below. (Ω _c / ω times) and output.

  The multiplier 53, which is a part of the calculation means, squares the output signal of the phase shifter 50 and outputs it. The multiplication unit 54, which is a part of the calculation means, squares the output signal of the constant multiplication unit 52 and outputs the result. The adder 55, which is a part of the calculation means, adds the output signal of the multiplier 53 and the output signal of the multiplier 54 and outputs the result.

  The comparator 56 that is a part of the detection means compares the output signal of the adder 55 with the reference signal Vref, and when the output signal of the adder 55 is equal to or higher than Vref, the output is set to a high state. Otherwise, it is in the low state.

  Next, the operation of the first embodiment of the present invention will be described.

  The voltage signal of the power source that is the target of the power failure detection is input to the phase shifters 50 and 51, respectively. Since the phase shifter 50 is a low-pass filter having a bilinear function shown in Expression (2) as a transfer function, the phase shifter 50 outputs the input signal with a delay by a phase angle shown in Expression (4). On the other hand, the phase shifter 51 is a high-pass filter having a bilinear function shown in Expression (3) as a transfer function, and therefore advances and outputs the input signal by the phase angle shown in Expression (5).

  The output of the phase shifter 51 is supplied to the constant multiplier 52, where it is output after being multiplied by a constant λ shown in the equation (9). As a result, the signal level of the output signal of the constant multiplier 52 and the output signal of the phase shifter 50 are substantially the same.

  The multiplier 53 squares the output signal from the phase shifter 50 and outputs it. The multiplier 54 squares the output signal from the constant multiplier 52 and outputs the result. The adder 55 adds the output of the multiplier 53 and the output of the multiplier 54. As a result, the input signal becomes a signal whose phase is shifted by 90 ° by the phase shifters 50 and 51, and is adjusted by the constant multiplier 52 so that the signal level is the same, and then is squared and added. The output of the adder 55 is a DC signal based on Equation 1.

  The comparator 56 compares the output of the adder 55 with a predetermined reference voltage (threshold value) Vref. When the output is less than the reference voltage Vref, the comparator 56 sets the output to a low state, and otherwise sets the output to a high state. To do. As a result, it can be determined that the output signal of the comparator 56 is normal when it is high, and that it is a power failure when it is low.

Incidentally, the phase shifter 50 as a low pass filter, a cutoff angular frequency omega _c as described above, since the set value of about 20000 [rad / s], the degree delay amount of the output signal can be ignored (1 Less than °). For this reason, compared with the case where a cutoff frequency of about several Hz is set as in the conventional technique shown in FIG. 15A, a power failure has occurred in the power failure detection apparatus according to the first embodiment of the present invention. In that case, the output changes instantaneously, so that the occurrence of a power failure can be detected quickly.

2-4 is a figure which shows the result of having simulated the operation | movement of the power failure detection apparatus which concerns on this Embodiment with the computer. In FIG. 2, 20000 [rad / s] is set as ω _c included in the phase shifters 50 and 51 and the constant multiplier 52, and 110π (= 2 × π × 55 Hz) [rad / s] is set as ω. FIG. 11 is a diagram illustrating an operation when a power failure occurs in a phase where a 55 Hz signal is input as an input voltage and the input voltage is “0”. Here, FIG. 2A is a diagram illustrating a signal state from 0.00 s to 0.20 s when a power failure occurs at 0.10 s. 2A, Vin indicates an input signal to the phase shifters 50 and 51, V0 indicates an output signal of the phase shifter 50, V90 indicates an output signal of the constant multiplier 52, and Vadd indicates an adder 55. In addition, Vcom indicates the output signal of the comparator 56. As shown in this figure, the input signal Vin is set to have a phase difference of 90 ° by the phase shifters 50 and 51, and set to have the same amplitude by the constant multiplier 52, and is output as V0 and V90. The When a power failure occurs at 0.10 s and the input signal Vin becomes “0”, the output signal Vadd of the adder 55 becomes “0”. As a result, the output signal Vcom of the comparator 56 is low. It becomes.

  FIG. 2B is an enlarged view of the vicinity of 0.10 s in the range of 98.00 ms to 102.00 ms. As shown in this figure, when a power failure occurs and the input signal Vin becomes “0”, the output signal Vcom of the comparator 56 instantaneously becomes low, and the change of the state is completed within 1 ms. Yes.

  FIG. 3 is a diagram illustrating an operation when a power failure occurs in a phase where the input voltage is maximum when the same conditions as in FIG. 2 are set. Here, FIG. 3A is a diagram illustrating a signal state in a range of 0.00 s to 0.20 s when a power failure occurs at 0.095 s. As shown in this figure, when a power failure occurs at 0.095 s and the input signal Vin becomes “0”, the output signal Vadd of the adder 55 becomes “0”, and as a result, the comparator 56 The output signal Vcom is in a low state. FIG. 3B is an enlarged view of the vicinity of 0.095 s in the range of 93.00 ms to 97.00 ms. As shown in this figure, when a power failure occurs and the input signal Vin becomes “0”, the output signal Vcom of the comparator 56 becomes low with a delay of about 0.20 ms. End within 1 ms.

Fig. 2 is a simulation when a power failure occurs when the input voltage is minimum, and Fig. 3 is a simulation when a power failure occurs when the input voltage is maximum, both of which detect the power failure within 500μs. Yes. From these simulations, set 20000 [rad / s] as omega _c, sets the 110π [rad / s] as omega, if you enter a signal of 55Hz as the input voltage is a power failure at any timing input signal Even in such a case, it is considered that a power failure can be detected within at least 500 μs.

  2 and 3, 110π [rad / s] is set as ω. This is because the frequency of the commercial power source is 60 Hz in western Japan and 50 Hz in eastern Japan. This is because 55 Hz is adopted. Therefore, when actually used, the frequency of the input signal is 50 Hz in eastern Japan and 60 Hz in western Japan.

  FIG. 4 is a diagram illustrating an operation when a power failure occurs at a phase in which 110π [rad / s] is set as ω, a 50 Hz signal is input as an input signal, and the input signal is “0”. As shown in FIG. 4A, when the set value of ω of the constant multiplier 52 is different from the angular frequency of the input signal, the amplitudes of V0 and V90 that are the outputs of the phase shifter 50 and the constant multiplier 52 are obtained. Is different. Further, the output signal of the adder 55 includes ripples and is not a complete DC voltage.

  FIG. 4B is an enlarged view of the range of 108.00 to 112.00 ms in FIG. As shown in this figure, when a power failure occurs at 110.00 ms, the output voltage Vcom of the comparator 56 is instantaneously low.

  FIG. 5 is a diagram illustrating an operation when a power failure occurs at a phase in which 110π [rad / s] is set as ω, a 50 Hz signal is input as an input signal, and the amplitude of the input signal is maximum. Also in this case, as in the case of FIG. 4, when the set value of ω of the constant multiplier 52 is different from the angular frequency of the input signal, V0 that is the output of the phase shifter 50 and the output of the constant multiplier 52 are used. The amplitude of a certain V90 is different. Further, the output signal of the adder 55 includes ripples and is not a complete DC voltage.

  FIG. 5B is an enlarged view of the range of 103.00 to 107.00 ms in FIG. As shown in this figure, when a power failure occurs at 105.00 ms, the output voltage Vcom of the comparator 56 goes low with a delay of about 0.20 ms, and the change in the state is completed within 1 ms.

  4 and 5, it is possible to quickly detect a power failure even when the set angular frequency of ω and the angular frequency of the input signal are different. In such a case, by using a value (eg, a value “0.4”) smaller than the expected fluctuation range of ripple as the reference voltage Vref of the comparator 56, malfunction due to ripple can be prevented. Including the error, the frequency of the input signal is 50 ± 5 Hz in eastern Japan, and 60 ± 5 Hz in western Japan, and takes a value between 45 and 65 Hz. It is desirable to use a small value as the reference voltage Vref.

  Next, a second embodiment of the present invention will be described.

  FIG. 6 is a diagram illustrating a configuration example of the power failure detection apparatus according to the second embodiment of the present invention. In this figure, parts corresponding to those in FIG. In the example of this figure, compared with the case of FIG. 1, a frequency detection unit 70 is newly added, and the constant multiplication unit 52 is replaced with a constant multiplication unit 71. The other parts are the same as in FIG.

  Here, the frequency detector 70 detects the frequency of the input signal and notifies the constant multiplier 71. The constant multiplier 71 sets the value of ω included in the transfer function of the constant multiplier 71 according to the frequency of the input signal detected by the frequency detector 70.

  Next, the operation of the above second embodiment will be described. In the second embodiment, only the operations of the frequency detection unit 70 and the constant multiplication unit 71 are different from those of the first embodiment, and therefore, these portions will be mainly described.

  As shown in FIGS. 4 and 5, when the frequency of the input signal is different from the angular frequency ω set in the constant multiplier 71, the output signal V0 of the phase shifter 50 and the output signal V90 of the constant multiplier 52 Have different amplitudes. However, in the present embodiment, since the frequency detection unit 70 detects the frequency of the input signal and adjusts the value of ω included in the transfer function of the constant multiplication unit 71, for example, an angular frequency corresponding to 55 Hz (= 110π), even when a 50 Hz or 60 Hz signal is input, the amplitude of the output signal V0 of the phase shifter 50 and the amplitude of the output signal V90 of the constant multiplier 52 are the same. Is set to be For this reason, it is possible to prevent a ripple from occurring in the output of the adder 55. Further, if ω is set in real time, the occurrence of ripple can be prevented in the same manner even when the frequency of the power supply fluctuates due to an error.

  As described above, according to the second embodiment of the present invention, the frequency of the input signal is detected by the frequency detector 70 and included in the transfer function of the constant multiplier 71 according to the detected frequency. Since ω is set, it is possible to operate stably in eastern Japan and western Japan. Moreover, even when the frequency of the power supply fluctuates due to an error, it is possible to operate stably.

  Next, a power failure detection apparatus according to the third embodiment of the present invention will be described.

  7 and 8 are diagrams showing a configuration example of the power failure detection apparatus according to the third embodiment of the present invention. The first and second embodiments described above are configuration examples when the input signal is temporally continuous. However, the third embodiment is a configuration when the input signal is discrete in time. It is an example.

  FIG. 7 is a block diagram showing a configuration example of a power failure detection apparatus according to the third embodiment of the present invention. As shown in this figure, a power failure detection device 80 according to the third embodiment of the present invention includes a CPU (Central Processing Unit) 80a, a ROM (Read Only Memory) 80b, a RAM (Random Access Memory) 80c, an I / O It has an F (Interface) 80d, a bus 80e, a low-pass filter (LPF) 80f, and an A / D converter 80g.

  Here, the CPU 80a is a control circuit that controls each part of the apparatus in accordance with a control program 80b1 stored in the ROM 80b. The ROM 80b is a semiconductor storage device that stores a control program 80b1, other programs and data, and reads and supplies necessary programs or data in response to a request from the CPU 80a.

  The RAM 80c is a semiconductor memory device that temporarily stores programs and data being processed when the CPU 80a executes various arithmetic processes. The I / F 80d appropriately converts and inputs the data representation format supplied from the A / D converter 80h, and outputs a power failure detection signal to the outside.

  The bus 80e is a group of connection lines that connect the CPU 80a, the ROM 80b, the RAM 80c, and the I / F 80d to each other and exchange data among them.

  The low-pass filter 80f allows only a low-frequency component (component below the Nyquist frequency) included in the power supply voltage to pass, and blocks a higher-frequency component beyond that. The A / D converter 80g samples and holds the output signal of the low-pass filter 80f, converts it into a corresponding digital signal (discrete signal), and outputs it. The cut-off frequency of the low-pass filter 80f is set to, for example, about several k to several tens of kHz, and therefore is very large compared to several Hz that is the cut-off frequency of the low-pass filter shown in FIG. The response speed will not slow down.

  FIG. 8 is a diagram showing functional blocks realized when the control program 80b1 shown in FIG. 7 is executed. As shown in this figure, the functional block realized by the control program 80b1 includes phase shifters 90 and 91, a constant multiplier 92, multipliers 93 and 94, an adder 95, and a comparator 96.

  Here, the phase shifters 90 and 91, which are phase shift means, receive the discrete signal x (n) output from the A / D converter 80g, and adjust the phase of each signal so that the phase difference is 90 °. shift. Here, the transfer functions of the phase shifters 90 and 91 are expressed by the following equations 10 and 11. These transfer functions are obtained by bilinear transformation of Equation 2 and Equation 3, respectively. Here, T represents a sampling time, and Z is an operator for Z conversion.

A constant multiplier 92 as a constant multiplier inputs the output signal of the phase shifter 91, multiplies it by K (= ω _c / ω), and outputs it. The multiplier 93 which is a part of the calculation means squares the output signal of the phase shifter 90 and outputs it. The multiplication unit 94 which is a part of the calculation means squares the output signal of the constant multiplication unit 92 and outputs the result.

  The adder 95, which is a part of the arithmetic means, adds the output signal of the multiplier 93 and the output signal of the multiplier 94 and outputs the result. The comparator 96, which is a part of the detection means, compares the output of the adder 95 with the reference voltage Vref. If the output of the adder 95 is equal to or higher than the reference voltage Vref, the output is set to the high state. In this case, the state is low.

  Next, a flow of processing actually executed when the control program 80b1 is started will be described with reference to FIG. Note that the processing of this flowchart implements the processing of the block diagram shown in FIG. When the processing of the flowchart of FIG. 9 is started, the following steps are executed.

  Step S10: The CPU 80a takes in the sampling value x (n) of the input signal via the I / F 80d.

Step S11: The CPU 80a, based on the following Expression 12, inputs the input signal x (n), the input signal x (n-1) one cycle before, and the output signal y ₁ (one cycle before the phase shifter 90). n-1) to obtain y ₁ (n) which is an output signal of the phase shifter 90. Further, the CPU 80a, based on the following Expression 13, inputs the input signal x (n), the input signal x (n−1) one cycle before, and the output signal y ₂ (n one cycle before the phase shifter 91). -1) and y ₂ (n) which is an output signal of the phase shifter 91 is obtained.

Step S12: The CPU 80a multiplies y ₂ (n) that is the output signal of the phase shifter 91 by K (= ω _c / ω) that is the transfer function of the constant multiplier 92.

Step S13: The CPU 80a squares y ₁ (n) that is the output signal of the phase shifter 90, squares y ₂ (n) that is the output signal of the phase shifter 91, and adds the obtained results. Output P (n).

  Step S14: The CPU 80a determines whether or not the value of P (n) that is the output of the adder 95 obtained in step S13 is less than the value of the reference voltage Vref, and the value of P (n) is the reference voltage. If it is less than the value of Vref, the process proceeds to step S15, and otherwise, the process proceeds to step S16.

  Step S15: The CPU 80a determines that a power failure has occurred, and outputs a signal (a power failure detection signal) indicating that a power failure has occurred to the outside via the I / F 80d.

  Step S16: The CPU 80a determines that it is normal and ends the process.

  As described above, according to the third embodiment of the present invention, it is possible to quickly and reliably detect a power failure using the computer shown in FIG. For this reason, it is not necessary to use an expensive analog multiplier, so that the cost of the apparatus can be reduced.

  Next, a power failure detection apparatus according to the fourth embodiment of the present invention will be described.

  FIG. 10 is a diagram illustrating a configuration example of a power failure detection apparatus according to the fourth embodiment of the present invention. In this figure, parts corresponding to those in FIG. In the example of this figure, compared with the case of FIG. 1, a pulse width counter 100 is newly added. The other parts are the same as in FIG.

  Here, when the output of the comparator 56 is in a low state, the pulse width counter 100 which is a part of the detection means starts the count operation at the falling edge and ends the counting operation at the rising edge. Reset the count value. When the count value reaches a predetermined value, the output is set to a high state.

  Next, the operation of the fourth embodiment of the present invention will be described. In the fourth embodiment, only the operation of the pulse width counter 100 is different from that in the first embodiment, and this portion will be mainly described.

  Since the phase shifter 51 constitutes a kind of differentiation circuit, if noise is mixed in the input signal, it appears as a large signal in the output. Therefore, the comparator 56 may malfunction in response to such noise. However, since the width of the pulse signal of the comparator 56 in response to such noise is very narrow, malfunction is detected by detecting the pulse width with the pulse width counter and removing pulses below a certain set value. Can be prevented.

  FIG. 11 is a timing chart for explaining the operation of the pulse width counter 100. As shown in this figure, when the output signal of the comparator 56 becomes low only for the time T1, the pulse width counter 100 starts a count-up operation. However, since the counter set value indicated by the broken line is not reached, the power failure detection signal that is the output remains low.

  Further, when the output signal of the comparator 56 is in a low state only for the time T2, the pulse width counter 100 starts a count-up operation, but in this case as well, the counter set value indicated by the broken line is not reached. The power failure detection signal that is the output remains low.

  Further, when a power failure occurs and the output signal of the comparator 56 becomes low, the counter value exceeds the counter set value indicated by the broken line, so the power failure detection signal that is the output of the pulse width counter 100 is high. It becomes a state.

  As described above, since the pulse width counter 100 does not react to a pulse having a predetermined width or less, a malfunction due to noise can be prevented. Further, by changing the set value of the pulse width counter 100, it is possible to adjust the response time from when a power failure occurs until the power failure is detected.

12 and 13 are diagrams showing the results of a computer simulation of the fourth embodiment shown in FIG. FIG. 12 is a diagram illustrating a signal state between 0.00 ms and 40.00 ms when a power failure occurs at 30.00 ms. In this figure, _{e 1} indicates an input signal, _{e 2} represents the output signal of the phase shifter 50, _{e 3} shows an output signal of the constant multiplier section 52, _{e d} indicates the output signal of the adder 55, Vcom Indicates an output signal of the comparator 56, Vdet indicates an output signal of the pulse width counter 100, and Trigger indicates a trigger signal indicating the start of a power failure. FIG. 13 is an enlarged view showing the range of 29.00 to 31.00 ms shown in FIG.

In the example of FIGS. 12 and 13, ω _c = 20000 [rad / s] is set, and 200 μs is set as the setting value of the pulse width counter 100. As the input signal, a signal obtained by superimposing random noise on a sine wave is used. As shown in this figure, when noise is superimposed on the input signal, the output of the comparator 56 responds to the noise, but the output signal Vdet of the pulse width counter 100 is not erroneously detected.

  Further, when the input signal is cut off at the timing of 30 ms, this is detected at a response speed of about 300 μs. Although the counter set value is 200 μs, the response time is longer than the counter set value of 200 μs due to the relationship between the response time of the transfer function of the input stage (about 50 μs) and the setting level of the comparator 56.

  As described above, according to the fourth embodiment of the present invention, the pulse width counter 100 is connected to the output of the comparator 56 so as not to respond to a pulse signal having a predetermined width or less. Even when noise is mixed in, it is possible to prevent malfunction. Further, by setting the pulse width counter 100, the reaction time from the occurrence of a power failure until the power failure is detected can be arbitrarily set.

  Next, a fifth embodiment of the present invention will be described.

  FIG. 14 is a diagram illustrating a configuration example of the fifth exemplary embodiment of the present invention. As shown in this figure, the fifth embodiment of the present invention is configured as a power supply switching device including the power failure detection device 80 described above. That is, the power supply switching device includes a power failure detection device 80, a control unit 120, and a switch 121, and a first power supply 130, a second power supply 131, and a load 132 are connected to the outside thereof.

  Here, the power failure detection apparatus 80 has the same configuration as that of FIG. 7, for example. The control unit 120 switches the switch 121 according to the power failure detection signal supplied from the power failure detection device 80. The switch 121 serving as switching means is constituted by, for example, an electromagnetic switch, a semiconductor switch, or the like. When a power failure occurs in one power source, the connection is switched to the other power source.

  The first power supply 130 is, for example, a commercial power supply, and is a regular power supply. The second power supply 131 is a standby power supply, such as an uninterruptible power supply. The load 132 is, for example, a host computer.

  Next, the operation of the fifth embodiment of the present invention will be described.

  When a power failure occurs when the switch 121 is connected to the first power supply 130 that is the regular system, the power failure detection device 80 detects the power failure by the above-described operation. When a power failure is detected, the power failure detection device 80 supplies a power failure detection signal to the control unit 120. When receiving the supply of the power failure detection signal, the control unit 120 switches the connection of the switch 121 from the first power supply 130 that is the normal system to the second power supply 131 that is the standby system. As a result, when a power failure occurs in the first power supply 130, the power supply from the second power supply 131 can be continued.

  As described above, the power failure detection apparatus according to the present embodiment can detect the power failure within 500 μs at the latest, so that the switching from the first power supply 130 to the second power supply 131 is instantaneous when a power failure occurs. Will be done. As a result, it is possible to execute power supply switching without affecting the host computer that is the load 132.

  It is also possible to incorporate the power supply switching device shown in FIG. 14 in the uninterruptible power supply so that the commercial power supply is switched to the internal inverter output when a power failure occurs. Even in this case, it is possible to quickly switch the power supply when a power failure occurs.

  Each embodiment described above is a preferred example of the present invention, but the present invention is not limited to these, and various modifications and changes can be made without departing from the scope of the present invention. It is.

For example, in each of the above-described embodiments, the phase shifter 50 having a low-pass characteristic and the phase shifter 51 having a high-pass characteristic are used, but 20,000 is set in ω _c and a 50 Hz signal is converted. When input, the phase shift amount of the phase shifter 50 is less than 1 °. Therefore, the phase shifter 50 may be omitted, and a phase shift of 90 ° may be generated only by the phase shifter 51. In that case, the constant multiplier 52 may multiply the reciprocal value of Expression 7.

  In the third embodiment described above, the phase shifters 90 and 91 having the transfer functions of Expression 10 and Expression 11 are used. For example, the input signal x (n) is stored in the semiconductor memory, and the 90 It is also possible to delay by reading after the period corresponding to ° has elapsed.

  In the third embodiment described above, a continuous-time transfer function is converted into a discrete-time transfer function by bilinear conversion. For example, SZ such as LDI (Lossless Discrete Integrator) conversion is used. A transformation can also be used.

  Furthermore, in the above-described fifth embodiment, the case where two power sources are switched has been described, but the present invention can be applied to the case where there are three or more power sources.

  The above processing functions can be realized by a computer. In that case, a program describing the processing contents of the function that the power failure detection apparatus should have is provided. By executing the program on a computer, the above processing functions are realized on the computer. The program describing the processing contents can be recorded on a computer-readable recording medium. Examples of the computer-readable recording medium include a magnetic recording device, an optical disk, a magneto-optical recording medium, and a semiconductor memory. Examples of the magnetic recording device include a hard disk device (HDD), a flexible disk (FD), and a magnetic tape. Examples of the optical disk include a DVD (Digital Versatile Disk), a DVD-RAM (Random Access Memory), a CD-ROM (Compact Disk Read Only Memory), and a CD-R (Recordable) / RW (ReWritable). Magneto-optical recording media include MO (Magneto-Optical disk).

  When distributing the program, for example, portable recording media such as a DVD and a CD-ROM in which the program is recorded are sold. It is also possible to store the program in a storage device of a server computer and transfer the program from the server computer to another computer via a network.

  The computer that executes the program stores, for example, the program recorded on the portable recording medium or the program transferred from the server computer in its own storage device. Then, the computer reads the program from its own storage device and executes processing according to the program. The computer can also read the program directly from the portable recording medium and execute processing according to the program. In addition, each time the program is transferred from the server computer, the computer can sequentially execute processing according to the received program.

  The present invention can be used for a power failure detection device that detects the occurrence of a power failure.

It is a figure which shows the structural example of the power failure detection apparatus which concerns on the 1st Embodiment of this invention. When ω _c = 20000 and ω = 110π, a 55 Hz signal is input, and an operation when a power failure occurs at a phase where the input voltage is “0” is shown. FIG. (B) is a figure which expands and shows the part which the power failure generate | occur | produced in (A). When ω _c = 20000 and ω = 110π, a 55 Hz signal is input, and an operation when a power failure occurs at a phase where the input voltage is maximum is shown. (A) is an overall view, (B ) Is an enlarged view of a portion where a power failure has occurred in (A). In the case of ω _c = 20000 and ω = 110π, it is a diagram showing an operation when a power failure occurs at a phase where a 50 Hz signal is input and the input voltage is “0”, and FIG. (B) is a figure which expands and shows the part which the power failure generate | occur | produced in (A). When ω _c = 20000 and ω = 110π, a signal of 50 Hz is input, and an operation when a power failure occurs at a phase where the input voltage is maximum is shown. (A) is an overall view, (B ) Is an enlarged view of a portion where a power failure has occurred in (A). It is a figure which shows the structural example of the power failure detection apparatus which concerns on the 2nd Embodiment of this invention. It is a figure which shows the structural example of the power failure detection apparatus which concerns on the 3rd Embodiment of this invention. It is a figure which shows the functional block implement | achieved by the power failure detection apparatus shown in FIG. It is a flowchart for implement | achieving the process of the functional block shown in FIG. It is a figure which shows the structural example of the power failure detection apparatus which concerns on the 4th Embodiment of this invention. It is a figure for demonstrating operation | movement of the power failure detection apparatus shown in FIG. It is a figure explaining the operation | movement at the time of giving the input signal on which noise was superimposed to the power failure detection apparatus shown in FIG. It is the figure which expanded the part which the power failure generate | occur | produced of FIG. It is a figure which shows the structural example of the power failure detection apparatus which concerns on the 5th Embodiment of this invention. It is a figure explaining the conventional power failure detection device, (A) is a power failure detection device that converts alternating current into direct current, and (B) is provided with limits on the H side and the L side in relation to this. This is a power failure detection device that detects a power failure.

Explanation of symbols

50, 51 Phase shifter (phase shift means)
52 Constant multiplication part (constant multiplication means)
53, 54 Multiplier (part of calculation means)
55 Adder (part of multiplication means)
56 Comparator (part of detection means)
70 Frequency detector 90, 91 Phase shifter (phase shift means)
92 Constant multiplication part (constant multiplication means)
93, 94 Multiplier (part of calculation means)
95 Adder (part of multiplication means)
96 Comparator (part of detection means)
100 Pulse width counter (part of detection means)
121 selector switch (switching means)

Claims (5)

The first signal and the second signal having a predetermined phase difference are generated by shifting the phase by inputting the power supply voltage, and the phase difference between the first signal and the second signal is 90. Obtained by applying the power supply voltage to the first filter having the transfer function ωc / (s + ωc) and the second filter having the transfer function s / (s + ωc). the output voltage is then output as the first signal and the second signal, and the phase shift means further have a constant multiple means for outputting .omega.c / omega multiplying by the output signal from the second filter ,
Arithmetic means for executing an operation of squaring and adding each of the first signal and the second signal output from the phase shift means;
Detecting means for determining that a power failure has occurred when the output of the computing means is less than or equal to a predetermined threshold;
Having
A power failure detection device. In the power failure detection device according to claim 1,
The phase shift means changes the value of ω of the constant multiplication means according to the frequency of the power supply voltage.
A power failure detection device. The first signal and the second signal having a predetermined phase difference are generated by shifting the phase by inputting the power supply voltage, and the phase difference between the first signal and the second signal is 90. Obtained by applying the power supply voltage to the first filter having the transfer function ωc / (s + ωc) and the second filter having the transfer function s / (s + ωc). Phase shift means having constant multiplication means for outputting the output voltage as the first signal and the second signal, respectively, and further outputting the output signal from the second filter multiplied by ωc / ω,
  Arithmetic means for executing an operation of squaring and adding each of the first signal and the second signal output from the phase shift means;
  Detecting means for determining that a power failure has occurred when the output of the computing means is less than or equal to a predetermined threshold;
  When it is detected by the detection means that a power failure has occurred, switching means for switching to another power source,
  Having
  A power supply switching device characterized by that.   The first signal and the second signal having a predetermined phase difference are generated by shifting the phase by inputting the power supply voltage, and the phase difference between the first signal and the second signal is 90. Obtained by applying the power supply voltage to the first filter having the transfer function ωc / (s + ωc) and the second filter having the transfer function s / (s + ωc). Phase shift means having constant multiplication means for outputting the output voltage as the first signal and the second signal, respectively, and further outputting the output signal from the second filter multiplied by ωc / ω,
  Arithmetic means for executing an operation of squaring and adding each of the first signal and the second signal output from the phase shift means;
  Detecting means for determining that a power failure has occurred when the output of the calculating means is equal to or less than a predetermined threshold;
  When it is detected by the detection means that a power failure has occurred, switching means for switching to a backup power source; and
  Having
  An uninterruptible power supply.   The first signal and the second signal having a predetermined phase difference are generated by shifting the phase by inputting the power supply voltage, and the phase difference between the first signal and the second signal is 90. Obtained by applying the power supply voltage to the first filter having the transfer function ωc / (s + ωc) and the second filter having the transfer function s / (s + ωc). Phase shift means having constant multiplier means for outputting the output voltage as the first signal and the second signal, respectively, and further outputting the output signal from the second filter multiplied by ωc / ω,
  Arithmetic means for executing an operation of squaring and adding each of the first signal and the second signal output from the phase shift means;
  Detecting means for determining that a power failure has occurred when the output of the calculating means is equal to or less than a predetermined threshold;
  A computer-readable power failure detection program characterized by causing a computer to function as a computer.

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