JP4306428B2 - Pop noise reduction circuit - Google Patents

Description

  The present invention relates to a circuit for reducing pop noise that occurs when an audio amplifier is powered on.

  In general, an audio system has a problem that a so-called pop noise caused by an audio amplifier is generated at power-on, power-off, mute, or mute release. Therefore, various techniques for reducing this pop noise have been proposed.

For example, in the circuit shown in FIG. 6, a time constant circuit composed of resistors R1, R2 and a capacitor C2 is connected to a non-inverting input of an amplifier OP1 that receives and amplifies an audio signal with a non-inverting input, and the operation of the amplifier when the power is turned on The dots are slowly raised to reduce pop noise.
In the technique disclosed in Patent Document 1, a DA circuit and a switch circuit are used, and a voltage that rises or falls gradually (monotonically) for a predetermined time after bias-on and bias-off is supplied to the audio circuit. Thus, pop noise is prevented when the bias is turned on and when the bias is turned off.
In the technique disclosed in Patent Document 2, a DC voltage from a D / A converter that is program-controlled by a microprocessor is arbitrarily changed and applied to an amplifier gradually, thereby applying a DC voltage. In addition, the generation of click sound from an amplifier that mutes or unmutes the signal output is suppressed.
JP 59-133715 A JP 2002-314344 A

In the conventional example shown in FIG. 6, since pop noise appears when the time constant is reduced, it is necessary to increase the time constant of the time constant circuit, and the rise is slow.
Further, in the technique disclosed in Patent Document 1, the bias voltage is gradually increased or decreased (monotonically), but there is a portion that does not change gently immediately before and after the lapse of a predetermined time. Pop noise may occur when lowering.
The technique disclosed in Patent Document 2 also reduces pop noise, but does not take into account particularly fast startup.
Further, when the amplifier is a single power supply DC amplifier, the output voltage must be changed from 0 [V] when the power is turned on to ½ of the power supply voltage. there were.

  The present invention has been made in view of these points, and can reduce the pop noise generated when the audio amplifier is turned on or off, and can be quickly turned on and off. It is to provide a circuit.

The pop noise reduction circuit of the present invention includes an A / D converter that supplies output data obtained by analog / digital conversion of an output signal when an amplifier that amplifies an audio signal is turned on or off, and the output data is captured. A control means for supplying data for applying a bias voltage to the amplifier so that the output signal becomes a signal having a frequency below an audible band that cannot be reproduced by a reproduction speaker during reproduction according to the output data; A D / A converter that receives the data, converts the data to digital / analog, and supplies the data to the amplifier as the bias voltage.

Further, the present invention provides a pop noise reduction circuit described above, the data used when the power is turned on, the output signal of the amplifier, (VDD / 4) × ( 1-cos (2πft)), however, VDD is the supply voltage , T is an elapsed time (t = 0 to 1 / (2f)), and f is a frequency selected from frequencies below the audible band that cannot be reproduced by the reproduction speaker. It is characterized by.

Further, the present invention provides a pop noise reduction circuit described above, the correction data to be used for power-off, the output signal of the amplifier, (VDD / 4) × ( 1 + cos (2πft)), however, VDD is the supply voltage, t is an elapsed time (t = 0 to 1 / (2f)), and f is a frequency selected from frequencies below the audible band that cannot be reproduced by the reproduction speaker. It is a feature.

According to the configuration of the present invention , when the power is turned on or off, the bias voltage supplied to the amplifier is controlled so that the output of the amplifier is a signal having a frequency below the audible band that cannot be reproduced by the reproduction speaker during the reproduction. Therefore, there is no pop noise from the playback speaker. Furthermore, it is possible to start up and shut down faster than before.

The pop noise reduction circuit according to the present invention includes an up / down counter, a D / A converter for digital / analog converting the output of the up / down counter to an amplifier for amplifying an audio signal, and supplying the output as a bias voltage; When the amplifier is turned on or off, it receives the count value of the up / down counter, oscillates at a low frequency at the beginning of the up / down counter by the up / down counter, and gradually increases the oscillation frequency, It oscillates at the highest frequency in the middle of the count, and then gradually decreases the oscillation frequency to stop at the up-count MAX or the down-count MIN. And an oscillator for supplying to the down counter. .
According to this configuration, since the output change of the amplifier smoothly rises and falls, the occurrence of pop noise can be prevented even when the rise and fall are relatively fast.

Further, the pop noise reduction circuit of the present invention causes the up / down counter to down-count when the power is shut off, and the input of the amplifier to which an audio signal is input when the borrow output of the up / down counter becomes active A switch for grounding the terminal is further provided.
The borrow signal is an active signal when it becomes MIN (all 0) in the down count state of the up / down counter.
According to this configuration, since the amplifier input terminal is grounded when the control of the power supply cutoff of the amplifier is completed, even if an audio signal or noise is input thereafter, it is not amplified and reproduced.

  According to the present invention, it is possible to reduce pop noise generated when the audio amplifier is turned on or off, and at the same time, it is possible to quickly start up and shut down the audio amplifier.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
First, a pop noise reduction circuit according to a first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram showing a schematic configuration of an entire audio system including a pop noise reduction circuit according to the present embodiment.

Reference numeral 1 denotes an amplifier circuit (amplifier) that amplifies the audio signal, reference numeral 2 denotes a pop noise reduction circuit, and reference numerals 3 to 5 denote a signal source that outputs the audio signal, a coupling capacitor, and a speaker, respectively.
In this embodiment, the amplifier circuit 1 is composed of an amplifier 1a and resistors R1 and R2. One end of the resistor R1 is connected to a node for receiving an audio signal input, and the other end is connected to one end of the resistor R2 and the inverting input of the amplifier 1a. The other end of the resistor R2 is connected to the output of the amplifier 1a to constitute an inverting amplifier. A bias voltage is supplied from the following pop noise reduction circuit 2 to the non-inverting input of the amplifier 1a. Then, the output of the amplifier 1 a is reproduced as sound from the speaker 5 via the coupling capacitor 4.

The pop noise reduction circuit 2 includes an A / D converter 2a, a control unit 2b, a D / A converter 2c, and a memory 2d.
The A / D converter 2a performs analog / digital conversion on the output signal (output voltage) of the amplifier circuit 1 and supplies it to the control unit 2b. The A / D converter 2a only needs to be capable of detecting the output voltage of the amplifier circuit 1 and supplying the data to the control unit 2b. The control unit 2b is configured by a CPU (Central Processing Unit) or the like, and uses data (described later) stored in the memory 2d in accordance with a control program stored in the memory 2d, and data corresponding to the output of the amplifier circuit 1 Is supplied to the D / A converter 2c.

The D / A converter 2c performs digital / analog conversion on the data supplied from the control unit 2b, and supplies this to the amplifier circuit 1 as a bias voltage (here, supplied to the non-inverting input of the amplifier 1a). . The memory 2d stores the data and a control program for operating the control unit 2b.
The data stored in the memory 2d is D / A converted and supplied to the amplifier circuit 1 as a bias voltage. If the power is turned on, the time has elapsed since the power was turned on. On the other hand, this is data for controlling the output voltage of the amplifier circuit 1 so that the output of the amplifier circuit 1 is represented by the following equation (Equation 1: see FIG. 2).

(VDD / 4) × (1-cos (2πft)) (Formula 1)
However, VDD is a power supply voltage, t is an elapsed time (t = 0 to 1 / (2f)), and f is a frequency selected in advance from frequencies below the audible band that cannot be reproduced by the speaker 5 as a reproduction speaker. .

  Assuming that the DC voltage of the signal input to the amplifier circuit 1 is VINDC, the above data sets the output of the D / A converter 2c to VINDC × R2 / (R1 + R2) at t = 0 (at this time, the output of the amplifier circuit 1) The output of the D / A converter 2c is set to VDD / 2− (VDD / 2−VINDC) × R2 / (R1 + R2) at t = 1 / (2f) (at this time, the amplifier circuit 1) Output is VDD / 2), and during the period of t = 0 to t = 1 / (2f), the output of the amplifier circuit 1 is changed so as to draw the curve of the above equation.

The VINDC sequentially receives the output data of the amplifier circuit 1 supplied from the A / D converter 2a for each sampling period from t = 0 to t = 1 / (2f). It is calculated from the supplied bias voltage. In addition, here, the data is stored in the memory 2d and is used. Of course, the control unit 2b may calculate and output necessary data.
In the case of power shutdown, the following formula is used.

(VDD / 4) × (1 + cos (2πft)) (Formula 2)
However, VDD is a power supply voltage, t is an elapsed time (t = 0 to 1 / (2f)), and f is a frequency selected in advance from frequencies below the audible band that cannot be reproduced by the speaker 5 as a reproduction speaker. .

Next, the operation (when the power is turned on) of the pop noise reduction circuit 2 of the present embodiment configured as described above will be described.
First, when the system is powered on, a reset signal (not shown) is supplied to the control unit 2b, and the control unit 2b enters a reset state. At this time, data “0” is output from the control unit 2 b to the D / A converter 2 c, and 0 [V] is supplied as a bias voltage to the amplifier circuit 1.

  When the reset is released after the lapse of a predetermined time, the control unit 2b starts control from this time point (t = 0), and the output of the amplifier circuit 1 supplied from the A / D converter 2a at the time point t = 0. The data is received, and the DC voltage VINDC input to the amplifier circuit 1 at this time is obtained. At this point, data that makes the output of the D / A converter 2c equal to VINDC × R2 / (R1 + R2) is read from the memory 2d and supplied to the D / A converter 2c. The D / A converter 2 c receives the previous data from the control unit 2 b, converts it to digital / analog, and outputs a voltage value of VINDC × R 2 / (R 1 + R 2) as a bias voltage to the amplifier circuit 1. As a result, the output of the amplifier circuit 1 becomes 0 as described above.

  Thereafter, the control unit 2b sequentially reads data for supplying a bias voltage for changing the output of the amplifier circuit 1 as expressed by Equation 1 from the memory 2d and supplies the data to the D / A converter 2c. On the other hand, the D / A converter 2 c converts the data received from the control unit 2 b from digital to analog and outputs the data as a bias voltage to the amplifier circuit 1. As a result, the output of the amplifier circuit 1 changes as shown in FIG. Finally (at time t = 1 / (2f)), as a bias voltage, VDD / 2− (VDD / 2−VINDC) × R2 / (R1 + R2) is supplied to the amplifier circuit 1, and the amplifier circuit 1 Outputs VDD / 2. In the case of power-off, the power-off is detected separately (for example, the off state of the power switch is detected), and starting from this point (t = 0), in this case, the same as the above based on the above equation 2 (By this control, the bias voltage supplied to the amplifier circuit 1 varies from VDD / 2− (VDD / 2−VINDC) × R2 / (R1 + R2) to VINDC × R2 / (R1 + R2)).

  As described above, by the control by the pop noise reduction circuit 2, the amplifier circuit 1 supplies an output signal approximated to the expression 1 when the power is turned on and to the speaker 5 when the power is turned off. . In each of the above formulas, f is a frequency selected in advance from frequencies below the audible band that cannot be reproduced by the reproduction speaker, so that no sound is reproduced from the speaker 5. Therefore, pop noise does not occur when the power is turned on and when the power is turned off. In addition, by appropriately selecting f in the above formulas 1 and 2 and performing the control in the present embodiment, the amplifier circuit 1 can be started up and shut down earlier than the conventional circuit for reducing pop-up noise. This is shown by simulation.

  The control unit 2b used for the pop noise reduction circuit 2 is configured by a CPU (central processing unit) or the like, and is reset when the power is turned on, but the reset is released earlier than the rise of the amplifier circuit 1. Therefore, as described above, control is started from the reset release time (t = 0). Further, when the amplifier circuit 1 and the pop noise reduction circuit 2 are separate power sources and the pop noise reduction circuit 2 is functioning in advance, the power-on on the amplifier circuit 1 side is detected, and at the time of detection (t = 0) The above-described control is started.

  Next, a pop noise reduction circuit according to a second embodiment of the present invention will be described with reference to FIG. FIG. 3 is a block diagram showing a schematic configuration of the entire audio system including the pop noise reduction circuit of the present embodiment.

In the following description, a configuration using a 3-bit up / down counter will be described for the sake of simplicity. However, it is preferable to use a configuration using an 8-bit up / down counter.
Reference numeral 1 shown in FIG. 3 is an amplifier circuit (amplifier) that amplifies the audio signal, reference numeral 6 is a pop noise reduction circuit, and reference numerals 3 to 5 are a signal source that outputs the audio signal, a coupling capacitor, and a speaker, respectively. .

  The amplifier circuit 1 also includes an amplifier 1a and resistors R1 and R2 in the present embodiment as in the first embodiment. One end of the resistor R1 is connected to a node for receiving an audio signal input, and the other end is connected to one end of the resistor R2 and the inverting input of the amplifier 1a. The other end of the resistor R2 is connected to the output of the amplifier 1a to constitute an inverting amplifier. Further, a bias voltage is supplied from the following pop noise reduction circuit 6 to the non-inverting input of the amplifier 1a. The output of the amplifier 1a is reproduced as sound from the speaker 5 via the coupling capacitor 4.

The pop noise reduction circuit 6 includes an up / down counter 6a, a D / A converter 6b using a buffer BUF and an R-2R ladder resistor, a bypass capacitor C1, a switch SW, a NOR circuit X1, and an oscillation circuit 6d.
The up / down counter 6a is switched between up-counting and down-counting according to the ON / OFF signal. Also, it is initialized by the CLEAR signal (output is set to 0). The ON / OFF signal and the CLEAR signal are supplied by another circuit (not shown) (reset circuit or the like). When the power is turned on, the CLEAR signal is supplied to the up / down counter 6a to perform initialization, and the ON / OFF signal = 1 ( High) starts up counting. When the power is shut off, down-counting is started by ON / OFF signal = 0 (Low).

In the D / A converter 6b, the buffer BUF receives an ON / OFF signal, and performs digital / analog conversion of the counter output of the up / down counter 6a in each of the up-count and down-count (counter output becomes 0 to full scale). The output is supplied to the amplifier circuit 1 as a bias voltage. Note that the power supply of the buffer BUF uses the same voltage as the power supply (VDD) of the amplifier circuit 1.
The NOR circuit X1 outputs the CAL output of the up / down counter 6a (carry output: ON / OFF signal = 1 (up count) and becomes active when the counter value becomes full scale (all 1)) and BOL output (borrow output). (ON / OFF signal = 0 (down count) and becomes active when the counter value becomes 0)), and the NOR output is supplied to the oscillation circuit 6d as a transmission control signal.

  The switch SW receives the BOL output of the up / down counter 6a, and when this signal is active (that is, when the down-counting is completed and the process at the time of power-off is completed), the signal input terminal (inverted input terminal) of the amplifier 1a Is grounded, otherwise ungrounded. The BOL output of the up / down counter 6a connected to the amplifier 1a is for powering down the amplifier.

  The decoder 6c receives the binary output (Q1, Q2, Q3) of the up / down counter 6a and, as shown in FIG. 4, according to the up count or down count of the up / down counter 6a (S1, S2 , S3) = (0,0,0) → (0,0,1) → (0,1,0) → (1,0,0) → (1,0,0) → (0,1,0) ) → (0,0,1) → (0,0,0).

The oscillation circuit 6d oscillates / stops according to the transmission control signal supplied from the NOR circuit X1 and oscillates at an oscillation frequency according to the counter output of the up / down counter 6a.
The oscillation circuit 6d is a well-known oscillation circuit that uses a two-input Schmitt trigger NAND circuit N1 (hereinafter referred to as a NAND circuit N1). And four resistors R3, R4, R5, and R6 connected to the capacitor C2 and a capacitor C2.

  In the oscillation circuit 6d, the output of the NAND circuit N1 is connected to one end of the resistor R3, and the other end of the resistor R6 is connected to one input of the NAND circuit N1 together with one end of the capacitor C2. The other end of the capacitor C2 is grounded. The switch SW1 is provided between the resistors R3 and R4 and the output of the NAND circuit N1, the switch SW2 is provided between the resistors R4 and R5 and the output of the NAND circuit N1, and the switch SW3 is provided between the resistors R5 and R5. , R6 and the output of the NAND circuit N1, the switches SW1, SW2, SW3 are controlled to be opened and closed by the outputs (S1, S2, S3) of the decoder 6c. That is, the combined resistance value is changed by opening and closing these switches, and the oscillation frequency is changed.

  The other input of the NAND circuit N1 is supplied with an oscillation control signal from the NOR circuit X1, and oscillates when the transmission control signal is “1” and stops oscillating when the transmission control signal is “0”. The switches SW, SW1 to SW3 are turned on when the signal for controlling them is “1” and turned off when the signal is “0”.

Next, the operation (when power is turned on) of the pop noise reduction circuit 6 of the present embodiment configured as described above will be described.
Before the power is turned on, the BOL output is active from the up / down counter 6a (at this time, the output of the up / down counter 6a is all 0 and the ON / OFF signal = 0 (Low)). The inverting input terminal of the amplifier 1a is grounded by the switch SW. At this time, the bias voltage is also 0, and its output is 0 [V].

  Here, it is assumed that the system is powered on. Then, a CLEAR signal is supplied from another circuit (not shown) to the up / down counter 6a, and initialization is performed. Since the up / down counter 6a outputs all 0, the output of the decoder 6c is also all 0 as shown in FIG. 4, and all the switches SW1, SW2 and SW3 of the oscillation circuit 6d are opened. Further, when the ON / OFF signal = 1 (High) is supplied to the up / down counter 6a, the BOL output becomes inactive (at this time 0 (Low)). At this time, since the CAL output is inactive (= 0), the output of the NOR circuit X1 becomes 1 (High), and the oscillation circuit 6d receiving this as an oscillation control signal oscillates at the lowest frequency. The up / down counter 6a receives the clock signal from the oscillation circuit 6d and starts up-counting when the CLEAR signal becomes inactive.

On the other hand, the switch SW receives an input signal that is opened (switched off) by the BOL output that has become inactive due to the ON / OFF signal = 1 (High).
The up / down counter 6a counts up from the counter value 0, but the counter output is supplied to the D / A converter 6b and the decoder 6c. A bias voltage (see FIG. 5A) that gradually increases from 0 [V] is supplied from the D / A converter 6b to the amplifier circuit 1 (here, the non-inverting input of the amplifier 1a). On the other hand, the decoder 6c receives the counter output of the up / down counter 6a, and outputs in accordance with this (see FIG. 4), and controls the opening / closing of the switches SW1, SW2 and SW3 of the oscillation circuit 6d.

  The oscillation circuit 6d is in a state in which only the switch S1 is closed (S1: ON; oscillation circuit 6d) from a state in which all the switches SW1, SW2, SW3 are open at the time of power-on (the oscillation circuit 6d oscillates at the lowest frequency). Oscillates at the second lowest frequency), only the switch S2 is closed (S2: ON; the oscillation circuit 6d oscillates at the second highest frequency), and only the switch S3 is closed (S3: ON; the oscillation circuit 6d is the most Similarly, only the switch S3 is closed (S3: ON; the oscillation circuit 6d oscillates at the highest frequency), and only the switch S2 is closed (S2: ON; the oscillation circuit 6d is the second highest frequency). Oscillation), only the switch S1 is closed (S1: ON; the oscillation circuit 6d oscillates at the second lowest frequency), and the output of the up / down counter 6a is Le scale output all zero decoder 6c when it becomes (all 1) and a state where the switches SW1, SW2, SW3 are opened all (oscillation circuit 6d oscillation at the lowest frequency) transitions to.

  In this way, the oscillator 6d oscillates at the lowest frequency at the beginning of the up count by the up / down counter 6a, gradually increases the oscillation frequency according to the count, and oscillates at the highest frequency in the middle of the count, Then gradually decrease the oscillation frequency. At the end of the up-count (at full scale), the CAL (carry) output becomes active (High), the output of the NOR circuit X1 becomes 0 (Low), and the oscillation of the oscillation circuit 6d stops. Since the oscillation output of the oscillator 6d is supplied as a clock signal to the up / down counter 6a, the counting speed is also the slowest at the start of counting, gradually increasing the counting speed, and counting at the maximum speed between the counting and the counting. Then gradually reduce the counting speed and stop counting at full scale.

  The output of the up / down counter 6a thus counted is digital / analog converted by the D / A converter 6b and supplied to the amplifier circuit 1 (the non-inverting input of the amplifier 1a) as described above. Therefore, as shown in FIG. 5A, the bias voltage supplied to the amplifier circuit 1 has a small change from 0 [V] immediately after the power is turned on, rises relatively rapidly in the middle, and thereafter changes. The change is expressed by a gentle curve with the degree reduced, and the up-count MAX becomes VDD / 2 (when the DC component VINDC of the audio signal of the amplifier circuit 1 is VDD / 2, the output of the amplifier circuit 1) Will also be VDD / 2).

  In the above description, the count is initialized by the CLEAR signal and the up-count is started from 0. However, it is also possible to load an arbitrary initial value and start the count in the middle. For example, when the resistance values of R1 and R2 of the amplifier circuit 1 are equal, the count is started and the bias voltage is changed so that the initial value of the bias voltage becomes VDD / 4 (see FIG. 5B). When the DC component VINDC of the audio signal of the amplifier circuit 1 is VDD / 2, the output of the circuit 1 changes from 0 [V] to VDD / 2 in the same manner as in the previous case.

  The operation when the power is turned on has been described. When the power is shut off, the down / counting starts when the output of the up / down counter 6a receives the ON / OFF signal = 0 (Low) from the full scale state. The bias voltage supplied to the amplifying circuit 1 changes gradually from VDD / 2 to 0 at first, drops rapidly in the middle, and gradually changes when approaching 0. On the other hand, at the MIN of the down count, the BOL output becomes active, the switch SW is closed, and the inverting input terminal (signal input terminal) of the amplifier 1a is grounded. On the other hand, a transmission control signal (= 0) is supplied from the NOR circuit X1 to the NAND circuit N1 of the oscillation circuit 6d to stop the oscillation.

  In the present embodiment, as described above, when the power is turned on and when the power is turned off, the bias voltage represented by the gentle and rapid curve as described above is supplied to the amplifier circuit 1, and the gentle output change is similarly performed. By doing so, pop noise can be reduced and the processing can be completed in a short time. In addition, the pop noise reduction circuit 6 part excluding the D / A converter 6b and the amplifier circuit 1 part are provided as separate power sources, or a time difference is provided between the rise and fall of each power source when the power is turned on and when the power is turned off. The above control is performed so that the pop noise reduction circuit 6 functions before the amplifier circuit 1 when the power is turned on and stops functioning later when the power is cut off.

The embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and includes a configuration that does not depart from the gist of the present invention.
The present invention is suitable when applied to a DC amplifier using a single power source other than the amplifier circuit 1 shown in the above embodiment. Further, depending on the configuration of the amplifier circuit, the change in the output of the amplifier circuit may correspond to a curve obtained by slightly changing the curve represented by the above-described Expression 1 or Expression 2.

  In the second embodiment, the decoder 6c and the oscillation circuit 6d having a variable oscillation frequency change the oscillation as described above when the amplifier is turned on or off, and the output is increased / reset as a clock signal. The oscillator that supplies the down counter is configured. An oscillation circuit that oscillates at a fixed frequency, and a conversion table that causes a change in the bias voltage as described above between the up / down counter and the D / A converter. You may make it comprise.

1 is a block diagram showing a schematic configuration of an entire audio system including a pop noise reduction circuit according to a first embodiment of the present invention. It is a figure which shows the waveform of the amplifier output voltage output by control of the pop noise reduction circuit of the embodiment. It is a block diagram which shows schematic structure of the whole audio system containing the pop noise reduction circuit of the 2nd Embodiment of this invention. It is a figure which shows the input-output conversion of the decoder in the embodiment. It is a figure which shows the waveform of the amplifier output voltage output by control of the pop noise reduction circuit of the embodiment. It is a block diagram which shows schematic structure of the whole audio system containing the conventional pop noise reduction circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Amplifier circuit (amplifier), 1a ... Amplifier, 2 ... Pop noise reduction circuit, 2a ... A / D converter, 2b ... Control part (control means), 2c ... D / A converter, 2d ... Memory, 3 ... Signal source, 4 ... coupling capacitor, 5 ... speaker, 6 ... pop noise reduction circuit, 6a ... up / down counter, 6b ... D / A converter, 6c ... decoder (part of oscillator), 6d ... oscillation circuit ( Part of the oscillator)

Claims (2)

Up / down counter,
A D / A converter that converts the output of the up / down counter to digital / analog and supplies it as a bias voltage to an amplifier that amplifies the audio signal;
When the amplifier is turned on or off, it receives the count value of the up / down counter, oscillates at a low frequency at the beginning of the up / down counter by the up / down counter, and gradually increases the oscillation frequency, It oscillates at the highest frequency in the middle of the count, and then gradually decreases the oscillation frequency to stop at the up-count MAX or the down-count MIN. A pop noise reduction circuit comprising: an oscillator for supplying to a down counter. A switch for grounding the input terminal of the amplifier to which an audio signal is input when the up / down counter is down-counted when the power is cut off and the borrow output of the up / down counter becomes active; The pop noise reduction circuit according to claim 1 .

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