JP4345245B2 - Address conversion circuit and address conversion method used therefor - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an address conversion circuit and an address conversion method used therefor, and more particularly to a storage device used for a conversion operation such as an address conversion from a logical address to a physical address.
[0002]
[Prior art]
The address conversion from the logical address to the physical address during communication between the processors needs to be performed based on the correspondence between the logical address and the physical address set by the OS (Operating System).
[0003]
In order to perform communication between processors without a system call, it is necessary to use a logical address as a memory address for protection, and an address conversion operation is essential.
[0004]
Correspondence between the logical address and the physical address is performed in units of pages. The physical page number corresponding to a certain logical page number is written in the address conversion table. By converting the part of the logical address into the logical page number and drawing the above address conversion table, the physical page number is converted. obtain.
[0005]
However, as the amount of data used for calculation increases, the number of bits used for logical addresses increases and the space of logical page numbers becomes very large.
[0006]
Therefore, it is not possible to have all the address conversion tables in the communication device, and address conversion is performed by caching a part of the address conversion table in the main memory in the communication device as necessary.
[0007]
The configuration of the conversion table memory used in the conventional method is shown in FIG. In FIG. 3, the conversion table memory 200 stores a logical page number 201 and a corresponding physical page number 202.
[0008]
If the logical page number to be converted exists in this conversion table memory 200, address conversion is performed using the corresponding physical page number. If the conversion table memory 200 does not have a logical page number to be converted, the physical page number corresponding to the logical page number is read out and stored in the conversion table memory 200 by referring to the page table in the main memory. Address conversion is performed in
[0009]
[Problems to be solved by the invention]
In the conventional address translation method described above, the overhead of the address translation described above becomes the overhead of inter-processor communication. Therefore, as many correspondence entries as possible between the logical page number and the physical page number can be reduced to reduce the overhead. Cache to reduce access to the main memory page table.
[0010]
However, since the combination of the logical page number and the corresponding physical page number is stored as it is, the space for the logical page number becomes large and a very large storage capacity is required for the conversion table memory.
[0011]
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to solve the above problems and provide an address conversion circuit capable of caching a large amount of address conversion information in an address conversion circuit in a communication apparatus and an address conversion method used therefor. .
[0012]
[Means for Solving the Problems]
An address conversion circuit according to the present invention is an address conversion circuit for converting a logical address to a physical address, and includes a programmable logic circuit capable of configuring an arbitrary logical circuit by changing a program, and the logical address and the The conversion rule with the physical address is realized as a logic circuit of the programmable logic circuit.
[0014]
An address conversion method according to the present invention is an address conversion method for converting a logical address to a physical address, and by supplying a program to a programmable logic circuit capable of configuring an arbitrary logic circuit by changing the program, The conversion rule between the logical address and the physical address is realized as a logic circuit of the programmable logic circuit.
[0015]
That is, in the address conversion table used for inter-processor communication, pages used for inter-processor communication are often pasted to the main memory until the end of communication, and the frequency of rewriting the contents is low. In the address conversion table, physical pages are assigned to logical page numbers by the OS, and continuous physical page areas are often assigned in the OS page management method.
[0016]
In the address translation table with such features, programmable logic that can configure an arbitrary logic circuit by programming something like its rule, rather than remembering the logical page number and the corresponding physical page number as it is By programming the circuit and configuring and storing as a logic circuit, the address conversion table can be stored more efficiently.
[0017]
As described above, by efficiently holding the address conversion table, it is possible to reduce the number of read accesses corresponding to the logical page number and the physical page number to the main memory as much as possible.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an interprocessor communication system according to an embodiment of the present invention. 1, the inter-processor communication system according to an embodiment of the present invention is a parallel computer system in which a plurality of processors 1-1 to 1-n are connected to a network 100. Each of the processors 1-1 to 1-n includes a CPU 2, a main storage device 3, a transmission device 4, and a reception device 5.
[0019]
The transmission device 4 sends to the network 100 a command register 41 that holds a command instructing transmission, an address conversion circuit 42 that converts a logical address indicating transmission data 31 on the main storage device 3 into a physical address, and the like. And a packet generation circuit 45 for generating a packet.
[0020]
The receiving device 5 has a write address register 51 that holds a write address of a packet coming from the network 100, an address conversion circuit 53 that converts the write address from a logical address to a physical address, and data that writes received data 32 to the main storage device 3. And a writing circuit 52.
[0021]
The address conversion circuit 42 of the transmission device 4 and the address conversion circuit 53 of the reception device 5 are respectively provided with programmable logic circuits 43 and 54 and program memories 44 and 55 for holding the programs.
[0022]
The main storage device 3 stores a page table 33 indicating correspondence between logical addresses and physical addresses for address conversion, and a program 34 for programmable logic circuits 43 and 54 converted based on the page table 33. The program 34 is loaded into the program memories 44 and 55, respectively.
[0023]
With reference to FIG. 1, a procedure for transmitting a packet in an interprocessor communication system according to an embodiment of the present invention will be described.
[0024]
A command for requesting transmission is stored in the command register 41. The command includes a read address indicating the address of the transmission data, converted from a logical address to a physical address by the address conversion circuit 42 and passed to the packet generation circuit 45. The packet generation circuit 45 reads the transmission data 31 on the main storage device 3 to create a packet, and sends it to the network 100.
[0025]
Next, a procedure for receiving a packet in an interprocessor communication system according to an embodiment of the present invention will be described.
[0026]
The received packet includes a write address, and the write address is stored in the write address register 51. The write address designated by the logical address stored in the write address register 51 is converted into a physical address by the address conversion circuit 53, and the data write circuit 52 writes the received data 32 onto the main memory 3.
[0027]
In the address conversion circuits 42 and 53, the logical page number of the upper part of the logical address is given as an input to the programmable logic circuits 43 and 54, and the physical page number is outputted as the output. In this embodiment, the correspondence between the logical page number and the physical page number is realized as a logical circuit constituted by the programmable logic circuits 43 and 54.
[0028]
FIG. 2 is a diagram showing a procedure for generating a program for the programmable logic circuits 43 and 54 from the page table 33 according to an embodiment of the present invention. With reference to FIG. 2, a description will be given of a procedure for making the address translation information into the program of the programmable logic circuits 43 and 54 according to the embodiment of the present invention.
[0029]
First, a page table 33 which is a correspondence table between the logical page number 101 and the physical page number 102 is created by an OS (Operating System) (not shown). A rule 103 is created from the information in this page table 33. In this example, logical page numbers 0x0000 to 0x1fff and 0x8000 to 0x9fff are mapped to physical page areas that are continuous with physical addresses.
[0030]
That is, as rule 103, “if logical page number is 0x0000 to 0x1fff, physical page number = logical page number + 0x1000”, “if logical page number is 0x8000 to 0x9fff, physical page number = logical page number−0x4000” is created. Is done.
[0031]
Finally, this rule 103 is converted into a program 104 representing a logic circuit realized by the programmable logic circuits 43 and 54. That is, as the program 104, a comparator 105 that compares the logical page number and 0x0000, a comparator 106 that compares the logical page number and 0x1fff, a comparator 107 that compares the logical page number and 0x8000, and a comparator The programmable logic circuit 43 includes a selector (SEL) 108 that outputs “0x1000” or “−0x4000” in accordance with the comparison results 105 to 107, and an adder 109 that adds the output of the selector 108 to the logical page number. , 54 as a logic circuit.
[0032]
The program 104 converted by the above processing is stored on the main storage device 3 and loaded as the program 34 into the program memories 44 and 55 of the address conversion circuits 42 and 53 of the transmission device 4 and the reception device 5.
[0033]
When the logical page number is in a range that cannot be converted by the address conversion circuits 42 and 53, the address conversion circuits 42 and 53 generate an interrupt to the CPU 2 and information on the new page table 33 on the main storage device 3 A program 34 is created based on the above and loaded into the program memories 44 and 55.
[0034]
As described above, by realizing the conversion rule between the logical address and the physical address as the logic circuit of the programmable logic circuits 43 and 54, it is possible to cache a large amount of address conversion information in the address conversion circuits 42 and 53. When the pages are assigned such that the physical page numbers are continuous, it is possible to cache the address translation information of a very large number of logical pages in the address translation circuits 42 and 53.
[0035]
【The invention's effect】
As described above, according to the present invention, in an address conversion circuit for converting a logical address to a physical address, a program is supplied from a program memory to a programmable logic circuit capable of configuring an arbitrary logical circuit by changing the program. By implementing the conversion rule between the logical address and the physical address as the logic circuit of the programmable logic circuit, it is possible to cache a large amount of address conversion information in the address conversion circuit in the communication device. .
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of an interprocessor communication system according to an embodiment of the present invention.
FIG. 2 is a diagram showing a procedure for generating a program of a programmable logic circuit from a page table according to an embodiment of the present invention.
FIG. 3 is a diagram showing a configuration of a conversion table memory of a conventional address conversion circuit.
[Explanation of symbols]
1-1 to 1-n Processor 2 CPU
3 Main storage device 4 Transmission device 5 Reception device 31 Transmission data 32 Reception data 33 Page table 34 Program 41 Command register 42, 53 Address conversion circuit 43, 54 Programmable logic circuit 44, 55 Program memory 44 Packet generation circuit 51 Write address register 52 Data write circuit 100 Network 101 Logical page number 102 Physical page number 103 Rule 104 Logic circuit program 105-107 Comparator 108 Selector 109 Adder

Claims (6)

An address conversion circuit for converting a logical address to a physical address, comprising a programmable logic circuit capable of configuring an arbitrary logical circuit by changing a program, and having a conversion rule between the logical address and the physical address An address conversion circuit realized as a logic circuit of the programmable logic circuit. 2. The programmable logic circuit according to claim 1, wherein when a logical page number forming a part of the logical address is input, the programmable logic circuit is programmed to output a physical page number corresponding to the logical page number. Address translation circuit. Means for generating a program for converting the logical page number into the physical page number when the logical page number is in a range that cannot be converted into the physical page number by the programmable logic circuit; 3. The address conversion circuit according to claim 2, wherein: An address conversion method for converting a logical address to a physical address, wherein the program is supplied to a programmable logic circuit capable of configuring an arbitrary logic circuit by changing the program, whereby the logical address, the physical address, An address conversion method characterized in that the conversion rule is realized as a logic circuit of the programmable logic circuit. 5. The programmable logic circuit according to claim 4, wherein when a logical page number forming a part of the logical address is inputted, the programmable logic circuit is programmed to output a physical page number corresponding to the logical page number. Address translation method. When the logical page number is in a range that cannot be converted into the physical page number by the programmable logic circuit, a program for enabling the logical page number to be converted into the physical page number is generated. 6. The address conversion method according to claim 5, wherein:

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