JP3665349B2 - Integrated circuit - Google Patents

Description

上記した実施例では３２ビットのアドレスを有する集積回路について説明したが、本発明は３２ビットの場合に拘らず１６ビット、６４ビットのアドレスバスを持つ集積回路の場合でも構わない。また、今回は３２ビットを上位１６ビット、下位１６ビットに等分割したが、例えば、上位８ビット、下位２４ビットの様に分割しても本発明は同様の効果を有する。
【００３９】
【発明の効果】
以上説明したように、本発明では、集積回路内のアドレスの一部を格納するレジスタをＣＰＵブロック側およびメモリブロック側の両方に設け供給されるアドレスの一部に対応するビット数の分に対応する（ＣＰＵブロックとメモリブロック間を結ぶ）アドレスバスの幅を減少させる。これにより、集積回路のピン数を減少することができ、集積回路の各ブロックのパット数を減少することができるので、パッケージコストを下げることができ、結果として集積回路の製造コストを下げることができかつ集積回路の高集積化に貢献することができる。また、供給されたアドレスの一部はレジスタ内に格納され、次に供給されるアドレスの一部がレジスタ内に格納されているアドレスと一致した場合は、レジスタ内のアドレスを利用することにより、アドレスバス内のビット数を減少したことに伴うメモリアクセスに必要なクロック数の増加を防ぐことができ、即ち処理ビット数能力を減少させることなく、メモリアクセスを実行できる集積回路を提供することができる。
【図面の簡単な説明】
【図１】本発明の第１実施例である集積回路の構成図である。
【図２】図１に示す集積回路の動作を示したタイミング図である。
【図３】本発明の第２実施例である集積回路の構成図である。
【図４】図２に示す集積回路の動作を示したタイミング図である。
【図５】従来例としての集積回路の構成図である。
【図６】図５に示す集積回路の動作を示したタイミング図である。
【符号の説明】
１，３０ 集積回路
２，３１ ＣＰＵブロック
３，３２ メモリブロック
６ ３２ビット上位アクセスレジスタ
８，１２，３４，３３，４０，４１ １６ビット上位アドレス保持レジスタ
９，３６，３７ 比較器
１０，４２ 入力セレクタ
１１，３５，３９ 出力セレクタ
１３ メモリ[0001]
[Industrial application fields]
The present invention relates to an integrated circuit, and more particularly, to an integrated circuit architecture including a microprocessor, a peripheral LSI, a DSP, a memory, and the like.
[0002]
[Prior art]
The address width of an integrated circuit composed of a current microprocessor, peripheral LSI, DSP (digital signal processor), etc. generally tends to increase as the amount of data handled increases. In general, in an integrated circuit using a microprocessor, instructions and data are often stored at successive addresses in a memory (hereinafter referred to as “data localization”). In other words, a rare case where the microprocessor accesses randomly all the addresses, generated many when accessing instructions and data that are usually specified by continuous addresses. In this case, the upper bits of the address hardly change.
[0003]
Hereinafter, conventional techniques and problems will be described with reference to FIGS. FIG. 5 is a schematic block diagram of a conventional integrated circuit, and FIG. 6 is a timing diagram of data transferred on the address bus of the integrated circuit of FIG.
[0004]
In FIG. 5, an integrated circuit 50 includes a microprocessor (CPU) 52 and a memory 56 as an external storage device. Here, the case of the integrated circuit 50 having an address width of 32 bits will be described. The CPU 52 and the memory 56 are connected by an address bus 58 having a 32-bit width and exchange data with each other. In general, the microprocessor 52 performs several types of memory access for operand read, operand write, instruction fetch, etc. Here, for the sake of simplicity of explanation, the case of operand read will be described. As shown in FIG. 6, in the first clock, the address 00000000H (H represents a hexadecimal number; the same applies hereinafter) is transferred from the address register 54 via the address bus 58 to the memory 56. Thereafter, in the second clock, the content A at the address 00000000H in the memory 56 is read (the reading destination is not shown). At the next third clock, the address register 54 outputs a 32-bit wide address 000000004H to the memory 56 via the address bus 58. Similarly, at the fourth clock, the contents B of the address 00000004H in the memory 56 is read. It will be. Similarly, in the subsequent clock, the data C in the memory 56 corresponding to the address 00000008H stored in the address register 54 is changed to the data D in the memory 56 corresponding to the address FFFFFFFF8H stored in the address register 54. data E of the address registers in memory 56 corresponding to the stored address FFFFFFF8H in 54, the data F in the memory 56 corresponding to the address 0000000CH stored in the address register 54, is stored in the address register 54 Data G in the memory 56 corresponding to the address 00000010H is read in synchronization with the clock. The relationship between the address and clock transferred to the address bus 58 for reading the data in the memory 56 is shown below.
[0005]
Clock transfer address (on address bus)
1 00000000H
2 00000004H
3 00000008H
4 FFFFFFF8H
5 FFFFFFFCH
6 0000000CH
700000001H
As described above, for example, only the lowest nibble changes in each transfer address from the first clock to the third clock, and the other nibbles have the same value. The same applies to the clocks 4 and 5 and the clocks 6 and 7.
[0006]
As described above, the value of the upper bit (address value to be transferred) of the address bus of the conventional integrated circuit is often not changed, in other words, the value of the least significant bit or nibble is often changed. . Nevertheless, dedicated signal pins corresponding to all bits of the address bus are prepared and output to the outside of the integrated circuit, for example, the memory in the above example, via these pins.
[0007]
[Problems to be solved by the invention]
Therefore, the following problems existed in the conventional integrated circuit.
[0008]
(A) As the number of bits of the address bus width increases, the number of pins of the package for assembling the integrated circuit increases, and the package cost and thus the manufacturing cost of the integrated circuit increase.
[0009]
(B) When a computer board is created using an integrated circuit, the area occupied by the address bus with respect to the area of the entire board increases, and therefore the mounting density of the entire board decreases.
[0010]
(C) The number of pads for the address bus increases or decreases according to the increase or decrease of the address bus width. Therefore, pads are also created for bit lines of address buses whose values do not change frequently. This means that the pointless area, i.e. the area for bit lines that are not frequently used, increases on the integrated circuit. That is, a pad neck is generated. This has a greater effect as the area of the integrated circuit becomes smaller.
[0011]
Therefore, the present invention has been made in order to solve the problems of the related art related to the above-described integrated circuit, and the object of the present invention is to reduce the processing bit number capability between the CPU and its peripheral devices without reducing the processing bit number capability. An object of the present invention is to provide an integrated circuit whose degree of integration is improved by reducing the bus width of the address bus connecting the peripheral devices.
[0012]
[Means for Solving the Problems]
An integrated circuit according to a first aspect of the present invention includes a first address register that holds a supplied address, and a second address that holds a second partial address that is a part of the supplied address before the address is supplied. The first address and the second address stored in the second address register are compared with the first address register and the third address register of the first address register and the second partial address stored in the second address register. In the integrated circuit comprising the comparing means for storing and the storage means for outputting data corresponding to the address indicated by the address, the address width of the first partial address is equal to the second partial address width, and the first address register And the second address register and the comparing means are formed on the first package, and the third address register and the storing means are the second one. A residual address formed on the package and obtained by subtracting the address width of the first partial address from the address width of the address stored in the first address register between the first package and the second package Storage means that combines the second partial address and the remaining address stored in the third address register on the basis of the result of the comparison means. It is the gist that it is input to. The second feature of the present invention is that the first package and the second package, a first address register configured in the first package and holding the supplied address, and configured in the first package. is a second address register configured from a plurality of holding the second upper address is an upper address of the plurality of address supplied before the supply of the address is divided into two, respectively, in the first package is configured, and a first upper address and a plurality of second high-order address is an upper address of the address stored in the first address register bisected respectively compared respectively, the upper address instruction signal a second address register as many provided is comparison means for outputting is configured in a second package, provided the same number as the second address register, a plurality A third address register for holding the second upper address, or to generate a high-order address storage distinguish signals on the basis of the upper address instruction signal, to hold the second upper address to one of the second address register And a control means for controlling whether the second higher address is held in any one of the third address registers, the first package and the second package, and the first address register An address bus having an address width equal to the address width of the remaining address obtained by subtracting the address width of the first upper address from the address width of the first address, and an upper address storage distinguishing signal and an upper address instruction. based on the signal, a second upper address stored in one of the third address register is selected, the selected Is summarized in that the upper address and a residual address and are combined address is a semiconductor integrated circuit and a memory unit to be input.
[0013]
[Action]
As described above, in the integrated circuit of the present invention, an address register for storing a part of the address in the integrated circuit is provided on both the CPU block side and the memory block side, and the number of bits corresponding to a part of the supplied address is set. The width of the address bus corresponding to the minute (connecting between the CPU block and the memory block) is reduced. As a result, the number of pins of the integrated circuit is reduced, and the number of pads of each block in the integrated circuit is reduced.
[0014]
A part of the supplied address is stored in the address register. If a part of the next supplied address matches the address stored in the address register, the address in the address register is used. This prevents an increase in the number of clocks required for memory access due to a decrease in the number of bits in the address bus. That is, the memory access can be executed without reducing the processing bit number capability.
[0015]
【Example】
The basic concept of the present invention is as follows.
[0016]
An integrated circuit is generally composed of a CPU and peripheral devices such as a memory, and the CPU and the memory are connected by an address bus, whereby address data to be accessed is transferred from the CPU to the memory. For example, if the CPU or memory is a device having a 32-bit processing capability, the address bus width is usually composed of 32 bits. However, when address data is exchanged between the CPU and the memory, it is rare that the value of the entire 32-bit width of the address bus constantly changes, and only some bit line values change. It is common. Therefore, the address bus width is reduced by deleting a part of the address bus, that is, a bit line whose value does not change frequently, and as an alternative, the address data value on the deleted bit line is saved in a register or the like. Then, whenever necessary, the address data obtained by combining the value saved in the register and the reduced value on the address bus is transferred to the CPU and the memory. Thereby, the degree of integration of the integrated circuit can be improved without reducing the access operation efficiency.
[0017]
Embodiments of the present invention will be described below with reference to the drawings.
[0018]
FIG. 1 is a schematic block diagram of an integrated circuit according to a first embodiment of the present invention. In the integrated circuit 1 of the present embodiment, the CPU and peripheral devices having a 4 Gbyte address space are capable of processing 32-bit data, and the address bus connecting each block has a 16-bit address width. It shall be. Further, for simplification of description, the peripheral device will be described by limiting only the memory. However, it goes without saying that the present invention is applicable to an integrated circuit including a CPU having a processing capacity for data other than 4G address space, that is, 32-bit data.
[0019]
The integrated circuit 1 is composed of, for example, an LSI, and the CPU block 2 and the memory block 3 are connected by a 16-bit width address bus via a pad or the like (not shown).
[0020]
The integrated circuit 1 includes a CPU block 2 and a memory block 3 as a peripheral device.
[0021]
The CPU 4 in the CPU block 2 is connected to a 32-bit address register 6 via an address bus 5 having a 32-bit width, and the register 6 stores 32-bit address data transferred from the CPU 4. The upper 16 bits of the 32-bit address register 5 are stored in the upper address holding register 8 via the address bus 7 having a 16-bit width. The comparator 16 compares the upper 16 bits of the address data stored in the register 8 and the address data transferred from the CPU 4 in the next cycle. The comparison result is transferred as a control signal to the input selector 10 and the output selector 11. The input selector 10 receives the upper 16 bits and lower 16 bits of the address data in the register 6, and either one is selected by the control signal from the comparator 9 and transferred to the memory block 3.
[0022]
The memory block 3 selects either the upper 16 bits or the lower 16 bits of the address data transferred from the CPU block 2 based on the control signal sent from the comparator 9, and selects the 16-bit upper address holding register 12 and Output to the memory 13.
[0023]
As described above, the memory block 3 includes the output selector 11, the register 12, and the memory 13.
[0024]
Next, the operation of the integrated circuit 1 will be described with reference to the timing chart of FIG. When it is repeated for confirmation, the operation of the integrated circuit 1 in which a 16-bit width address bus is formed in an address space of 4 G bytes ( ²³² bytes, 32 bits address) as a first embodiment of the present invention will be described.
[0025]
First, a memory access at an address value of 00000000H is as follows (procedure A: when the upper 16 bits of the previous address data match the upper 16 bits of the current address data).
[0026]
At the first clock, the 32-bit address register 6 stores a 32-bit address (00000000H) for executing a memory access. Further, in the first half of the first clock, the contents of the upper 16 bits in the 32-bit address register 6 and the value stored in the 16-bit upper address holding register 8 are compared by the comparator 9. Here, the value of the upper 16 bits of the register 6 is 0000H, and the value in the register 8 is undetermined (unknown, that is, not 0000H). Therefore, Oite to the second clock, the upper address instruction signal as the output of the comparator 9 becomes a High level. In other words, the comparison result by the comparator 9 indicates that the address values do not match. In the second clock, the high level instruction signal from the comparator 9 is supplied to the input selector 10. Then, the contents of the upper 16 bits (0000H) of the 32-bit address register are output to the 16-bit address bus 14. Then, the contents of the 16-bit address bus 14 are input to the output selector 11, and the output destination of the output selector 11 becomes the 16-bit upper address holding register 12 according to the upper address instruction signal supplied from the comparator 9. In the third clock, since the upper bits of the 32-bit address register 6 and the contents of the 16-bit upper address holding register 8 match, the value of the upper address instruction signal of the comparator 9 becomes low level. Therefore, the lower 16 bits of the 32-bit address register 6 are output to the 16-bit address bus 14 by the input selector 10 at the third clock. In the output selector 11, since the upper address signal transferred from the comparator 9 is at a low level, the address is transferred to the memory 13. The upper 16 bits of this address are the contents (0000H) stored in the 16-bit upper address holding register 12 one clock before, and the lower 16 bits are the contents of the lower 16 bits in the 32-bit address register 6. A 32-bit address 00000000H is input to the memory 13 via a 32-bit address bus 15 in the memory circuit.
[0027]
Then, the content <A> of the memory 13 corresponding to the address 00000000H is read at the fourth clock.
[0028]
(Procedure B: When the upper 16 bits of the address data accessed last time matches the upper 16 bits of the address data accessed this time)
Next, the memory access at address 00000004H will be described.
[0029]
At the third clock, a 32-bit address for performing the current memory access is stored in the 32-bit address register 6 (00000004H). The comparator 9 compares the content of the upper 16 bits of the 32-bit address register 6 with the content of the upper address stored in the 16-bit upper address holding register 8 in the first half of the first clock within the same clock. Since the contents of the upper 16 bits of the 32-bit address register are 0000H and the contents stored in the 16-bit upper address holding register 8 are also 0000H, the output of the comparator 9 (upper address instruction signal) is output at the fourth clock. Low level. In the fourth clock, the low level output output from the comparator 9 is input to the input selector 10, and the lower 16-bit content (0000H) of the 32-bit address register 6 is output to the 16-bit address bus 14. Then, the contents of the 16-bit address bus 14 are input to the output selector 11. The output destination is the memory 13 by the output of the comparator 9. At this time, the upper 16 bits use the value (0000H) stored in the 16-bit upper address holding register 12 in the third clock.
[0030]
Then, the content <B> of the memory 13 corresponding to the address 00000004H is read at the next fifth clock.
[0031]
Similarly, if the immediately preceding address is different from the current address, the memory access is performed according to the procedure A, and if the immediately preceding address is the same as the current address, the memory access is performed according to the procedure B.
[0032]
Next, an explanation will be given of an integrated circuit as a second embodiment of the present invention with reference to FIGS. FIG. 3 is a diagram showing a configuration of an integrated circuit according to the second embodiment of the present invention, and FIG. 4 is a diagram showing timing of the operation.
[0033]
In addition to the components of the integrated circuit shown in the first embodiment, the configuration of the integrated circuit shown in FIG. 3 includes a 16-bit upper address holding register 33 that holds the contents of the upper 16 bits of the 32-bit address register 6, and a 32-bit The upper 16-bit address of the 32-bit address register 6 is stored in either the 16-bit upper address holding register 33 that holds the upper 16-bit contents of the address register 6, the 16-bit upper address holding register 34, or the 16-bit upper address holding register 33. An output selector 35 for selecting whether to transfer, a comparator 36 for comparing the upper 16-bit addresses of the 16-bit upper address holding register 34 and the 32-bit address register 6, a 16-bit upper address holding register 33 and the 32-bit address register 6 The upper 16 bits of A comparator 37, an AND circuit 38, an output selector 39, a 16-bit upper address holding register 40 holding the output of the output selector 39, a 16-bit upper address holding register 41 having the same function, An input selector 42 that selects the output of the bit upper address holding register 40 and the 16-bit upper address holding register 41, an output selector 35, an output selector 39, and a storage destination switching circuit 43 that generates a signal for controlling the input selector 42. Composed. The integrated circuit 60 includes a CPU block 31, a memory block 32, and a 16-bit address bus and signal lines connecting them.
[0034]
As is apparent from the description of the configuration of the integrated circuit of the second embodiment, the basic difference between the configuration of the integrated circuit of the first embodiment and the configuration of the integrated circuit of the second embodiment is the 31-bit address register. In the case of the first embodiment, there are one set of registers for storing the upper 16 bits of data 6 (that is, the 16-bit registers indicated by reference numerals 8 and 12 in FIG. 1). Two sets (that is, 16-bit registers indicated by reference numerals 33, 34 and 40, 41 in FIG. 3) are incorporated in the integrated circuit 30.
[0035]
In the integrated circuit of the second embodiment configured as described above, the storage destination switching circuit 43 controls the control signal indicating the storage destination when the upper 16-bit address of the 32-bit address register 6 changes (that is, the upper address storage distinction signal). ), Or a control signal indicating a register in which a valid upper 16-bit address is stored when the upper 16-bit address has not changed (also an upper address storage distinction signal) is supplied to the output selectors 35 and 39. Whether or not a valid upper 16-bit address should be stored in either the register 33 or 34 on the block 31 side, or in either the register 40 or 41 on the memory block 32 side, according to this upper address storage distinction signal It becomes clear.
[0036]
In the integrated circuit 1 of the first embodiment, when the upper 16 bits in the 32-bit address register change (in the case of the 16-bit address bus shown in FIG. 2 from the clock 9 to the clock 10), the 32-bit address is set over 2 clocks. it is necessary to supply the memory 13, but in the integrated circuit 30 of the second embodiment, as shown in clock 9 and 10 in FIG. 4, only a 32-bit address applied one clock can be supplied to the memory 13 . In this case, the address of 0000H stored in any of the 16-bit upper address holding registers with the clock 2 is used as the upper 16-bit address. The control is executed by the storage destination switching circuit 43, the input selectors 10, 42, and the output selectors 35, 11, 39.
[0037]
In the prior art, the first embodiment, and the second embodiment, the width of the address bus and the time for transferring seven data are compared as follows.
[0038]
[Table 1]

In the above embodiment, an integrated circuit having a 32-bit address has been described. However, the present invention may be applied to an integrated circuit having a 16-bit or 64-bit address bus regardless of the case of 32 bits. In addition, 32 bits are equally divided into upper 16 bits and lower 16 bits this time, but the present invention has the same effect even if divided into upper 8 bits and lower 24 bits, for example.
[0039]
【The invention's effect】
As described above, in the present invention, a register for storing a part of the address in the integrated circuit is provided on both the CPU block side and the memory block side, and it corresponds to the number of bits corresponding to a part of the supplied address. The width of the address bus (which connects the CPU block and the memory block) is reduced. Thus, it is possible to reduce the number of pins of the integrated circuit, it is possible to reduce the number of putts each block of the integrated circuit, it is possible to reduce the packaging cost, and Sageruko the manufacturing cost of the integrated circuits as a result And can contribute to higher integration of integrated circuits. In addition, a part of the supplied address is stored in the register, and when a part of the next supplied address matches the address stored in the register, by using the address in the register, To provide an integrated circuit capable of preventing an increase in the number of clocks required for memory access due to a decrease in the number of bits in the address bus, that is, performing a memory access without reducing the processing bit number capability. it can.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of an integrated circuit according to a first embodiment of the present invention.
FIG. 2 is a timing chart showing an operation of the integrated circuit shown in FIG.
FIG. 3 is a configuration diagram of an integrated circuit according to a second embodiment of the present invention.
4 is a timing chart showing an operation of the integrated circuit shown in FIG. 2. FIG.
FIG. 5 is a configuration diagram of an integrated circuit as a conventional example.
6 is a timing chart showing an operation of the integrated circuit shown in FIG. 5. FIG.
[Explanation of symbols]
1, 30 Integrated circuit 2, 31 CPU block 3, 32 Memory block 6 32-bit upper access register 8, 12, 34, 33, 40, 41 16-bit upper address holding register 9, 36, 37 Comparator 10, 42 Input selector 11, 35, 39 Output selector 13 Memory

Claims (2)

A first package and a second package;
A first address register configured in the first package and holding a supplied address;
A second package configured in the first package and configured to hold a second higher address, which is a higher address among the plurality of addresses supplied before the address supply is divided into two. An address register;
A first upper address, which is an upper address among the addresses divided into two, each configured in the first package and stored in the first address register, and a plurality of the second upper addresses, respectively. Comparison means provided in the same number as the second address register to be compared;
An AND circuit that detects that none of the plurality of second upper addresses matches the first upper address based on the comparison results of the plurality of comparison means, and outputs an upper address instruction signal;
An address width equal to the address width of the remaining address obtained by connecting the first package and the second package and subtracting the address width of the first higher address from the address width of the first address register. An address bus with
The first upper address is configured in the first package and the first upper address is assigned to the address bus when none of the plurality of second upper addresses matches the first upper address based on the upper address instruction signal. And when any one of the plurality of second upper addresses matches the first upper address, the lower address of the address stored in the first address register is divided into two. An input selector that outputs to the bus;
A third address register configured in the second package, provided in the same number as the second address register, and holding a plurality of the second upper addresses;
Control whether to generate an upper address storage distinction signal based on the comparison results of the plurality of comparing means and hold the second upper address in any of the second address registers, and the third address Control means for controlling whether to hold the second upper address in any of the registers;
The second upper address configured in the second package and stored in any of the third address registers is selected based on the upper address storage distinction signal and the upper address instruction signal. Storage means for inputting an address in which the selected second upper address and lower address are combined ;
The first high-order address from the address bus when configured in the second package and based on the high-order address instruction signal, when none of the plurality of second high-order addresses matches the first high-order address The address is output to the third address register as the second upper address, and the lower address from the address bus when any of the plurality of second upper addresses matches the first upper address And an output selector for outputting to the storage means . The control means includes
A storage destination switching circuit for generating the upper address storage distinction signal based on a comparison result of the plurality of comparison means ;
An output selector for selecting whether to hold the second upper address in any of the second address registers based on the upper address storage distinction signal;
The output selector for selecting whether to hold the second upper address in any one of the third address registers based on the upper address storage distinction signal. Integrated circuit.

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