JP4350070B2 - A / D converter - Google Patents

Description

  The present invention relates to an A / D conversion device.

  Along with the digitization and speeding up of signal processing in information communication equipment and the lightening and downsizing of equipment, A / D conversion devices mounted thereon are also required to be fast and high performance. At present, an A / D conversion apparatus capable of performing a high-speed sampling operation in a wireless device or the like whose bit rate is increasing has been proposed (for example, Patent Document 1).

The A / D converter includes a reference voltage generation circuit that outputs a plurality of reference voltages, a plurality of comparators that compare any of the reference voltages with an analog input signal, and an encoder that outputs a digital signal from the result of the comparators It is equipped with.
JP 2003-101411 A

  The A / D conversion device described in Patent Document 1 requires a large number of comparators and supplies clocks to the respective comparators, so that the internal clock tree becomes large. In order to operate such an A / D converter at high speed, it is required to match these clock skews as much as possible. However, the operating environment due to manufacturing fluctuation, temperature change, power supply voltage drop, etc. Due to the change, the clock skew does not match as designed at the stage of actual operation. When the clock skews in the A / D converter are not aligned, there is a problem that the data propagation time in the A / D converter is insufficient and the SN ratio of the output signal is deteriorated. It was.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide an A / D conversion device capable of high-speed sampling operation with a good S / N ratio.

  One embodiment of the present invention relates to an A / D conversion device. This apparatus converts an analog signal into a digital signal via at least two functional blocks, and each A / D converter is configured so that each functional block performs a pipeline operation. A clock control unit is provided for adjusting the skew of the clock supplied to each functional block based on the S / N ratio of the digital signal converted by the apparatus.

  According to this aspect, the skew of the clock inside the A / D converter is adjusted based on the S / N ratio from the digital signal after A / D conversion. As a result, when the A / D converter is operated at high speed, signal propagation inside the A / D converter cannot be performed accurately, and the S / N ratio of the A / D converted digital signal is reduced. However, the skew of each clock can be adjusted so that the SN ratio of the digital signal is increased, and the SN ratio of the A / D converted digital signal can be increased. Therefore, it is possible to realize an A / D conversion device capable of high-speed sampling operation with a good SN ratio.

  In this aspect, the clock control unit may adjust the skew by increasing or decreasing the delay time of the clock signal for each clock supplied to each functional block. The clock skew can be finely adjusted by increasing or decreasing the delay time of the clock signal supplied to each stage of the pipeline.

  In this aspect, the skew adjustment may be repeatedly performed while the SN ratio is equal to or lower than a predetermined level. As a result, the skew of the clock in the A / D converter can be adjusted until the digital signal after A / D conversion reaches a predetermined level. A conversion device can be realized.

  Note that any combination of the above-described constituent elements, and those in which the constituent elements and expressions of the present invention are mutually replaced between methods, apparatuses, systems, and the like are also effective as an aspect of the present invention.

  According to the present invention, it is possible to obtain an A / D converter capable of high-speed sampling operation with a good SN ratio.

  The embodiment of the present invention is an A / D conversion device used for a reception device in a communication system in which frequency hopping is performed in symbol units. An OFDM (Orthogonal Frequency Division Multiplexing) modulation scheme is applied to a frequency hopped symbol, and this communication system targets an UWB (Ultra Wide Band) to which an MB-OFDM (Multiband OFDM) modulation scheme is applied.

  FIG. 1 shows a configuration of receiving apparatus 100 according to an embodiment of the present invention. The receiving device 100 includes an antenna 10, a radio unit 12, an A / D conversion device 14, a baseband processing unit 16, and a control unit 18.

  The antenna 10 receives a signal from a transmission device (not shown) via a wireless section. An OFDM modulation scheme and an FH (Frequency Hopping) scheme are applied to received signals. Each subcarrier is phase-modulated by QPSK (Quadrature Phase Shift Keying). Further, an OFDM symbol which is one unit in the OFDM modulation scheme is frequency hopped by a predetermined hopping pattern. Here, the OFDM symbol will be described later. The received signal has a predetermined radio frequency.

  The radio unit 12 converts the radio frequency signal received by the antenna 10 into a baseband signal. The radio unit 12 includes a code generator for performing frequency hopping according to a predetermined hopping pattern, and a pseudo-random code signal generated from the code generator is a hopping pattern in a received radio frequency signal. Synchronized with. The code generator performs synchronization with the hopping pattern on the received radio frequency signal by a predetermined method. Since the baseband signal includes in-phase components and quadrature components, it should generally be indicated by two signal lines. Here, for the sake of clarity, the signal is indicated by one signal line. And The same applies to the following.

  The A / D converter 14 converts a baseband signal that is an analog signal input from the wireless unit 12 into a digital signal. The A / D converter 14 has a configuration characteristic of the present invention. That is, the A / D converter 14 evaluates the SN ratio using the signal converted into the digital signal, and adjusts the skew of the clock tree in the A / D converter 14 until a predetermined SN ratio is obtained. . The configuration and operation of the A / D converter 14 will be described later.

  The baseband processing unit 16 demodulates the baseband signal converted into a digital signal by the A / D conversion device 14. The control unit 18 controls the entire receiving apparatus 100 so that the receiving apparatus 100 can execute a predetermined process.

  FIG. 2 shows a symbol configuration of a signal received by receiving apparatus 100. FIG. 2A shows a signal (hereinafter referred to as “IFFT signal”) on which IFFT (Inverse Fast Fourier Transform) is performed in the transmission apparatus. In the transmission apparatus, the frequency domain signal is IFFT and converted into a time domain signal. Here, the IFFT of the transmission device and the FFT of the reception device are both executed as a unit, that is, as an FFT window (hereinafter, the timing corresponding to one of the 128 data is referred to as “FFT point”). "). FIG. 2A shows the data of 128 FFT points as “D1”, “D2”, “D3”, and “D4” in order from the front.

  FIG. 2B shows a signal obtained by adding a guard interval (GI) to the IFFT signal shown in FIG. As shown in the drawing, “GI” is added to the back of each of “D1”, “D2”, “D3”, and “D4”, which is data of 128 FFT points. Here, “GI” corresponds to a portion where no signal is transmitted, that is, a non-transmission section. Further, a combination of 128 FFT point data and “GI” is referred to as the “OFDM symbol” described above. For example, “D1” and “GI” correspond to one OFDM symbol. The same applies to “D2”, “D3”, and “D4”.

  FIG. 3 shows a waveform of a signal received by the receiving apparatus 100. FIG. 3A shows a waveform of a signal corresponding to FIG. As shown in the figure, the OFDM symbol is formed by repeating a transmission / reception period corresponding to the IFFT signal and a non-transmission period corresponding to the GI. FIG. 3B shows a waveform of a signal when the signal of FIG. 2A is received by the antenna 10 through the wireless transmission path. Since a delayed wave is generated in the wireless transmission path, the antenna 10 receives a predetermined signal even in the GI section. However, the signal strength in the GI section is smaller than that in the IFFT signal section. In the embodiment of the present invention, the SN ratio is derived from this IFFT signal section and GI section.

  FIG. 4 is a block diagram showing the configuration of the A / D conversion device 14. The A / D converter 14 is a parallel A / D converter, and includes an A / D converter 20, a latch driver 22, an SN ratio determination unit 24, and a clock controller 26. The A / D converter 14 is configured so that the A / D converter 20 is one functional block and the latch driver 20 is one functional block, and these two functional blocks perform a pipeline operation.

The A / D converter 20 converts an analog signal (baseband signal output from the wireless unit 12) 200 into an n-bit digital signal 202. The A / D converter 20 includes a reference voltage generation circuit that outputs 2 ⁿ reference voltages, 2 ⁿ comparators, and an encoder. Each comparator compares the analog signal 200 with each reference voltage generated by the reference voltage generation circuit, encodes the output of each comparator by an encoder, and outputs an n-bit digital signal 202. The A / D converter 20 operates in synchronization with the clock CK1 whose clock skew is adjusted by the clock controller 26.

  The latch driver 22 latches the n-bit digital signal 202 output from the A / D conversion unit 20 and outputs the latched digital signal 204 to the baseband processing unit 16 at the subsequent stage. The digital signal 204 output from the latch driver 22 is also input to the SN ratio determination unit 24. The latch driver 22 operates in synchronization with the clock CK <b> 2 whose clock skew is adjusted by the clock control unit 26.

  The SN ratio determination unit 24 determines the SN ratio of the digital signal 204 output from the latch driver 22. As described above, the digital signal 204 has a transmission / reception interval corresponding to the IFFT signal and a non-transmission interval corresponding to the GI. The SN ratio is determined by calculating the SN ratio of the digital signal 204 from the IFFT signal and the signal in the section corresponding to the GI, and determining whether the calculated SN ratio is larger than a predetermined SN ratio. When the calculated SN ratio is equal to or lower than the predetermined SN ratio, the SN ratio determination unit 24 outputs a pulse 206 to the clock control circuit 26. The value of the predetermined SN ratio may be a value stored in the SN ratio determination unit 24 in advance. Further, it may be a value set by the control unit 18.

  Here, a method for calculating the SN ratio of the digital signal 204 will be described. First, the power in the section of the IFFT signal in one OFDM symbol is integrated. Here, the power in the interval of the input IFFT signal is integrated according to the sampling interval at which the baseband processing unit 16 operates. Also, the power in the GI section in one OFDM symbol is integrated. Here, the power of the input GI section is integrated according to the sampling interval at which the baseband processing unit 16 operates. The separation of the IFFT signal section and the GI section in the OFDM symbol is performed based on information about the boundary between the IFFT signal section and the GI section input from the baseband processing unit 16.

  Next, the integrated power in the IFFT signal section is averaged according to the number of samples in the IFFT signal section. The same processing is also executed in the GI section. That is, since the IFFT signal section and the GI section have different lengths, it is difficult to directly process the integrated power of the IFFT signal section and the integrated power of the GI section. Therefore, an average process is executed so that the process can be executed between them.

  Then, the SN ratio is calculated by dividing the average power of the IFFT signal section by the average power of the GI section. Strictly speaking, since the delayed wave is also received in the GI section, the average power of the GI section is different from the complete noise level, but is generally lower than the power of the average IFFT signal section. Therefore, it can be regarded as a noise level. Note that, as the average power in the GI section, the power in the rear portion may be averaged in the GI section. Thereby, the influence of the delayed wave can be reduced.

  When the pulse 206 is input from the SN ratio determination unit 24, the clock control unit 26 adjusts the clock skew of the clocks CK1 and CK2 input to the A / D conversion unit 20 and the latch driver 22. The clock skew is adjusted by increasing or decreasing the delay time of the clocks CK1 and CK2.

  FIG. 5 is a diagram illustrating a configuration of the clock control unit 26. The clock control unit 26 includes a bit counter 30 and two delay control units 32 and 34.

  The bit counter 30 is a counter of (m1 + m2) bits and counts the number of pulses 206 input from the SN ratio determination unit 24. That is, every time the pulse 206 is input, the bit counter 30 is incremented by one. In the bit counter 30, the upper m1 bit signal Q <b> 2 is input to the delay control unit 32, and the lower m2 bit signal Q <b> 2 is input to the delay control unit 34.

  The delay control unit 32 generates the clock CK1 of the A / D conversion unit 20 by delaying the input clock CLK. Further, the delay control unit 34 delays the input clock CLK and generates the clock CK2 of the latch driver 22. Each delay amount is determined by the value of the bit counter 30. That is, the delay amount of the delay control unit 32 is determined based on the value of the upper m1 bit signal Q1 of the bit counter 30, and the delay amount of the delay control unit 34 is set to the value of the lower m2 bit signal Q2 of the bit counter 30. Determined based on. Then, by counting up the bit counter 30, the delay amounts of the delay control units 32 and 34 are increased or decreased by changing the values of the signals Q1 and Q2. As described above, the delay control units 32 and 34 individually delay the input clock CLK based on the value of the bit counter 30, so that the clock CK 1 of the A / D conversion unit 20 and the clock CK 2 of the latch driver 22 are delayed. Adjust the clock skew.

  FIG. 6 is a diagram illustrating a configuration of the delay control unit 32 when the signal Q1 input from the bit counter 30 is 3 bits. In the delay control unit 32, seven delay cells 40 to 46 are connected in cascade, and the input clock CLK is input to the first-stage delay cell 40. Further, the output of the delay cell 46 at the final stage is output as the clock CK1 of the A / D converter 20.

  FIG. 7 shows a configuration example of the delay cells 40 to 46. FIG. 7A shows an example in which a delay cell is configured by a resistor. When the signal Q1 is “1”, the switch to which the resistor is connected is turned on, the switch to which the resistor is not connected is turned off, and the input signal IN is delayed and output as the output signal OUT. When the signal Q1 is “0”, the switch to which the resistor is not connected is turned on, the switch to which the resistor is connected is turned off, and the input signal IN is output as it is without being delayed. . The delay cell shown in FIG. 7B is an example in which the resistor shown in FIG. 7A is replaced with two inverters. The operation is the same as in FIG.

  FIG. 7C shows an example in which a delay cell is configured by two inverters and one capacitor. When the signal Q1 is “0”, the input signal IN is delayed by two inverters and output as the output signal OUT. On the other hand, when the signal Q1 is “1”, a capacitor is inserted between the intermediate point of the two inverters and the ground point, and the input signal IN is greatly delayed by the capacitor and output as the output signal OUT.

  In the delay cells of FIGS. 7A to 7C, the polarity of the signal Q1 may be reversed. In this case, when the signal Q1 is “0”, the input signal IN is greatly delayed and output as the output signal OUT.

  In the delay control unit 32 of FIG. 6 including the delay cells 40 to 46 having the configurations of FIGS. 7A to 7C, the least significant bit Q1 [0] of the 3-bit signal Q1 is one delay. In the cell 46, the middle bit Q1 [1] is connected to the two delay cells 44 and 45, and the most significant bit Q1 [2] is connected to the four delay cells 40-43. When the signal Q1 [0] is “1”, the input clock CLK is delayed by one delay cell by the delay cell 46. When the signal Q1 [1] is “1”, the delay cell 44, 45 delays the input clock CLK by two delay cells. When the signal Q1 [2] is “1”, the input clock CLK is delayed by four delay cells by the delay cells 40-43. As a result, by changing the 3-bit signal Q1 from “0” to “7”, the input clock CLK is not delayed or delayed by one to seven delay cells, and the A / D converter 20 is output as clock CK1.

Although FIG. 6 shows an example of the delay control unit 32 when the signal Q1 is 3 bits, when the signal Q1 is m1 bits, the delay control unit 32 is configured by cascading 2 ^m1 delay cells. do it. At this time, 2k delay cells may be connected to the kth bit Q1 [k] (0 ≦ k <m1). Thus, by changing the m1 bit signal Q1, the input clock CLK is output as the clock CK1 to the A / D converter 20 without delaying or by delaying the delay cell by one stage to two ^m1 stages. Can be made.

The delay control unit 34 can also be realized by the same configuration as that in FIG. That is, when the signal Q2 is m2 bits, 2 ^m2 delay cells are connected in cascade to form the delay control unit 34. At this time, 2l delay cells may be connected to the l-th bit Q2 [l] (0 ≦ l <m2). Thus, by changing the m2 bit signal Q2, the input clock CLK is output as the clock CK2 to the latch driver 22 without delaying the input clock CLK or by delaying the delay cell by one stage to two ^m2 stages. Can do.

  The operation of receiving apparatus 100 having the above configuration will be described. The radio unit 12 converts the frequency-hopped signal in units of OFDM symbols from a radio frequency to a baseband frequency and outputs the received signal 200. The A / D converter 14 converts the received signal 200, which is an analog signal, into a digital signal. At this time, the bit counter 30 provided in the clock control unit 26 in the A / D conversion device 14 is set to an arbitrary value, and the delay amount of the clock CK1 driving the A / D conversion unit 20 with respect to the input clock CLK. The delay amount of the clock CK2 for driving the latch driver 22 with respect to the input clock CLK is determined based on the value of the bit counter 30.

  The digital signal 204 converted by the A / D converter 14 is input to the baseband processing unit 16, and the baseband signal is demodulated. The digital signal 204 is also input to the SN ratio determination unit 24 inside the A / D conversion device 14. The S / N ratio determination unit 24 calculates the S / N ratio of the digital signal 204 and determines whether or not the calculated S / N ratio is larger than a predetermined S / N ratio. When the S / N ratio determining unit 24 determines that the calculated S / N ratio is larger than the predetermined S / N ratio, the value of the bit counter 30 in the clock control unit 26 is not changed, and the delay amount of the clock CK 1 with respect to the input clock CLK The delay amount of the clock CK2 is kept as it is.

  On the other hand, when the S / N ratio determining unit 24 determines that the calculated S / N ratio is equal to or lower than the predetermined S / N ratio, the S / N ratio determining unit 24 generates a pulse and inputs this pulse to the clock control unit 26. When receiving a pulse from the SN ratio determination unit 24, the clock control unit 26 increments the value of the bit counter 30 by one. The clock skews of the clocks CK1 and CK2 are adjusted by newly determining a delay amount with respect to the input clock CLK based on the value of the bit counter 30 after the increment. Then, the A / D converter 14 converts the received signal 200 into the digital signal 204 again using CK1 and CK2 having a new clock skew. Using this new digital signal 204, the S / N ratio determination unit 24 performs S / N ratio determination. When the S / N ratio of the digital signal 204 is equal to or lower than a predetermined S / N ratio, the S / N ratio determination unit 24 sends a pulse to the clock control unit 26. The clock skew of the clocks CK1 and CK2 is adjusted again. Then, the clock skew adjustment of the clocks CK1 and CK2 is repeatedly performed until the SN ratio of the digital signal 204 becomes larger than the predetermined SN ratio.

  8 shows the clock CK1 input to the A / D converter 20 in the A / D converter 14 and its output signal 202, the clock CK2 input to the latch driver 22, and the output pulse of the SN ratio determination unit 24. An example of a timing chart 206 is shown. In the output signal 202 in FIG. 8, the shaded timing indicates that the output signal 202 is an indeterminate value, and in the outlined timing, the output signal 202 is output with a definite value. Indicates that

  In FIG. 8, the output signal 202 of the A / D converter 20 is output in synchronization with the clock CK1 at the timing shown in the figure. In the period 1, the clock CK1 and the clock CK2 have the same clock skew. In such a situation, the rising edge of the clock CK2 overlaps with the timing at which the output signal 202 of the A / D converter 20 changes, and the latch driver 22 operating in synchronization with the clock CK2 is connected to the A / D converter. Twenty output signals 202 cannot be latched correctly. Therefore, the SN ratio of the digital signal 204 that is the output signal of the latch driver 22 is poor, and the SN ratio determination circuit 24 generates an output pulse 206 in the clock control unit 26. The clock control unit 26 receives the output pulse 206 and increases the delay amount of the clock CK2.

  Next, in period 2, the delay amount of the clock CK2 is increased, and the clock skew between the clock CK1 and the clock CK2 is slightly increased. In this state, when the clock CK2 rises, the output signal 202 of the A / D converter 20 has not yet been determined, and the latch driver 22 operating in synchronization with the clock CK2 The 20 output signals 202 cannot be latched correctly. Therefore, even in the period 2, the SN ratio of the digital signal 204 that is the output signal of the latch driver 22 is poor, and the SN ratio determination circuit 24 generates the output pulse 206 in the clock control unit 26. In response to the output pulse 206, the clock control unit 26 further increases the delay amount of the clock CK2.

  Next, in period 3, the clock skew between the clock CK1 and the clock CK2 is further increased. In this state, the output signal 202 of the A / D converter 20 is determined at the rising edge of the clock CK2, and the latch driver 22 operating in synchronization with the clock CK2 outputs the output signal 202 of the A / D converter 20. Can be latched correctly. Therefore, the S / N ratio of the digital signal 204 that is the output signal of the latch driver 22 is improved, and the S / N ratio determination unit 24 stops adjusting the clock skew without generating the output pulse 206 in the clock control unit 26. Thereafter, as long as the SN ratio of the digital signal 204 does not become a predetermined value or less, the delay amount of each clock in the clock control unit 26 is kept constant. On the other hand, when the relationship between the clock skews of the clocks CK1 and CK2 changes due to a temperature change or the internal delay changes, the SN ratio of the digital signal 204 may become a predetermined value or less again. In this case, the SN ratio determination unit 24 generates an output pulse 206 for the clock control unit 26 and adjusts the clock skew of the clocks CK1 and CK2 again.

  As described above, according to the embodiment of the present invention, the S / N ratio is calculated from the digital signal after A / D conversion, and when the calculated S / N ratio is equal to or lower than the predetermined S / N ratio, The clock skew is adjusted by increasing or decreasing the delay time of the clock signal for each clock supplied to each stage of the pipeline. Thereby, even when a high-speed sampling operation is performed, the skew of each clock is adjusted so that the propagation of the signal inside the A / D converter can be accurately performed. The ratio can be increased. Therefore, it is possible to realize an A / D conversion device with a high S / N ratio capable of high-speed sampling operation.

  In addition, since the skew of each clock can be adjusted while actually operating, it is not necessary to increase the clock skew margin according to the manufacturing process and operating environment at the design stage, and an A / D capable of high-speed sampling operation. The conversion device can also be designed easily. Furthermore, since the clock skew can be adjusted in accordance with changes in the actual operating environment such as temperature, it is possible to realize an A / D converter that compensates for the high-speed sampling operation in a wide range of operating environments.

  The present invention has been described based on the embodiments. The embodiments are exemplifications, and it will be understood by those skilled in the art that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are within the scope of the present invention. .

  For example, in the SN ratio determination unit 24 of FIG. 4, when the SN ratio of the digital signal 204 is less than or equal to a predetermined value, the SN ratio determination unit 24 outputs a pulse to the clock control unit 26, but the SN ratio of the digital signal 204 An enable signal that becomes active when the ratio becomes equal to or smaller than a predetermined value and becomes inactive when the SN ratio of the digital signal 204 becomes larger than the predetermined value may be output. In this case, the clock control unit 26 may include a pulse signal generation circuit that generates a pulse signal every cycle when the enable signal is in an active state, and the pulse signal generated by the pulse signal generation circuit You may make it input into the bit counter 30. FIG. In this case, in one cycle, the A / D converter 20 performs A / D conversion, the latch device 22 latches and outputs the digital signal, and the SN ratio determination unit 24 sets the SN ratio of the digital signal 204. What is necessary is just the time required to judge.

  In FIG. 4, the A / D converter 14 uses the A / D converter 20 as one functional block and the latch driver 22 as one functional block so that these two functional blocks perform pipeline operation. Although the example which comprised was shown, it does not restrict to this, You may comprise by the pipeline of two or more stages. For example, the A / D conversion unit 20 may be divided into two functional blocks of a comparator and an encoder, and a three-stage pipeline structure including the latch driver 22 may be used. Further, a pipeline for correcting a bubble error that frequently occurs when a plurality of comparators are operated at high speed may be added to the subsequent stage of the comparator, and this may be used as one functional block to configure the pipeline. When the A / D converter 14 is configured with a plurality of stages of pipelines, the clock control unit 26 may adjust each delay amount for each clock input to each stage of the pipeline.

  Further, in the present embodiment, the configuration in which the SN ratio determination unit is provided in the A / D conversion device 14 is shown. However, depending on the communication system, the baseband processing unit 16 may perform the SN ratio determination. . In such a case, the S / N ratio determination unit 14 is not provided in the A / D conversion device 14, and the result of the S / N ratio determination unit provided in the baseband processing unit 16 is fed back to the A / D conversion device 14. May be.

It is a block diagram of the receiver which concerns on embodiment of this invention. FIGS. 2A and 2B are diagrams illustrating a symbol configuration of a signal received by the receiving apparatus of FIG. FIGS. 3A and 3B are diagrams illustrating waveforms of signals received by the receiving apparatus of FIG. 1 is a configuration diagram of an A / D conversion device according to an embodiment of the present invention. FIG. 5 is a configuration diagram of a clock control unit in FIG. 4. It is a block diagram of the delay control part of FIG. FIGS. 7A to 7C are examples showing the configuration of the delay cell of FIG. 5 is a timing chart of signals inside the A / D conversion device shown in FIG. 4.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Antenna 12 Radio | wireless part 14 A / D converter 16 Baseband process part 18 Control part 20 A / D conversion part 22 Latch driver 24 SN ratio determination part 26 Clock control part 30 Bit counter 32, 34 Delay control part 40-46 Delay cell 100 receiver

Claims (3)

An A / D converter configured to convert an analog input signal into a digital signal through at least two functional blocks, each functional block operating in a pipeline,
And a clock control unit configured to adjust a skew of a clock supplied to each functional block based on an average power ratio between an IFFT signal section and a guard interval section in the OFDM symbol digitally converted by the A / D conversion apparatus. A / D conversion device.   The A / D converter according to claim 1, wherein the clock control unit adjusts the skew by increasing or decreasing a delay time of a clock signal for each clock supplied to each functional block.   3. The A / D conversion apparatus according to claim 1, wherein the skew adjustment is repeatedly performed while the SN ratio is equal to or lower than a predetermined level.

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