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JP4356502B2 - Method of manufacturing nitride semiconductor device - Google Patents
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JP4356502B2 - Method of manufacturing nitride semiconductor device - Google Patents

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JP4356502B2
JP4356502B2 JP2004117344A JP2004117344A JP4356502B2 JP 4356502 B2 JP4356502 B2 JP 4356502B2 JP 2004117344 A JP2004117344 A JP 2004117344A JP 2004117344 A JP2004117344 A JP 2004117344A JP 4356502 B2 JP4356502 B2 JP 4356502B2
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修 三木
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Nichia Corp
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Description

本発明は、例えばLED(発光ダイオード)、LD(レーザダイオード)等の窒化物半導体(InAlGa1−X−YN、0≦X、0≦Y、X+Y≦1)に使用されるGaN基板の製造方法に関する。The present invention is used for nitride semiconductors (In X Al Y Ga 1-XY N, 0 ≦ X, 0 ≦ Y, X + Y ≦ 1) such as LED (light emitting diode) and LD (laser diode). The present invention relates to a method for manufacturing a GaN substrate.

本出願人は、窒化物半導体基板の上に積層した様々な層構成でもって、例えば青色等の高輝度な発光ダイオード(LED)、室温で長時間にわたる連続発振を可能とした青色のレーザダイオード(LD)のような、窒化物半導体素子を実現してきた。また、窒化物半導体の用途はこれだけにとどまらず、他の窒化物半導体素子への利用が提案され、様々な研究機関により精力的な研究がなされている。  The present applicant has various light-emitting diodes (LEDs), such as blue, which are stacked on a nitride semiconductor substrate, and blue laser diodes that enable continuous oscillation over a long period of time at room temperature (LEDs). (LD) has been realized. Further, the use of nitride semiconductors is not limited to this, and use for other nitride semiconductor devices has been proposed, and extensive research has been conducted by various research institutions.

このような窒化物半導体は、一般的にサファイアに代表されるような異種基板上に積層させた窒化物半導体層を基板として、この上に種々の層を積層することで所望の素子が製造されている。具体的に発光素子を例としてあげると、サファイア基板上に窒化物半導体層をエピタキシャル成長させた後、n層、p層を積層し、それぞれの層に対応する電極を設けることである。  Such a nitride semiconductor is generally manufactured by stacking various layers on a nitride semiconductor layer laminated on a heterogeneous substrate such as sapphire. ing. As a specific example of a light emitting device, after epitaxially growing a nitride semiconductor layer on a sapphire substrate, an n layer and a p layer are stacked, and electrodes corresponding to the respective layers are provided.

このように、窒化物半導体と格子整合する窒化物半導体基板の製造実現への要望は高まるばかりであるが、GaNバルク結晶を例にとっても、様々な研究機関により試みられているにもかかわらず、数mmのものが報告されるにとどまっている。  As described above, the demand for the realization of a nitride semiconductor substrate that is lattice-matched with a nitride semiconductor is increasing, but GaN bulk crystal is taken as an example in spite of attempts by various research institutions. Only a few millimeters have been reported.

窒化物半導体基板を製造する方法として、サファイア基板に酸化亜鉛の中間層を形成した後、窒化物半導体を積層し、前記中間層を湿式エッチングによりサファイア基板を剥離する方法が特開平7−202265号公報に開示されている。しかし、この方法により得られる窒化物半導体層では結晶性の良好な窒化物半導体基板が得られなかった。  JP-A-7-202265 discloses a method of manufacturing a nitride semiconductor substrate, in which a zinc oxide intermediate layer is formed on a sapphire substrate, a nitride semiconductor is laminated, and the intermediate layer is peeled off by wet etching. It is disclosed in the publication. However, a nitride semiconductor substrate with good crystallinity cannot be obtained with the nitride semiconductor layer obtained by this method.

しかしGaN単結晶サファイア基板を薄くした際、サファイア基板とGaNとの格子不整合により応力が発生し、基板に反りが生じてしまい、この基板上に窒化物半導体を形成して良好な窒化物半導体素子を得ようとしても限度があった。  However, when the GaN single crystal sapphire substrate is thinned, stress is generated due to lattice mismatch between the sapphire substrate and GaN, and the substrate is warped, and a nitride semiconductor is formed on the substrate to form a good nitride semiconductor. There was a limit even when trying to obtain an element.

また、酸化物基板上にGaNを成膜した後、サファイア基板側から研磨をして、GaNのみにする方法が特開平11−1399号公報に開示されている。この方法は酸化物基板上にGaNを成長させてHVPE法により一定の厚さの1次のGaNを形成し、この1次のGaN層の成長された窒化物半導体基板を研磨して酸化物基板の一部を除去し、1次のGaN層上に2次のGaN層を成長させ、再度研磨して除去し、この窒化物半導体基板が完全に除去された1次および2次のGaN層上に再び所定の厚さのGaN層を成長させてGaN単結晶を成長させ、最後にGaN単結晶を研磨してGaN基板を得る。  Japanese Laid-Open Patent Publication No. 11-1399 discloses a method of forming GaN on an oxide substrate and then polishing from the sapphire substrate side to make only GaN. In this method, GaN is grown on an oxide substrate, primary GaN having a certain thickness is formed by HVPE, and the nitride semiconductor substrate on which the primary GaN layer is grown is polished to obtain an oxide substrate. On the primary and secondary GaN layers from which the nitride semiconductor substrate has been completely removed, by growing a secondary GaN layer on the primary GaN layer and polishing and removing it again. A GaN layer having a predetermined thickness is again grown to grow a GaN single crystal, and finally the GaN single crystal is polished to obtain a GaN substrate.

しかしこの方法で得られるGaN基板は非常に欠陥が多く、この基板を用いて窒化物半導体を作製しても特性の良い素子は得られず、また層構成の複雑な窒化物半導体レーザ素子に至っては発振さえしなかった。  However, the GaN substrate obtained by this method has many defects, and even if a nitride semiconductor is produced using this substrate, an element having good characteristics cannot be obtained, and a nitride semiconductor laser element having a complicated layer structure has been obtained. Did not even oscillate.

本発明は上述の事情に鑑みてなされたものであり、GaN基板上に窒化物半導体が積層されて窒化物半導体素子となるGaN基板において、作製時に生じる反りが軽減した結晶欠陥の非常に少ないGaN基板の製造方法を提供し、素子特性の良好な窒化物半導体素子を歩留良く得ることを目的とする。  The present invention has been made in view of the above circumstances, and in a GaN substrate that is a nitride semiconductor element formed by laminating a nitride semiconductor on a GaN substrate, GaN having very few crystal defects with reduced warpage occurring during fabrication. An object of the present invention is to provide a method for manufacturing a substrate, and to obtain a nitride semiconductor device having good device characteristics with a high yield.

本発明者は、上記目的を達成するため、GaN基板について研究した結果、サファイア基板上にGaNを厚膜で形成した後に、サファイア基板側から研磨をしてGaNのみにすると反りが生じてしまうが、このGaN基板にさらに厚膜でGaNを積層することによって、サファイアとGaNとの格子不整合によって発生した際のひずみ応力が緩和され、反りが軽減した良好なGaN基板を得ることに成功した。  As a result of studying the GaN substrate to achieve the above-mentioned object, the present inventor has warped if the sapphire substrate is formed from a thick film and then polished from the sapphire substrate side to make only GaN. Further, by stacking GaN with a thick film on this GaN substrate, the strain stress caused by lattice mismatch between sapphire and GaN was alleviated, and a good GaN substrate with reduced warpage was successfully obtained.

さらに本発明の製造方法によって得られるGaN基板は、ラテラル成長したGaNを利用して作製するため、結晶欠陥の非常に少ないGaN基板を比較的厚い膜で得ることができ、またGaNの劈開により共振面を作製出来ることから、特に層構成の複雑な窒化物半導体レーザ素子の作製に有用である。  Furthermore, since the GaN substrate obtained by the manufacturing method of the present invention is fabricated using laterally grown GaN, a GaN substrate with very few crystal defects can be obtained as a relatively thick film, and resonance can be achieved by cleaving GaN. Since the surface can be produced, it is particularly useful for producing a nitride semiconductor laser device having a complicated layer structure.

すなわち、本発明は、
窒化物半導体基板上に積層された窒化物半導体を有する窒化物半導体素子の製造方法であって、
窒化物半導体と異なる異種基板上に、第1の窒化物半導体をラテラル成長させ、その上に第2の窒化物半導体を10μm以上400μm以下の厚さで成長させる第1の結晶成長工程と、
前記異種基板を除去して、前記窒化物半導体を、反りを有する窒化物半導体基板とする基板除去工程と、
前記窒化物半導体基板の上に、第3の窒化物半導体を10μm〜800μmの厚さで成長させる第2の結晶成長工程と、
前記第1の結晶成長工程で成長させた窒化物半導体及び前記第2の結晶成長工程で成長させた窒化物半導体を有する状態で、前記窒化物半導体基板の異種基板が除去された側を研磨して、前記ラテラル成長した窒化物半導体結晶の少なくとも一部を除去して、窒化物半導体基板の膜厚を小さくした窒化物半導体基板とする基板薄膜化工程と、
を具備することを特徴とする。
本発明の窒化物半導体素子の製造方法は、以下を組み合わせることができる。前記基板薄膜化工程において、研磨された窒化物半導体基板が反りを有する。前記基板除去工程において、異種基板を除去した後に、前記窒化物半導体基板の異種基板側を研磨して、窒化物半導体基板の膜厚を小さくする第1の基板研磨工程を具備する。前記基板研磨工程後に、窒化物半導体素子を有する窒化物半導体基板の研磨面側に、前記窒化物半導体基板を劈開する劈開工程を具備する。前記窒化物半導体素子がレーザ素子であり、該レーザ素子が前記劈開工程の劈開による共振面を有する。前記基板研磨工程後に、窒化物半導体素子を有する窒化物半導体基板の研磨面側に、電極を形成する工程を具備する。前記第1の結晶成長工程において、GaNからなる第1の層に凹凸を形成して、該第1の層上に窒化物半導体を成長させる。
また、本発明の他の態様を以下に示す。
GaN基板上に窒化物半導体を積層して窒化物半導体素子となるGaN基板の製造方法であって、
窒化物半導体と異なる異種基板上にラテラル成長によるGaNを含む第1の窒化物半導体層を成長させる第1の工程と、
その上に第2の窒化物半導体を成長させる第2の工程と、
第2の工程後、少なくとも異種基板までを除去する第3の工程と、
第3の工程後、第2の窒化物半導体の上に第3の窒化物半導体を成長させる第4の工程とを有することを特徴とする。
That is, the present invention
A method of manufacturing a nitride semiconductor device having a nitride semiconductor stacked on a nitride semiconductor substrate,
The nitride semiconductor different foreign substrate, the first nitride semiconductor is lateral growth, a first crystal growth step Ru second nitride semiconductor is grown with a thickness of 400μm or more 10μm thereon,
Removing the dissimilar substrate to make the nitride semiconductor a warped nitride semiconductor substrate; and
A second crystal growth step of growing a third nitride semiconductor on the nitride semiconductor substrate at a thickness of 10 μm to 800 μm ;
In the state having the nitride semiconductor grown in the first crystal growth step and the nitride semiconductor grown in the second crystal growth step, the side of the nitride semiconductor substrate from which the dissimilar substrate is removed is polished. Removing the laterally grown nitride semiconductor crystal, and reducing the thickness of the nitride semiconductor substrate to reduce the thickness of the nitride semiconductor substrate;
It is characterized by comprising.
The manufacturing method of the nitride semiconductor device of the present invention can combine the following. In the substrate thinning step, the polished nitride semiconductor substrate has a warp. The substrate removing step includes a first substrate polishing step of removing the dissimilar substrate and then polishing the dissimilar substrate side of the nitride semiconductor substrate to reduce the thickness of the nitride semiconductor substrate. After the substrate polishing step, a cleaving step of cleaving the nitride semiconductor substrate is provided on the polishing surface side of the nitride semiconductor substrate having a nitride semiconductor element. The nitride semiconductor element is a laser element, and the laser element has a resonance surface formed by cleavage in the cleavage step. After the substrate polishing step, the method includes a step of forming an electrode on the polishing surface side of the nitride semiconductor substrate having the nitride semiconductor element. In the first crystal growth step, irregularities are formed in the first layer made of GaN, and a nitride semiconductor is grown on the first layer.
Moreover, the other aspect of this invention is shown below.
A method of manufacturing a GaN substrate, which is a nitride semiconductor element obtained by laminating a nitride semiconductor on a GaN substrate,
A first step of growing a first nitride semiconductor layer containing GaN by lateral growth on a different substrate different from the nitride semiconductor;
A second step of growing a second nitride semiconductor thereon;
After the second step, a third step of removing at least the dissimilar substrate;
And a fourth step of growing a third nitride semiconductor on the second nitride semiconductor after the third step.

前記第1の工程は、異種基板上にGaNを成長させた後、そのGaN表面に凹凸を形成し、少なくとも凹部から凸部の表面にわたって、GaNをほぼ横方向に成長させる工程であることを特徴とする。  The first step is a step of growing GaN on a heterogeneous substrate, forming irregularities on the GaN surface, and growing GaN substantially laterally from at least the concave portion to the convex surface. And

前記第4の工程後、異種基板を除去した側から第2の窒化物半導体の一部または全部、あるいは第3の窒化物半導体の一部までを除去する第5の工程を有することを特徴とする。  After the fourth step, there is a fifth step of removing a part or all of the second nitride semiconductor or a part of the third nitride semiconductor from the side where the heterogeneous substrate is removed. To do.

前記第2の窒化物半導体層の厚さは、10μm以上400μm以下に調整することを特徴とし、前記第3の窒化物半導体層の厚さは、100μm以上400μm以下に調整することを特徴とする。  The thickness of the second nitride semiconductor layer is adjusted to 10 μm or more and 400 μm or less, and the thickness of the third nitride semiconductor layer is adjusted to 100 μm or more and 400 μm or less. .

さらに前記第1の工程はMOVPE法により、第2の工程および第4の工程はHVPE法により窒化物半導体を成長させることを特徴とする。  Further, the first step is characterized in that a nitride semiconductor is grown by MOVPE, and the second and fourth steps are grown by HVPE.

前記第5の工程後、GaN基板を研磨して厚さを100μm以上300μm以下にして、この上にデバイス構造を作製することを特徴とする。これは3層以上の構造を有するGaN基板の総膜厚をこの範囲とすることで、この上に窒化物半導体を積層して得られる窒化物半導体素子の特性が良好となる。  After the fifth step, the GaN substrate is polished to a thickness of 100 μm to 300 μm, and a device structure is fabricated thereon. This is because, by setting the total film thickness of the GaN substrate having a structure of three or more layers within this range, the characteristics of the nitride semiconductor element obtained by stacking the nitride semiconductor thereon are improved.

前記窒化物半導体と異なる異種基板は、C面を基準としてオフアングルされたサファイア基板を用いることを特徴とする。  The dissimilar substrate different from the nitride semiconductor is a sapphire substrate that is off-angled with respect to the C plane.

前記第2の窒化物半導体層および/または第3の窒化物半導体層に、SiあるいはSnをドープすることを特徴とする。  The second nitride semiconductor layer and / or the third nitride semiconductor layer is doped with Si or Sn.

以上説明したように、従来のGaN基板を得る方法では異種基板とGaNとの格子不整合により応力が発生し、基板に大きな反りが生じていたが、本発明の方法によると、異種基板側から研磨をしてGaNのみにすると反りが生じてしまうが、このGaN基板にさらに厚膜でGaNを積層することによって、異種基板とGaNとの格子不整合によって発生した際のひずみ応力が緩和され、反りが軽減し、良好なGaN基板が得られる。  As described above, in the conventional method of obtaining the GaN substrate, stress is generated due to lattice mismatch between the dissimilar substrate and GaN, and the substrate is greatly warped. However, according to the method of the present invention, from the dissimilar substrate side. When polishing and making only GaN, warping will occur, but by laminating GaN with a thick film on this GaN substrate, the strain stress generated due to lattice mismatch between the dissimilar substrate and GaN is relaxed, Warpage is reduced and a good GaN substrate can be obtained.

さらに本発明の製造方法によって得られるGaN基板は、エピタキシャル成長したGaNを利用して作製するため、非常に結晶欠陥が少ないGaN基板を比較的厚い膜で得ることができ、特に層構成の複雑な窒化物半導体レーザ素子の作製に有用である。  Furthermore, since the GaN substrate obtained by the manufacturing method of the present invention is produced by using epitaxially grown GaN, a GaN substrate with very few crystal defects can be obtained as a relatively thick film, and in particular, nitriding with a complicated layer structure. This is useful for manufacturing a semiconductor laser device.

以下、本発明について詳細に説明する。図1〜6は本発明の製造方法の具体例を示す模式図である。  Hereinafter, the present invention will be described in detail. FIGS. 1-6 is a schematic diagram which shows the specific example of the manufacturing method of this invention.

まず第1の工程として、図1に示すように、MOVPE法によりサファイア基板などの窒化物半導体と異なる異種基板1上に窒化物半導体の下地層を成長させこれを第1の層と称し、次にエピタキシャル成長による窒化物半導体を形成する。エピタキシャル成長とは結晶欠陥の少ない単結晶の成長をいい、特に窒化物半導体では厚さ方向に対して横方向に選択成長(ラテラル成長)させることで、結晶欠陥が厚さ方向に成長することがなくなり、良好なエピタキシャル成長層が得られることが知られている。  As a first step, as shown in FIG. 1, a nitride semiconductor underlayer is grown on a heterogeneous substrate 1 different from a nitride semiconductor such as a sapphire substrate by MOVPE, and this is referred to as a first layer. A nitride semiconductor is formed by epitaxial growth. Epitaxial growth refers to growth of a single crystal with few crystal defects. In particular, in a nitride semiconductor, crystal growth does not grow in the thickness direction by selective growth (lateral growth) in a direction transverse to the thickness direction. It is known that a good epitaxial growth layer can be obtained.

具体的に横方向に選択成長(ラテラル成長)させる方法としては、GaNからなる第1の層を形成し、この第1の層を部分的に凹凸を形成して(2a)凹部側面に窒化物半導体の横方向の成長が可能な面を露出させ、その上に窒化物半導体を成長させる(2b)。  Specifically, as a method of selectively growing in the lateral direction (lateral growth), a first layer made of GaN is formed, and the first layer is partially uneven (2a). A surface capable of lateral growth of the semiconductor is exposed, and a nitride semiconductor is grown thereon (2b).

その他にラテラル成長させる方法としては、GaNからなる窒化物半導体層上にSiO等のマスクを部分的に形成し(例えばストライプ状)、この上に窒化物半導体を成長させる。どちらの方法によっても窒化物半導体はラテラル成長し、どちらも結晶欠陥の非常に少ないエピタキシャル成長層は得られるが、SiO等のマスク材料は、窒化物半導体が良好な単結晶として得られる温度、例えば1000℃以上の温度で分解するおそれがあり、また窒化物半導体が異常成長する原因にもなるために、凹凸を形成する方法によってラテラル成長させる方が好ましい。As another lateral growth method, a mask such as SiO 2 is partially formed on a nitride semiconductor layer made of GaN (for example, in a stripe shape), and a nitride semiconductor is grown thereon. Both methods allow lateral growth of nitride semiconductors, and both can provide an epitaxially grown layer with very few crystal defects, but the mask material such as SiO 2 can be used at a temperature at which the nitride semiconductor is obtained as a good single crystal, for example, Since there is a risk of decomposition at a temperature of 1000 ° C. or higher, and also causes abnormal growth of the nitride semiconductor, it is preferable to perform lateral growth by a method of forming irregularities.

また、窒化物半導体と異なる異種基板1は、C面、R面、A面を含むサファイアの他、スピネル(MgAl)のような絶縁性基板、SiC(6H、4H、3Cを含む)、ZnS、ZnO、GaAs、Si等の従来知られている窒化物半導体と異なる基板材料を用いることができる。In addition, the heterogeneous substrate 1 different from the nitride semiconductor includes an insulating substrate such as spinel (MgAl 2 O 4 ), SiC (including 6H, 4H, and 3C) in addition to sapphire including C-plane, R-plane, and A-plane. A substrate material different from a conventionally known nitride semiconductor such as ZnS, ZnO, GaAs, or Si can be used.

また、本発明に用いる窒化物半導体と異なる異種基板1はステップ状にオフアングル(傾斜)された基板を用いることが望ましい。サファイア基板を用いる場合、サファイアA面に対し垂直(サファイアのM軸方向と平行)にオフアングルし、そのオフアングルのオフ角を0.1°〜0.3°の範囲にすることで、良好な窒化物半導体素子が得られる。  In addition, it is desirable that a different substrate 1 different from the nitride semiconductor used in the present invention is a step-off substrate (inclined). When using a sapphire substrate, the off-angle is perpendicular to the sapphire A plane (parallel to the M-axis direction of sapphire), and the off-angle of the off-angle is in the range of 0.1 ° to 0.3 °. A nitride semiconductor device can be obtained.

オフ角を0.1°〜0.3°の範囲にすると、HVPE法で積層した第2の窒化物半導体と第3の窒化物半導体の表面形態が、異種基板のステップに平行なすじ状となる。この窒化物半導体表面のステップ(段差に沿う方向)はレーザ素子を作製する際の導波路方向と同じとなり、導波路構造内にステップ状の段差ができることがなく、最も良い。さらに好ましくは0.15°〜0.25°とすると良い。  When the off-angle is in the range of 0.1 ° to 0.3 °, the surface forms of the second nitride semiconductor and the third nitride semiconductor stacked by the HVPE method are stripes parallel to the steps of the different substrates. Become. The step on the surface of the nitride semiconductor (the direction along the step) is the same as the waveguide direction when the laser element is manufactured, and it is best that there is no stepped step in the waveguide structure. More preferably, the angle is 0.15 ° to 0.25 °.

オフ角が0.1°より小さいか、またはオフアングルされていないサファイアを用いると、第2の窒化物半導体層と第3の窒化物半導体層の表面形態は六角錘状(または六角錘に似た形)となり、この上に作製する窒化物半導体表面にも六角パターンが反映され、素子特性が悪くなってしまう。また、オフ角が0.3°より大きいサファイアを用いると表面が荒れてしまい、サファイアのC面からのずれが大きくなり、エピタキシャル成長が困難になる。  When sapphire having an off-angle smaller than 0.1 ° or not off-angle is used, the surface forms of the second nitride semiconductor layer and the third nitride semiconductor layer are hexagonal pyramids (or similar to hexagonal pyramids). The hexagonal pattern is also reflected on the surface of the nitride semiconductor fabricated thereon, resulting in poor device characteristics. In addition, when sapphire with an off angle larger than 0.3 ° is used, the surface becomes rough, and the deviation of sapphire from the C-plane increases, making epitaxial growth difficult.

また、本発明のラテラル成長する第1の工程は繰り返し2回以上行っても良い。
繰り返し行うことで、その上に形成する窒化物半導体層の結晶欠陥の数をさらに少なくすることができる。繰り返してラテラル成長を形成する際は、そのまえに行ったラテラル成長の際の凹凸に対して、凸部上に凹部、凹部上に凸部となるように形成する。
The first step of lateral growth of the present invention may be repeated twice or more.
By repeating the process, the number of crystal defects in the nitride semiconductor layer formed thereon can be further reduced. When the lateral growth is repeatedly formed, the concave and convex portions are formed on the convex portion and the convex portion on the concave portion with respect to the concave and convex portions at the time of the lateral growth performed before that.

次に第2の工程として、図2に示すように、エピタキシャル成長した第1の窒化物半導体層2上にHVPE法を用いて第2の窒化物半導体3を成長させる。このHVPE法による窒化物半導体は厚膜で形成し、下地層を含めて400μm以下にすることが望ましい。400μmより厚く成長すると、異種基板との格子不整合あるいは熱膨張係数差によって発生する反りが大きくなりすぎてしまい、素子構造となる窒化物半導体を積層する際に不都合が生じてしまう。これは窒化物半導体と異種基板との間で発生する格子不整合あるいは熱膨張係数差によるひずみが、はじめは異種基板の方が膜厚が大きいために格子不整合あるいは熱膨張係数差によって発生する応力は異種基板1に依存し、窒化物半導体の方がひずみ応力を受けた状態となっていた。しかし、窒化物半導体が400μmより大きくなると、次第に応力は窒化物半導体に依存するようになってくるため、窒化物半導体にかかっていたひずみ応力が緩和されはじめ、今度は異種基板の方がひずみ応力を受けるようになり、そこで大きな反りが発生してしまう。  Next, as a second step, as shown in FIG. 2, a second nitride semiconductor 3 is grown on the epitaxially grown first nitride semiconductor layer 2 using the HVPE method. The nitride semiconductor formed by the HVPE method is preferably formed as a thick film and is 400 μm or less including the base layer. When grown to a thickness of more than 400 μm, warpage caused by lattice mismatch with a different substrate or a difference in thermal expansion coefficient becomes too large, which causes inconvenience when stacking nitride semiconductors that form an element structure. This is caused by lattice mismatch or thermal expansion coefficient difference between the nitride semiconductor and the dissimilar substrate, and initially due to lattice mismatch or thermal expansion coefficient difference because the dissimilar substrate has a larger film thickness. The stress depends on the dissimilar substrate 1, and the nitride semiconductor is in a state of receiving a strain stress. However, when the nitride semiconductor becomes larger than 400 μm, since the stress gradually depends on the nitride semiconductor, the strain stress applied to the nitride semiconductor starts to be relieved. Will receive a large warp there.

さらにこの第2の工程を行うことによって次のような効果もある。第1の工程においてラテラル成長による第1の窒化物半導体層2を成長させた場合、第1の窒化物半導体層表面では結晶欠陥の数が不均一であったものが、第2の窒化物半導体層3を成長させると、第2の窒化物半導体中で結晶欠陥が拡散され、第2の窒化物半導体層表面ではほぼ均一となり、その上に成長させる窒化物半導体も均一な層として成長させることができる。  Further, the following effects can be obtained by performing the second step. When the first nitride semiconductor layer 2 is grown by lateral growth in the first step, the number of crystal defects on the surface of the first nitride semiconductor layer is not uniform. When the layer 3 is grown, crystal defects are diffused in the second nitride semiconductor, become substantially uniform on the surface of the second nitride semiconductor layer, and the nitride semiconductor grown thereon grows as a uniform layer. Can do.

またこの第2の窒化物半導体層3を成長させるとき、SiあるいはSnのn型不純物をドープすることが望ましい。これはn電極とのオーミック性を良くするためで、GaN基板上にn層、活性層、p層の順に素子構造を形成した場合、p層側にp電極を形成して、p電極とは反対のn層側すなわちGaN基板にn電極を形成する場合に、SiまたはSnをドープすると、オーミック性が良好となる。  Further, when the second nitride semiconductor layer 3 is grown, it is desirable to dope an Si or Sn n-type impurity. This is to improve the ohmic property with the n-electrode. When an element structure is formed on the GaN substrate in the order of the n layer, the active layer, and the p-layer, the p-electrode is formed on the p-layer side. When the n electrode is formed on the opposite n layer side, that is, on the GaN substrate, doping with Si or Sn improves the ohmic property.

このSiまたはSnのn型不純物は、5×1016/cm〜5×1021/cmの範囲でドープすることが望ましい。5×1016/cmより少ないと、オーミック性が悪くなってしまい、また5×1021/cmより多いと、不純物濃度が大きいために結晶性が悪くなり、結晶欠陥が増大する傾向にある。好ましい範囲としては、1×1017/cm〜1×1020/cmとする。The n-type impurity of Si or Sn is preferably doped in the range of 5 × 10 16 / cm 3 to 5 × 10 21 / cm 3 . When the amount is less than 5 × 10 16 / cm 3 , ohmic properties are deteriorated. When the amount is more than 5 × 10 21 / cm 3 , the crystallinity is deteriorated due to a large impurity concentration, and crystal defects tend to increase. is there. A preferable range is 1 × 10 17 / cm 3 to 1 × 10 20 / cm 3 .

次に第3の工程として、図3に示すように、第2の窒化物半導体3までを形成した後、異種基板1の露出した面側から研磨していき、少なくとも異種基板までを除去する。研磨により取り除く層はSiO等のマスク材料を用いてエピタキシャル成長層を形成した場合はマスク材料等までを除去することが望ましい。この異種基板1を研磨により除去していくと、前述の説明と同じように、異種基板に依存していた応力が窒化物半導体に依存するようになり、結果的に異種基板1をすべて除去した段階で、大きく反った状態の窒化物半導体が得られる。Next, as a third step, as shown in FIG. 3, after forming up to the second nitride semiconductor 3, polishing is performed from the exposed surface side of the heterogeneous substrate 1, and at least the heterogeneous substrate is removed. When the epitaxial growth layer is formed using a mask material such as SiO 2, the layer removed by polishing is desirably removed up to the mask material. When this heterogeneous substrate 1 is removed by polishing, the stress dependent on the heterogeneous substrate becomes dependent on the nitride semiconductor, as described above, and as a result, all the heterogeneous substrate 1 is removed. A nitride semiconductor in a greatly warped state is obtained in stages.

この大きく反りのある窒化物半導体を次に第4の工程として、図4に示すように、HVPE法を用いて第3の窒化物半導体4を成長させる。このHVPEによる第3の窒化物半導体4を厚膜で形成することで反りの軽減したGaN基板が得られる。これは異種基板1との格子不整合によってひずみ応力を受けた第2の窒化物半導体3が、異種基板が除去された状態でさらに窒化物半導体を積層していくことで、次第にひずみ応力が取り除かれるようになり、反りが軽減したと考えられる。この第3の窒化物半導体は10μm〜800μmで形成し、好ましくは200μm〜500μmで形成する。  Next, as shown in FIG. 4, a third nitride semiconductor 4 is grown by using the HVPE method as a fourth step of the nitride semiconductor having large warpage. A GaN substrate with reduced warpage can be obtained by forming the third nitride semiconductor 4 by HVPE as a thick film. This is because the second nitride semiconductor 3 that has been subjected to strain stress due to lattice mismatch with the heterogeneous substrate 1 is further laminated with the nitride semiconductor stacked in a state where the heterogeneous substrate is removed, so that the strain stress is gradually removed. It seems that warpage has been reduced. The third nitride semiconductor is formed with a thickness of 10 μm to 800 μm, preferably with a thickness of 200 μm to 500 μm.

次に好ましくは第5の工程として、図5に示すように、得られたGaN基板を異種基板1を除去した側から第2の窒化物半導体3の一部または全部、あるいは第3の窒化物半導体4の一部までを除去する。これは第1の窒化物半導体2はラテラル成長を得るために、SiO等のマスクを含んでいたり、凹凸を形成した上に窒化物半導体を形成したりしており、ひずみ応力が取り除かれにくくなっているため、第1の窒化物半導体層および第2の窒化物半導体層の一部または全部を研磨により除去することが望ましい。この研磨によって最終的なGaN基板としての膜厚は、50μm〜500μm、好ましくは100μm〜300μmとする。Next, preferably, as a fifth step, as shown in FIG. 5, a part or all of the second nitride semiconductor 3 or the third nitride is obtained from the side of the obtained GaN substrate from which the heterogeneous substrate 1 is removed. A part of the semiconductor 4 is removed. This is because the first nitride semiconductor 2 includes a mask of SiO 2 or the like in order to obtain lateral growth, or a nitride semiconductor is formed on an uneven surface, and strain stress is difficult to be removed. Therefore, it is desirable to remove part or all of the first nitride semiconductor layer and the second nitride semiconductor layer by polishing. By this polishing, the final film thickness of the GaN substrate is 50 μm to 500 μm, preferably 100 μm to 300 μm.

以上のようにして作製したGaN基板4’を用いると、GaN基板上にn型窒化物半導体、活性層、p型窒化物半導体を形成して窒化物半導体素子を作製したとき、反りも小さく、また欠陥も少ないために、歩留が良く、発光効率の優れた窒化物半導体素子が得られる。
[実施例1]
異種基板1として、2インチφ、C面を主面とし、オリフラ面をA面とするサファイア基板1をMOVPE反応容器内にセットし、温度を510℃にして、キャリアガスに水素、原料ガスにアンモニアとTMG(トリメチルガリウム)とを用い、サファイア基板1上にGaNよりなるバッファ層(図示されていない)を約200オングストロームの膜厚で成長させる。
When the GaN substrate 4 ′ manufactured as described above is used, when a nitride semiconductor device is manufactured by forming an n-type nitride semiconductor, an active layer, and a p-type nitride semiconductor on the GaN substrate, warpage is small, In addition, since there are few defects, a nitride semiconductor device with good yield and excellent luminous efficiency can be obtained.
[Example 1]
As a heterogeneous substrate 1, a sapphire substrate 1 having a 2 inch φ, C-plane as the main surface and an orientation flat surface as the A-plane is set in the MOVPE reaction vessel, the temperature is set to 510 ° C., the carrier gas is hydrogen, the source gas is A buffer layer (not shown) made of GaN is grown on the sapphire substrate 1 to a thickness of about 200 Å using ammonia and TMG (trimethylgallium).

バッファ層を成長後、TMGのみ止めて、温度を1050℃まで上昇させる。1050℃になったら、さらにTMGを用いて、GaNよりなる窒化物半導体層2を2.5μmの膜厚で成長させる。  After growing the buffer layer, only TMG is stopped and the temperature is raised to 1050 ° C. When the temperature reaches 1050 ° C., the nitride semiconductor layer 2 made of GaN is further grown to a thickness of 2.5 μm using TMG.

窒化物半導体層2を成長後、ストライプ状のフォトマスクを形成し、CVD装置によりストライプ幅(凸部の上部になる部)2μm、ストライプ間隔(凹部の底部となる部分)10μmにパターニングされたSiO膜を形成し、続いて、RIE装置によりSiO膜の形成されていない部分の第1の窒化物半導体層2を第1の窒化物半導体2が残る程度に途中までエッチングして凹凸を形成することにより、凹部側面に第1の窒化物半導体2を露出させる(図1の2a)。図1のように凹凸を形成した後、凸部上部のSiOを除去する。なお、ストライプ方向は、図6に示すように、オリフラ面に対して垂直な方向(GaNのM軸方向)で形成する。After the nitride semiconductor layer 2 is grown, a striped photomask is formed, and is patterned with a CVD apparatus to a stripe width (a portion that becomes the top of the convex portion) of 2 μm and a stripe interval (a portion that becomes the bottom of the concave portion) of 10 μm. 2 films are formed, and then the RIE apparatus is used to etch the first nitride semiconductor layer 2 where the SiO 2 film is not formed halfway to the extent that the first nitride semiconductor 2 remains, thereby forming irregularities. Thus, the first nitride semiconductor 2 is exposed on the side surface of the recess (2a in FIG. 1). After forming the unevenness as shown in FIG. 1, the SiO 2 on the upper portion of the convex portion is removed. The stripe direction is formed in a direction perpendicular to the orientation flat surface (M-axis direction of GaN) as shown in FIG.

次に、MOVPE反応容器内にセットし、温度を1050℃で、原料ガスにTMG、アンモニアを用い、アンドープのGaNよりなる窒化物半導体層2bを15μmの膜厚で成長させ、これを第1の窒化物半導体層2とする。  Next, it is set in a MOVPE reaction vessel, a temperature is set to 1050 ° C., TMG and ammonia are used as source gases, and a nitride semiconductor layer 2b made of undoped GaN is grown to a thickness of 15 μm. The nitride semiconductor layer 2 is used.

第1の窒化物半導体層2を成長後、続いてウエハーをHVPE装置に移し、温度を1050℃で、原料ガスに塩化ガリウム、アンモニア、シランガスを用い、Siを1×1018/cmドープしたGaNよりなる第2の窒化物半導体層3を250μmの膜厚で成長させる。After the growth of the first nitride semiconductor layer 2, the wafer was subsequently transferred to an HVPE apparatus, the temperature was 1050 ° C., gallium chloride, ammonia, and silane gas were used as source gases, and Si was doped at 1 × 10 18 / cm 3 . A second nitride semiconductor layer 3 made of GaN is grown to a thickness of 250 μm.

このとき結晶欠陥の数を断面TEM(透過電子顕微鏡)により観察すると、第1の窒化物半導体層2表面での結晶欠陥密度は凸部上で1010個/cmであり、凹部上で10個/cm以下であったものが、第2の窒化物半導体層3表面ではほぼ均一で10個/cmになった。At this time, when the number of crystal defects is observed with a cross-sectional TEM (transmission electron microscope), the crystal defect density on the surface of the first nitride semiconductor layer 2 is 10 10 pieces / cm on the convex portion and 10 4 on the concave portion. The number of particles / cm 2 or less was approximately uniform on the surface of the second nitride semiconductor layer 3 and was 10 6 / cm 2 .

続いてウエハーを反応容器から取り出し、サファイア基板側から、サファイア基板1が完全に除去されて下地層のGaNが露出するまで研磨していく。このサファイア基板がすべて取り除かれた状態ではウエハーは大きく反った状態となっている。  Subsequently, the wafer is taken out of the reaction vessel and polished from the sapphire substrate side until the sapphire substrate 1 is completely removed and the underlying GaN is exposed. When the sapphire substrate is completely removed, the wafer is greatly warped.

次に、サファイア基板の取り除かれたウエハーを再びHVPE装置に移し、同じく温度を1050℃で、原料ガスに塩化ガリウム、アンモニア、シランガスを用い、Siを1×1018/cmドープしたGaNよりなる第3の窒化物半導体層4を300μmの膜厚で成長させる。この第3の窒化物半導体層を成長させることで反りは軽減される。Next, the wafer from which the sapphire substrate has been removed is transferred again to the HVPE apparatus, and is similarly made of GaN doped with Si at 1 × 10 18 / cm 3 using gallium chloride, ammonia, silane gas as source gases at 1050 ° C. The third nitride semiconductor layer 4 is grown to a thickness of 300 μm. The warp is reduced by growing the third nitride semiconductor layer.

第3の窒化物半導体層4を成長後、ウエハーを反応容器から取り出し、先ほど除去したサファイア基板側から、第1の窒化物半導体層2、および第2の窒化物半導体層3の一部までを研磨していき、最終的に総膜厚が250μmのGaN基板4’にする。  After the third nitride semiconductor layer 4 is grown, the wafer is taken out from the reaction vessel, and the first nitride semiconductor layer 2 and a part of the second nitride semiconductor layer 3 are removed from the sapphire substrate side removed earlier. Polishing is finally performed to obtain a GaN substrate 4 ′ having a total film thickness of 250 μm.

得られたGaN基板4’は反りが小さく、また欠陥も少ないために、このGaN上に形成した窒化物半導体素子は、歩留が良く、また発光効率の優れたものが得られた。  Since the obtained GaN substrate 4 ′ had a small warp and few defects, a nitride semiconductor device formed on the GaN had a good yield and an excellent luminous efficiency.

[実施例2]
実施例1と同様にしてGaN基板4’を作製する。得られたGaN基板上に図7に示すようにInGaNよりなるクラック防止層(これは省略が可能である)、AlGaNとSiドープのGaNとの超格子からなるn側クラッド層6、GaNよりなるn側光ガイド層7、InGaNよりなる多重量子井戸構造(MQW)の活性層8、MgドープのAlGaNよりなるp側キャップ層9、MgドープのGaNよりなるp側光ガイド層10、AlGaNとMgドープのGaNとの超格子からなるp側クラッド層11、MgドープのGaNよりなるp側コンタクト層12を順に積層する。
[Example 2]
A GaN substrate 4 ′ is produced in the same manner as in Example 1. On the obtained GaN substrate, as shown in FIG. 7, a crack prevention layer made of InGaN (this can be omitted), an n-side cladding layer 6 made of a superlattice of AlGaN and Si-doped GaN, made of GaN An n-side light guide layer 7, an active layer 8 having a multiple quantum well structure (MQW) made of InGaN, a p-side cap layer 9 made of Mg-doped AlGaN, a p-side light guide layer 10 made of Mg-doped GaN, AlGaN and Mg A p-side cladding layer 11 made of a superlattice with doped GaN and a p-side contact layer 12 made of Mg-doped GaN are sequentially stacked.

積層後、p側コンタクト層12とp側クラッド層11とをエッチングして表面をリッジ形状とし、リッジ上にZrOなどの絶縁膜31とpオーミック電極20を形成し、最後にpパッド電極21を、またp電極とは反対のGaN基板側にnオーミック電極22とnパッド電極23を形成し、最後にGaNの劈開により共振面を形成し、チップ化する。After the lamination, the p-side contact layer 12 and the p-side cladding layer 11 are etched to form a ridge-shaped surface, an insulating film 31 such as ZrO 2 and the p ohmic electrode 20 are formed on the ridge, and finally the p pad electrode 21 The n-ohmic electrode 22 and the n-pad electrode 23 are formed on the GaN substrate side opposite to the p-electrode, and finally, a resonance surface is formed by cleaving GaN to form a chip.

以上のようにして窒化物半導体レーザ素子を得て、これをフェースアップ(基板とヒートシンクとが対抗した状態)でヒートシンクに設置し、それぞれの電極をワイヤーボンディングして、室温で連続発振を試みたところ、閾値電流密度2kA/cm、20mWの出力において、連続発振が確認され、2000時間以上の寿命を示した。A nitride semiconductor laser device was obtained as described above, and this was placed on the heat sink face-up (in a state where the substrate and the heat sink faced each other). Each electrode was wire-bonded, and continuous oscillation was attempted at room temperature. However, continuous oscillation was confirmed at a threshold current density of 2 kA / cm 2 and an output of 20 mW, indicating a lifetime of 2000 hours or more.

[実施例3]
実施例2と同様にして、実施例1によって得られたGaN基板上に図8に示すように素子構造としてAlGaNからなるn側コンタクト層5、クラック防止層(省略可能)、n側クラッド層6、n側光ガイド層7、活性層8、p側キャップ層9、p側光ガイド層10、p側クラッド層11、p側コンタクト層12を積層する。
[Example 3]
In the same manner as in Example 2, on the GaN substrate obtained in Example 1, as shown in FIG. 8, an n-side contact layer 5 made of AlGaN as an element structure, a crack prevention layer (can be omitted), and an n-side cladding layer 6 The n-side light guide layer 7, the active layer 8, the p-side cap layer 9, the p-side light guide layer 10, the p-side cladding layer 11, and the p-side contact layer 12 are laminated.

次にp側コンタクト層12の一部をエッチングしてn側コンタクト層5を露出させる。さらにp側層をp側クラッド層11までRIEによりドライエッチングしてリッジを形成し、リッジ上に保護膜としてZrOなどの絶縁膜31とそれぞれのコンタクト層上にpオーミック電極20とpパッド電極21、nオーミック電極22とnパッド電極23を形成し、最後にGaNの劈開により共振面を形成し、チップ化する。Next, a part of the p-side contact layer 12 is etched to expose the n-side contact layer 5. Further, the p-side layer is dry-etched to the p-side cladding layer 11 by RIE to form a ridge, an insulating film 31 such as ZrO 2 as a protective film on the ridge, and a p-ohmic electrode 20 and a p-pad electrode on each contact layer 21. An n-ohmic electrode 22 and an n-pad electrode 23 are formed. Finally, a resonant surface is formed by cleaving GaN to form a chip.

以上のようにして窒化物半導体レーザ素子を得て、これをフェースアップ(基板とヒートシンクとが対抗した状態)でヒートシンクに設置し、それぞれの電極をワイヤーボンディングして、室温で連続発振を試みたところ、閾値電流密度2kA/cm、20mWの出力において、連続発振が確認され、1000時間以上の寿命を示した。A nitride semiconductor laser device was obtained as described above, and this was placed on the heat sink face-up (in a state where the substrate and the heat sink faced each other). Each electrode was wire-bonded, and continuous oscillation was attempted at room temperature. However, continuous oscillation was confirmed at a threshold current density of 2 kA / cm 2 and an output of 20 mW, indicating a lifetime of 1000 hours or more.

[実施例4]
異種基板1として、2インチφ、C面を主面とし、オリフラ面をA面とするサファイア基板1をMOVPE反応容器内にセットし、温度を510℃にして、キャリアガスに水素、原料ガスにアンモニアとTMG(トリメチルガリウム)とを用い、サファイア基板1上にGaNよりなるバッファ層(図示されていない)を約200オングストロームの膜厚で成長させる。
[Example 4]
As a heterogeneous substrate 1, a sapphire substrate 1 having a 2 inch φ, C-plane as the main surface and an orientation flat surface as the A-plane is set in the MOVPE reaction vessel, the temperature is set to 510 ° C., the carrier gas is hydrogen, the source gas is A buffer layer (not shown) made of GaN is grown on the sapphire substrate 1 to a thickness of about 200 Å using ammonia and TMG (trimethylgallium).

バッファ層を成長後、TMGのみ止めて、温度を1050℃まで上昇させる。1050℃になったら、さらにTMGを用いて、GaNよりなる窒化物半導体層2aを2.5μmの膜厚で成長させる。  After growing the buffer layer, only TMG is stopped and the temperature is raised to 1050 ° C. When the temperature reaches 1050 ° C., a nitride semiconductor layer 2a made of GaN is grown to a thickness of 2.5 μm using TMG.

窒化物半導体層2aを成長後、ストライプ状のフォトマスクを形成し、CVD装置によりストライプ幅10μm、窓部2μmのSiOよりなる保護膜30を0.5μmの膜厚で形成する。ストライプ方向は、オリフラ面に対して垂直な方向で形成する。After growing the nitride semiconductor layer 2a, a striped photomask is formed, and a protective film 30 made of SiO 2 having a stripe width of 10 μm and a window portion of 2 μm is formed to a thickness of 0.5 μm by a CVD apparatus. The stripe direction is formed in a direction perpendicular to the orientation flat surface.

保護膜30形成後、ウエハーをMOVPE反応容器に移し、1050℃にて、原料ガスにTMG、アンモニアを用い、アンドープのGaNよりなる窒化物半導体層2bを15μmの膜厚で成長させ、これを第1の窒化物半導体層2とする。  After the protective film 30 is formed, the wafer is transferred to a MOVPE reaction vessel, and at 1050 ° C., TMG and ammonia are used as source gases, and a nitride semiconductor layer 2b made of undoped GaN is grown to a thickness of 15 μm. 1 nitride semiconductor layer 2.

第1の窒化物半導体層2を成長後、続いてウエハーをHVPE装置に移し、温度を1050℃で、原料ガスに塩化ガリウム、アンモニア、シランガスを用い、Siを1×1018/cmドープしたGaNよりなる第2の窒化物半導体層3を250μmの膜厚で成長させる(図6)。After the growth of the first nitride semiconductor layer 2, the wafer was subsequently transferred to an HVPE apparatus, the temperature was 1050 ° C., gallium chloride, ammonia, and silane gas were used as source gases, and Si was doped at 1 × 10 18 / cm 3 . A second nitride semiconductor layer 3 made of GaN is grown to a thickness of 250 μm (FIG. 6).

このとき結晶欠陥の数を断面TEM(透過電子顕微鏡)により観察すると、第1の窒化物半導体層表面での結晶欠陥密度は凸部上で10個/cmであり、凹部上で1010個/cm以下であったものが、第2の窒化物半導体層上ではほぼ均一で10個/cmになった。At this time, when the number of crystal defects is observed with a cross-sectional TEM (transmission electron microscope), the crystal defect density on the surface of the first nitride semiconductor layer is 10 4 / cm 2 on the convex portion and 10 10 on the concave portion. The number of pieces / cm 2 or less was almost uniform on the second nitride semiconductor layer, which was 10 6 pieces / cm 2 .

続いてウエハーを反応容器から取り出し、サファイア基板側から、第1の窒化物半導体層2の一部までを研磨していき、サファイア基板および、保護膜のSiOを完全に除去する。このサファイアおよびSiOがすべて取り除かれた状態ではウエハーは大きく反った状態となっている。Subsequently, the wafer is taken out from the reaction container, and the part of the first nitride semiconductor layer 2 is polished from the sapphire substrate side to completely remove the sapphire substrate and SiO 2 of the protective film. When all of the sapphire and SiO 2 are removed, the wafer is greatly warped.

次に、サファイア基板1の取り除かれたウエハーを再びHVPE装置に移し、同じく温度を1050℃で、原料ガスに塩化ガリウムTMG、アンモニア、シランガスを用い、Siを1×1018/cmドープしたGaNよりなる第3の窒化物半導体層を300μmの膜厚で成長させる。この第3の窒化物半導体層4を成長させることで反りは軽減される。Next, the wafer from which the sapphire substrate 1 has been removed is transferred again to the HVPE apparatus. Similarly, the temperature is 1050 ° C., gallium chloride TMG, ammonia, silane gas is used as the source gas, and GaN doped with Si at 1 × 10 18 / cm 3 is used. A third nitride semiconductor layer is grown to a thickness of 300 μm. The warpage is reduced by growing the third nitride semiconductor layer 4.

第3の窒化物半導体層4を成長後、ウエハーを反応容器から取り出し、先ほど除去したサファイア基板側から、残りの第1の窒化物半導体層2、および第2の窒化物半導体層3の一部までを研磨していき、最終的に総膜厚が250μmのGaN基板4’にする。  After the third nitride semiconductor layer 4 is grown, the wafer is taken out of the reaction vessel, and the remaining first nitride semiconductor layer 2 and a part of the second nitride semiconductor layer 3 are removed from the sapphire substrate side removed earlier. The final GaN substrate 4 ′ having a total film thickness of 250 μm is obtained.

得られたGaN基板4’は反りが小さく、また欠陥も少ないために、このGaN上に形成した窒化物半導体素子は,歩留が良く,また発光効率の優れたものが得られた。  Since the obtained GaN substrate 4 ′ has a small warp and few defects, a nitride semiconductor device formed on the GaN has a good yield and an excellent luminous efficiency.

[実施例5]
実施例1において、第3の窒化物半導体4をアンドープのGaNとした他は同様にして、GaN基板4’を得た。
[Example 5]
A GaN substrate 4 ′ was obtained in the same manner as in Example 1, except that the third nitride semiconductor 4 was undoped GaN.

このGaN基板4’上に図7に示すように、InGaNよりなるクラック防止層(これは省略が可能である)、AlGaNとSiドープのGaNとの超格子からなるn側クラッド層6、GaNよりなるn側光ガイド層7、InGaNよりなる多重量子井戸構造(MQW)の活性層8、MgドープのAlGaNよりなるp側キャップ層9、MgドープのGaNよりなるp側光ガイド層10、AlGaNとMgドープのGaNとの超格子からなるp側クラッド層11、MgドープのGaNよりなるp側コンタクト層12を順に積層する。  On the GaN substrate 4 ′, as shown in FIG. 7, a crack prevention layer made of InGaN (this can be omitted), an n-side cladding layer 6 made of a superlattice of AlGaN and Si-doped GaN, and from GaN An n-side optical guide layer 7, an active layer 8 having a multiple quantum well structure (MQW) made of InGaN, a p-side cap layer 9 made of Mg-doped AlGaN, a p-side light guide layer 10 made of Mg-doped GaN, AlGaN A p-side cladding layer 11 made of a superlattice with Mg-doped GaN and a p-side contact layer 12 made of Mg-doped GaN are sequentially stacked.

積層後、p側コンタクト層とp側クラッド層とをエッチングして表面をリッジ形状とし、リッジ上にZrOなどの絶縁膜31とpオーミック電極20を形成し、最後にpパッド電極21を、またp電極とは反対のGaN基板側にnオーミック電極22とnパッド電極23を形成し、最後にGaNの劈開により共振面を形成し、チップ化する。After the lamination, the p-side contact layer and the p-side cladding layer are etched to form a ridge shape, and an insulating film 31 such as ZrO 2 and a p ohmic electrode 20 are formed on the ridge, and finally the p pad electrode 21 is formed. Further, an n ohmic electrode 22 and an n pad electrode 23 are formed on the side of the GaN substrate opposite to the p electrode, and finally a resonance surface is formed by cleaving GaN to form a chip.

以上のようにして窒化物半導体レーザ素子を得て、これをフェースアップ(基板とヒートシンクとが対抗した状態)でヒートシンクに設置し、それぞれの電極をワイヤーボンディングして、室温で連続発振を試みたところ、閾値電流密度2kA/cm、20mWの出力において、連続発振が確認され、1000時間以上の寿命を示した。A nitride semiconductor laser device was obtained as described above, and this was placed on the heat sink face-up (in a state where the substrate and the heat sink faced each other). Each electrode was wire-bonded, and continuous oscillation was attempted at room temperature. However, continuous oscillation was confirmed at a threshold current density of 2 kA / cm 2 and an output of 20 mW, indicating a lifetime of 1000 hours or more.

[実施例6]
異種基板1として、2インチφ、C面を主面とし、オリフラ面をA面とするサファイア基板1において、さらにステップ上にオファングルされ、そのオフ角が0.13°、ステップに沿う方向(段差方向)がA面に垂直に形成された基板を用いる他は実施例2と同様にして窒化物半導体レーザ素子を得て、室温で連続発振を試みたところ、閾値電流密度2kA/cm、20mWの出力において、連続発振が確認され、3000時間以上の寿命を示した。
[Example 6]
In the sapphire substrate 1 having a 2 inch φ, C-plane as the main surface and the orientation flat surface as the A-plane as the heterogeneous substrate 1, it is further over-stepped, its off-angle is 0.13 °, and the direction along the step (step) A nitride semiconductor laser device was obtained in the same manner as in Example 2 except that a substrate whose direction was perpendicular to the A plane was used, and when continuous oscillation was attempted at room temperature, the threshold current density was 2 kA / cm 2 and 20 mW. In the output, continuous oscillation was confirmed, indicating a lifetime of 3000 hours or more.

[実施例7]
実施例1と同様にしてGaN基板4’を作製する。得られたGaN基板上にAlGaNよりなるn側コンタクト層5、InGaNよりなるクラック防止層(これは省略が可能である)、AlGaNとSiドープのGaNとの超格子からなるn側クラッド層6、InGaNよりなる多重量子井戸構造(MQW)の活性層8、MgドープのAlGaNよりなるp側キャップ層9、AlGaNとMgドープのGaNとの超格子からなるp側クラッド層11、MgドープのGaNよりなるp側コンタクト層12を順に積層する。
[Example 7]
A GaN substrate 4 ′ is produced in the same manner as in Example 1. An n-side contact layer 5 made of AlGaN, a crack prevention layer made of InGaN (this can be omitted), an n-side cladding layer 6 made of a superlattice of AlGaN and Si-doped GaN on the obtained GaN substrate, Multiple quantum well structure (MQW) active layer 8 made of InGaN, p-side cap layer 9 made of Mg-doped AlGaN, p-side cladding layer 11 made of a superlattice of AlGaN and Mg-doped GaN, and Mg-doped GaN The p-side contact layer 12 is sequentially laminated.

積層後、p側コンタクト層12上にpオーミック電極(透明電極)20とpパッド電極21を形成し、p電極とは反対のGaN基板側にnオーミック電極22と、nパッド電極23を形成し、最後にGaNの劈開によりチップ化する。  After the lamination, a p-ohmic electrode (transparent electrode) 20 and a p-pad electrode 21 are formed on the p-side contact layer 12, and an n-ohmic electrode 22 and an n-pad electrode 23 are formed on the GaN substrate side opposite to the p-electrode. Finally, a chip is formed by cleaving GaN.

以上のようにして得られたLED素子は順方向電流20mAにおいて、順方向電圧3.4V、465nmの青色発光を示し、発光出力は9mWであった。  The LED element obtained as described above emitted blue light with a forward voltage of 3.4 V and 465 nm at a forward current of 20 mA, and the light emission output was 9 mW.

本発明の第1の工程を説明するGaN基板の構造を示す模式断面図。  The schematic cross section which shows the structure of the GaN substrate explaining the 1st process of this invention. 本発明の第2の工程を説明するGaN基板の構造を示す模式断面図。  The schematic cross section which shows the structure of the GaN substrate explaining the 2nd process of this invention. 本発明の第3の工程を説明するGaN基板の構造を示す模式断面図。  The schematic cross section which shows the structure of the GaN substrate explaining the 3rd process of this invention. 本発明の第4の工程を説明するGaN基板の構造を示す模式断面図。  The schematic cross section which shows the structure of the GaN substrate explaining the 4th process of this invention. 本発明の第5の工程を説明するGaN基板の構造を示す模式断面図。  The schematic cross section which shows the structure of the GaN substrate explaining the 5th process of this invention. 本発明の他の実施例を説明するGaN基板を用いたレーザ素子の構造を示す模式断面図。  FIG. 6 is a schematic cross-sectional view showing the structure of a laser device using a GaN substrate for explaining another embodiment of the present invention. 本発明の実施例によって得られるGaN基板を用いたレーザ素子の構造を示す模式断面図。  The schematic cross section which shows the structure of the laser element using the GaN substrate obtained by the Example of this invention. 本発明の他の実施例によって得られるGaN基板を用いたレーザ素子の構造を示す模式断面図。  The schematic cross section which shows the structure of the laser element using the GaN substrate obtained by the other Example of this invention. 本発明の他の実施例によって得られるGaN基板を用いたレーザ素子の構造を示す模式断面図。  The schematic cross section which shows the structure of the laser element using the GaN substrate obtained by the other Example of this invention.

符号の説明Explanation of symbols

1・・・異種基板
2・・・第1の窒化物半導体層
3・・・第2の窒化物半導体層4・・・第3の窒化物半導体層
4’・・・GaN基板
5・・・n側コンタクト層
6・・・n側クラッド層
7・・・n側光ガイド層
8・・・活性層
9・・・p側キャップ層
10・・・p側光ガイド層
11・・・p側クラッド層
12・・・p側コンタクト層
20・・・pオーミック電極
21・・・pパッド電極
22・・・nオーミック電極
23・・・nパッド電極
30・・・SiO
31・・・絶縁膜
DESCRIPTION OF SYMBOLS 1 ... Dissimilar substrate 2 ... 1st nitride semiconductor layer 3 ... 2nd nitride semiconductor layer 4 ... 3rd nitride semiconductor layer 4 '... GaN substrate 5 ... n-side contact layer 6 ... n-side cladding layer 7 ... n-side light guide layer 8 ... active layer 9 ... p-side cap layer 10 ... p-side light guide layer 11 ... p-side Cladding layer 12 ... p-side contact layer 20 ... p ohmic electrode 21 ... p pad electrode 22 ... n ohmic electrode 23 ... n pad electrode 30 ... SiO 2
31 ... Insulating film

Claims (7)

窒化物半導体基板上に積層された窒化物半導体を有する窒化物半導体素子の製造方法であって、
窒化物半導体と異なる異種基板上に、第1の窒化物半導体をラテラル成長させ、その上に第2の窒化物半導体を10μm以上400μm以下の厚さで成長させる第1の結晶成長工程と、
前記異種基板を除去して、前記窒化物半導体を、反りを有する窒化物半導体基板とする基板除去工程と、
前記窒化物半導体基板の上に、第3の窒化物半導体を10μm〜800μmの厚さで成長させる第2の結晶成長工程と、
前記第1の結晶成長工程で成長させた窒化物半導体及び前記第2の結晶成長工程で成長させた窒化物半導体を有する状態で、前記窒化物半導体基板の異種基板が除去された側を研磨して、前記ラテラル成長した窒化物半導体結晶の少なくとも一部を除去して、窒化物半導体基板の膜厚を小さくした窒化物半導体基板とする基板薄膜化工程と、
を具備することを特徴とする窒化物半導体素子の製造方法。
A method of manufacturing a nitride semiconductor device having a nitride semiconductor stacked on a nitride semiconductor substrate,
The nitride semiconductor different foreign substrate, the first nitride semiconductor is lateral growth, a first crystal growth step Ru second nitride semiconductor is grown with a thickness of 400μm or more 10μm thereon,
Removing the dissimilar substrate to make the nitride semiconductor a warped nitride semiconductor substrate; and
A second crystal growth step of growing a third nitride semiconductor on the nitride semiconductor substrate at a thickness of 10 μm to 800 μm ;
In the state having the nitride semiconductor grown in the first crystal growth step and the nitride semiconductor grown in the second crystal growth step, the side of the nitride semiconductor substrate from which the dissimilar substrate is removed is polished. Removing the laterally grown nitride semiconductor crystal, and reducing the thickness of the nitride semiconductor substrate to reduce the thickness of the nitride semiconductor substrate;
A method for producing a nitride semiconductor device comprising:
前記基板薄膜化工程において、研磨された窒化物半導体基板が反りを有する請求項1記載の窒化物半導体素子の製造方法。   The method for manufacturing a nitride semiconductor device according to claim 1, wherein in the substrate thinning step, the polished nitride semiconductor substrate has a warp. 前記基板除去工程において、前記異種基板を除去した側から前記第2の窒化物半導体の一部までを少なくとも除去する第1の基板研磨工程を具備する請求項1又は2記載の窒化物半導体素子の製造方法。 3. The nitride semiconductor device according to claim 1, further comprising a first substrate polishing step of removing at least a part of the second nitride semiconductor from a side where the different substrate is removed in the substrate removing step. Production method. 前記基板研磨工程後に、窒化物半導体素子を有する窒化物半導体基板の研磨面側に、前記窒化物半導体基板を劈開する劈開工程を具備する請求項1乃至3のいずれか1項に記載の窒化物半導体素子の製造方法。   The nitride according to any one of claims 1 to 3, further comprising a cleavage step of cleaving the nitride semiconductor substrate on a polishing surface side of the nitride semiconductor substrate having a nitride semiconductor element after the substrate polishing step. A method for manufacturing a semiconductor device. 前記窒化物半導体素子がレーザ素子であり、該レーザ素子が前記劈開工程の劈開による共振面を有する請求項4記載の窒化物半導体素子の製造方法。   The method for manufacturing a nitride semiconductor device according to claim 4, wherein the nitride semiconductor device is a laser device, and the laser device has a resonance surface formed by cleavage in the cleavage step. 前記基板研磨工程後に、窒化物半導体素子を有する窒化物半導体基板の研磨面側に、電極を形成する工程を具備する請求項1乃至5のいずれか1項に記載の窒化物半導体素子の製造方法。   6. The method for manufacturing a nitride semiconductor device according to claim 1, further comprising a step of forming an electrode on a polishing surface side of a nitride semiconductor substrate having a nitride semiconductor device after the substrate polishing step. . 前記第1の結晶成長工程において、GaNからなる第1の層に凹凸を形成して、該第1の層上に窒化物半導体を成長させる請求項1乃至6のいずれか1項に記載の窒化物半導体素子の製造方法。   The nitriding according to any one of claims 1 to 6, wherein in the first crystal growth step, irregularities are formed in the first layer made of GaN, and a nitride semiconductor is grown on the first layer. Method for manufacturing a semiconductor device.
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