JP4357916B2 - Power protection circuit - Google Patents

Description

  The present invention relates to a power protection circuit for electrostatic countermeasures in a semiconductor integrated circuit, and more particularly to a power protection circuit that prevents an abnormal increase in voltage at a power input terminal due to ESD (electrostatic discharge) or the like.

  In recent years, with the progress of miniaturization technology in a semiconductor integrated circuit, a decrease in breakdown voltage of an IC has become a problem. In particular, in the case of an IC using a MOS transistor, in order to achieve miniaturization, the thickness of the insulating oxide film in the MOS transistor has to be reduced, and this tends to lower the breakdown voltage of the MOS transistor. It was. For this reason, when the IC is not operating, a problem may occur in the IC due to a voltage increase at the power input terminal due to ESD or the like. Such a phenomenon becomes more prominent as IC miniaturization progresses.

Therefore, conventionally, a circuit configuration as shown in FIG. 10 has been generally used as a power protection circuit against ESD.
In the power supply protection circuit 100 of FIG. 10, the rise of the power supply voltage VCC2 due to ESD is mitigated by using the PMOS transistor 101 to flow current to another power supply system, for example, the power supply voltage VCC1. During normal operation, the gate of the PMOS transistor 101 is connected to the power supply voltage VCC1 on the high voltage side. Since the PMOS transistor 101 is off, the power supply voltage VCC2 is supplied from the power supply input terminal 102 to which the power supply voltage VCC1 is supplied. Current does not flow through the power input terminal 103. When the power supply voltage VCC1 and VCC2 are not supplied, and the voltage at the power supply input terminal 103 rises due to ESD, the PMOS transistor 101 is turned on and a current flows to the power supply input terminal 102.

In the case of the power supply protection circuit 100 as shown in FIG. 10, there is a problem that a current constantly flows from the power supply input terminal 103 to the power supply input terminal 102 when only the power supply voltage VCC2 is supplied in a normal state. The circuit of FIG. 11 has been considered to prevent such a current (see, for example, Patent Document 1).
The power supply protection circuit 110 as shown in FIG. 11 prevents current from flowing to other power supply systems regardless of whether or not the power supply voltages VCC1 and VCC2 are supplied during normal operation.

  For example, when only the power supply voltage VCC1 is supplied, the PMOS transistor 111 is turned on, but the diode 112 causes a current to flow from the power supply input terminal 113 supplied with the power supply voltage VCC1 to the power supply input terminal 114 supplied with the power supply voltage VCC2. Prevent it from flowing. When only the power supply voltage VCC2 is supplied, the power supply voltage VCC2 is applied to the gate of the PMOS transistor 111, so that the PMOS transistor 111 is turned off and current flows from the power supply input terminal 114 to the power supply input terminal 113. To prevent.

Further, when the power supply voltage VCC2 rises due to ESD, the PMOS transistor 111 is turned off by the rise of the gate voltage of the PMOS transistor 111. By delaying the turn-off time, a current flows from the power input terminal 114 to the power input terminal 113 via the PMOS transistor 111 and the diode 112, and the rise of the power supply voltage VCC2 is mitigated.
JP 2000-243842 A

  However, in the case of FIG. 11, when the power supply voltage is supplied only to the power input terminal 113 during the normal operation, the PMOS transistor 111 is turned on because the power supply voltage is not supplied to the power input terminal 114. Therefore, the diode 112 is necessary to prevent a current from flowing from the power input terminal 113 to the power input terminal 114. The rise in the power supply voltage VCC2 due to ESD is mitigated by passing a current to the power supply voltage VCC1, but there is a problem that a smooth current path is lost due to the diode 112 when the power supply voltage VCC1 due to ESD rises. .

  The present invention has been made in order to solve the above-described problem. With a simple circuit configuration, the power supply is caused to flow from a power supply input terminal whose voltage has been increased by ESD or the like to another power supply input terminal. The voltage rise at the input terminals can be suppressed, and an abnormal voltage rise at each power supply input terminal by flowing current between each power supply input terminal when surge voltage such as ESD is applied to the power supply input terminal An object of the present invention is to obtain a power protection circuit that can suppress each of the above.

A power protection circuit according to the present invention is a power protection circuit that protects a circuit having a plurality of power input terminals from an abnormal voltage such as ESD applied to the power input terminals.
A first MOS transistor connected between corresponding power input terminals;
The voltage of each power input terminal to which the first MOS transistor is connected is monitored, the voltage applied to one power input terminal is output to the substrate gate of the corresponding first MOS transistor, and the power The voltage applied to the input terminal is delayed for a predetermined time and output to the gate of the first MOS transistor. When the voltage is applied to the power input terminal, the first MOS transistor is turned on for a predetermined period. A power supply voltage monitor circuit for passing a current from the power supply input terminal to the other power supply input terminal ;
With
The power supply voltage monitor circuit is
A delay circuit that delays the input voltage for the predetermined time and outputs the delayed voltage to the gate of the first MOS transistor;
It operates according to the voltage of a predetermined first power supply input terminal, and when turned on, a second gate for connecting the substrate gate of the first MOS transistor and the input terminal of the delay circuit to the predetermined second power supply input terminal, respectively. A MOS transistor;
A third MOS transistor that, when turned on, connects the substrate gate of the first MOS transistor and the input terminal of the delay circuit to the first power input terminal;
A fourth MOS transistor which operates according to the voltage of the first power input terminal and turns on the third MOS transistor when turned on;
It operates in accordance with the voltage of the first power input terminal, and when turned on, applies the voltage of the second power input terminal to the gate of the third MOS transistor, and forms a complementary transistor with the fourth MOS transistor. 5 MOS transistors,
With
The third MOS transistor is configured such that the voltage of the second power input terminal is input to the gate from the fifth MOS transistor which is turned on when the fourth MOS transistor is turned off .

  Specifically, the power supply voltage monitor circuit changes the gate voltage of the corresponding first MOS transistor so that the power supply input monitor circuit is turned off with a delay of several nsec to several hundred nsec from the voltage rise of the power supply input terminal.

Specifically, the delay circuit includes:
A resistor connected between an input terminal and an output terminal of the delay circuit;
A capacitor connected between the output terminal of the delay circuit and the ground voltage;
I was prepared to.

  Further, the first MOS transistor and the power supply voltage monitor circuit are provided correspondingly between different power supply input terminals.

  In this case, (N-1) first MOS transistors and power supply voltage monitor circuits are provided for N power input terminals which are integers of 2 or more, respectively.

  Further, the N first MOS transistors and the power supply voltage monitor circuit may be provided for N power input terminals which are integers of 2 or more, respectively.

  According to the power protection circuit of the present invention, when one of the corresponding power input terminals rises due to ESD or the like, a current flows from the power input terminal whose voltage has risen to another power input terminal for a predetermined period. The increase in voltage at the power input terminal can be suppressed, and the occurrence of malfunctions in the internal circuit can be prevented. In addition, in an IC or the like having a large number of power supply input terminals, it is possible to suppress a voltage increase at each power supply input terminal due to the application of an abnormally high voltage, and to compensate for a decrease in the breakdown voltage of the IC due to miniaturization. Therefore, it is possible to prevent the occurrence of a malfunction of the IC due to the above, so that the reliability can be improved.

Next, the present invention will be described in detail based on the embodiments shown in the drawings.
First embodiment.
FIG. 1 is a diagram showing a configuration example of a power supply protection circuit according to the first embodiment of the present invention.
In FIG. 1, a power supply protection circuit 1 includes a power supply voltage monitor that monitors voltages at a first power supply input terminal T1 to which a first power supply voltage VCC1 is supplied and a second power supply input terminal T2 to which a second power supply voltage VCC2 is supplied. A circuit 2 and a PMOS transistor P1 are provided. The PMOS transistor P1 forms a first MOS transistor. The power supply voltage monitor circuit 2 supplies a voltage to the gate G and the substrate gate (also referred to as a back gate) B of the PMOS transistor P1 in accordance with the voltages of the first power supply input terminal T1 and the second power supply input terminal T2.

The normal operation of the power supply voltage monitor circuit 2 in FIG. 1 will be described with reference to FIGS. 2 to 4, B indicates the substrate gate of the PMOS transistor P1, and G indicates the gate of the PMOS transistor P1.
FIG. 2 shows a case where the first power supply voltage VCC1 is supplied to the first power supply input terminal T1 and the second power supply voltage VCC2 is not supplied to the second power supply input terminal T2. In the case of FIG. 2, the power supply voltage monitor circuit 2 supplies the first power supply voltage VCC1 to the gate and the substrate gate of the PMOS transistor P1, respectively.
FIG. 3 shows a case where the second power supply voltage VCC2 is supplied to the second power supply input terminal T2 and the first power supply voltage VCC1 is not supplied to the first power supply input terminal T1. In the case of FIG. 3, the power supply voltage monitor circuit 2 supplies the second power supply voltage VCC2 to the gate and the substrate gate of the PMOS transistor P1, respectively.

FIG. 4 shows a case where the first power supply voltage VCC1 is supplied to the first power supply input terminal T1, and the second power supply voltage VCC2 is supplied to the second power supply input terminal T2. In the case of FIG. 4, the power supply voltage monitor circuit 2 supplies the first power supply voltage VCC1 to the gate and substrate gate of the PMOS transistor P1, respectively.
2 and 4, the power supply voltage monitor circuit 2 delays the rise of the gate voltage Vg of the PMOS transistor P1 from several nsec to several hundreds of nsec from the rise of the first power supply voltage VCC1. Similarly, in FIGS. 3 and 4, the power supply voltage monitor circuit 2 delays the rise of the gate voltage Vg of the PMOS transistor P1 from several nsec to several hundreds nsec from the rise of the second power supply voltage VCC2.

  When the gate voltage Vg of the PMOS transistor P1 is smaller than the first power supply voltage VCC1 or the second power supply voltage VCC2, the PMOS transistor P1 is not completely turned off. However, as can be seen from FIG. 2 to FIG. 4, the rise times of the first power supply voltage VCC1 and the second power supply voltage VCC2 are normally sufficiently slower than the delay time, and therefore, depending on whether the power supply is turned on or off during normal operation. There is almost no current flowing from the first power input terminal T1 to the second power input terminal T2 or from the second power input terminal T2 to the first power input terminal T1.

  On the other hand, since the voltage rise due to ESD is considered to be several hundred nsec or less, when the voltage at the first power input terminal T1 rises due to ESD, the power supply voltage monitor circuit 2 turns on the PMOS transistor P1 as shown in FIG. Thus, a current can be passed to the second power input terminal T2 to limit the voltage rise at the first power input terminal T1. Similarly, when the voltage at the second power supply input terminal T2 rises due to ESD, the power supply voltage monitor circuit 2 turns on the PMOS transistor P1 to flow current to the first power supply input terminal T1, as shown in FIG. The voltage increase at the second power input terminal T2 can be limited. In FIGS. 5 and 6, B represents the substrate gate of the PMOS transistor P1, and G represents the gate of the PMOS transistor P1.

Next, FIG. 7 is a diagram showing a circuit example of the power supply voltage monitor circuit 2 of FIG.
In FIG. 7, the power supply voltage monitor circuit 2 includes PMOS transistors P2 to P4, an NMOS transistor N1, and a delay circuit 11. The PMOS transistor P2 serves as a second MOS transistor, the PMOS transistor P3 serves as a third MOS transistor, the PMOS transistor P4 serves as a fifth MOS transistor, and the NMOS transistor N1 serves as a fourth MOS transistor.

  A PMOS transistor P4 and an NMOS transistor N1 are connected in series between the second power input terminal T2 and the ground voltage, and the gates of the PMOS transistor P4 and the NMOS transistor N1 are connected to the first power input terminal T1, respectively. Has been. In the PMOS transistor P4, the substrate gate is connected to the source, and in the NMOS transistor N1, the substrate gate is connected to the source.

  A PMOS transistor P3 and a PMOS transistor P2 are connected in series between the first power input terminal T1 and the second power input terminal T2, and the gate of the PMOS transistor P2 is connected to the first power input terminal T1 and the PMOS transistor. The gate of P3 is connected to the connection between the PMOS transistor P4 and the NMOS transistor N1. The substrate gates of the PMOS transistors P1, P2, and P3 are connected to each other, and the connection is connected to the connection between the PMOS transistor P2 and the PMOS transistor P3 and to the input terminal of the delay circuit 11. Furthermore, the output terminal of the delay circuit 11 is connected to the gate of the PMOS transistor P1.

  In such a configuration, when the first power supply voltage VCC1 and the second power supply voltage VCC2 are not supplied and the voltage of the first power supply input terminal T1 rises due to ESD, the PMOS transistors P2 and P4 are turned off, respectively. The NMOS transistor N1 is turned on, and the gate of the PMOS transistor P3 is connected to the ground voltage via the NMOS transistor N1. Therefore, the PMOS transistor P3 is turned on, and the voltage of the first power input terminal T1 is applied to the substrate gate of the PMOS transistor P1 and the input terminal of the delay circuit 11 via the PMOS transistor P3. The voltage of the first power input terminal T1 input to the input terminal of the delay circuit 11 is delayed by the delay circuit 11 and applied to the gate of the PMOS transistor P1.

  Next, in a state where the first power supply voltage VCC1 and the second power supply voltage VCC2 are not supplied, when the voltage of the second power input terminal T2 rises due to ESD, the PMOS transistor P4 is turned on and the NMOS transistor N1 is turned off. The voltage of the second power input terminal T2 is applied to the gate of the PMOS transistor P3, and the PMOS transistor P3 is turned off. Since the first power supply voltage VCC1 is not supplied to the first power supply input terminal T1, the PMOS transistor P2 is turned on, and the voltage of the second power supply input terminal T2 passes through the PMOS transistor P2 and the substrate gate of the PMOS transistor P1. Each is applied to the input terminal of the delay circuit 11. The voltage of the second power input terminal T2 input to the input terminal of the delay circuit 11 is delayed by the delay circuit 11 and applied to the gate of the PMOS transistor P1.

  In the normal operation, when the first power supply voltage VCC1 is supplied to the first power supply input terminal T1 and the second power supply voltage VCC2 is supplied to the second power supply input terminal T2, the first power supply voltage VCC1 and the second power supply voltage are supplied. Even when VCC2 is the same voltage or when the first power supply voltage VCC1 is larger than the second power supply voltage VCC2, the PMOS transistors P2 and P4 are turned off and the NMOS transistor N1 is turned on. For this reason, the PMOS transistor P3 is turned on, and the first power supply voltage VCC1 is applied to the substrate gate of the PMOS transistor P1 and the input terminal of the delay circuit 11 via the PMOS transistor P3. The voltage of the first power input terminal T1 input to the input terminal of the delay circuit 11 is delayed by the delay circuit 11 and applied to the gate of the PMOS transistor P1, and the PMOS transistor P1 is always turned off.

  Further, the delay circuit 11 for delaying the voltage supply to the gate of the PMOS transistor P1 can be realized by a simple circuit as shown in FIG. In FIG. 8, the delay circuit 11 includes a resistor R1 and a capacitor C1. The resistor R1 is connected between the connection portion of the PMOS transistors P2 and P3 and the gate of the PMOS transistor P1, and the capacitor C1 is connected between the connection portion of the gate of the PMOS transistor P1, the resistor R1 and the ground voltage. Has been. Further, the PMOS transistor P1 needs to flow a large current, so that a transistor with a large transistor width is required. However, the power supply voltage monitor circuit 2 does not need to flow a large current, and thus has a simple circuit configuration and a small size. Realization in the area becomes possible.

  On the other hand, even if the voltage of any of the plurality of power supply input terminals rises due to ESD, the voltage rise of the power supply input terminal due to ESD can be suppressed by flowing current to the other power supply input terminals. Therefore, by providing a plurality of power protection circuits 1 between the power input terminals as shown in FIG. 9, a plurality of current paths can be secured, and a smoother current path for ESD can be provided. FIG. 9 shows an example in which four power input terminals T1 to T4 are provided, but N or (N−1) for N (an integer of N> 1) power input terminals. One power protection circuit 1 is provided. FIG. 9 shows an example in which three power protection circuits 1 are provided. However, when four power protection circuits 1 are provided, the power protection circuit 1 is also provided between the power input terminals T1 and T4. Make it.

  As described above, when a voltage is applied to one of the first power input terminal T1 and the second power input terminal T2, the power protection circuit according to the first embodiment uses the voltage of the PMOS transistor P1. In addition to being applied to the substrate gate, it is delayed by the delay circuit 11 and applied to the gate of the PMOS transistor P1 connected between the first power input terminal T1 and the second power input terminal T2. From this, when the voltage of either the first power input terminal T1 or the second power input terminal T2 rises due to ESD or the like, a current flows from the power input terminal whose voltage has risen to another power input terminal for a predetermined period. It is possible to suppress an increase in voltage at the power input terminal, and to prevent occurrence of a malfunction in the internal circuit. In addition, in an IC or the like having a large number of power supply input terminals, it is possible to suppress a voltage increase at each power supply input terminal due to the application of an abnormally high voltage, and to compensate for a decrease in the breakdown voltage of the IC due to miniaturization. Therefore, it is possible to prevent the occurrence of a malfunction of the IC due to the above, so that the reliability can be improved.

It is the figure which showed the structural example of the power supply protection circuit in the 1st Embodiment of this invention. FIG. 2 is a diagram showing an example of normal operation in the power supply voltage monitor circuit 2 of FIG. FIG. 7 is a diagram showing another example of normal operation in the power supply voltage monitor circuit 2 of FIG. 1. FIG. 7 is a diagram showing another example of normal operation in the power supply voltage monitor circuit 2 of FIG. 1. It is the figure which showed the operation example when ESD is added to the 1st power supply input terminal T1 in the power supply voltage monitor circuit 2 of FIG. It is the figure which showed the operation example when ESD is added to 2nd power supply input terminal T2 in the power supply voltage monitor circuit 2 of FIG. It is the figure which showed the circuit example of the power supply voltage monitor circuit 2 of FIG. FIG. 8 is a diagram illustrating a circuit example of the delay circuit 11 in FIG. 7. It is the figure which showed the case where two or more power supply protection circuits 1 of FIG. 1 were used. It is the figure which showed the example of the conventional power supply protection circuit. It is the figure which showed the other example of the conventional power supply protection circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Power supply protection circuit 2 Power supply voltage monitor circuit 11 Delay circuit P1-P4 PMOS transistor N1 NMOS transistor T1 1st power supply input terminal T2 2nd power supply input terminal T3 3rd power supply input terminal T4 4th power supply input terminal R1 Resistance C1 Capacitor

Claims (6)

In a power protection circuit for protecting a circuit having a plurality of power input terminals from an abnormal voltage such as ESD applied to the power input terminals,
A first MOS transistor connected between corresponding power input terminals;
The voltage of each power input terminal to which the first MOS transistor is connected is monitored, the voltage applied to one power input terminal is output to the substrate gate of the corresponding first MOS transistor, and the power The voltage applied to the input terminal is delayed for a predetermined time and output to the gate of the first MOS transistor. When the voltage is applied to the power input terminal, the first MOS transistor is turned on for a predetermined period. A power supply voltage monitor circuit for passing a current from the power supply input terminal to the other power supply input terminal ;
With
The power supply voltage monitor circuit is
A delay circuit that delays the input voltage for the predetermined time and outputs the delayed voltage to the gate of the first MOS transistor;
It operates according to the voltage of a predetermined first power supply input terminal, and when turned on, a second gate for connecting the substrate gate of the first MOS transistor and the input terminal of the delay circuit to the predetermined second power supply input terminal, respectively. A MOS transistor;
A third MOS transistor that, when turned on, connects the substrate gate of the first MOS transistor and the input terminal of the delay circuit to the first power input terminal;
A fourth MOS transistor which operates according to the voltage of the first power input terminal and turns on the third MOS transistor when turned on;
It operates in accordance with the voltage of the first power input terminal, and when turned on, applies the voltage of the second power input terminal to the gate of the third MOS transistor, and forms a complementary transistor with the fourth MOS transistor. 5 MOS transistors,
With
In the third MOS transistor, the voltage of the second power input terminal is inputted to the gate from the fifth MOS transistor which is turned on when the fourth MOS transistor is turned off. .   2. The gate voltage of the corresponding first MOS transistor is changed so that the power supply voltage monitor circuit is turned off with a delay of several nsec to several hundred nsec from a rise in voltage of a power supply input terminal. Power protection circuit. The delay circuit is
A resistor connected between an input terminal and an output terminal of the delay circuit;
A capacitor connected between the output terminal of the delay circuit and the ground voltage;
Power supply protection circuit according to claim 1, wherein further comprising a. Said first MOS transistor and the power supply voltage monitoring circuit, the power supply protection circuit according to claim 1, 2 or 3, wherein the provided corresponding to the different power supply input terminal. 5. The power supply protection circuit according to claim 4 , further comprising (N-1) first MOS transistors and a power supply voltage monitor circuit for N power supply input terminals which are integers of 2 or more . 5. The power supply protection circuit according to claim 4 , further comprising N first MOS transistors and a power supply voltage monitor circuit for N power supply input terminals which are integers of 2 or more.

Images