JP4358710B2 - Image resolution converter - Google Patents

Description

  The present invention relates to an image resolution conversion apparatus, and more particularly to an image resolution conversion apparatus suitable for converting a resolution from a pixel value of an original image at an arbitrary magnification and generating a pixel value at a newly set pixel position.

As a conventional example, Japanese Patent Laid-Open No. 2001-189850 “Resolution Conversion Device and Resolution Conversion Method” proposes a resolution conversion device composed of a line memory for storing video signals, a coefficient generator for generating interpolation coefficients, and the like. Yes. In this proposal, interpolation processing is performed by obtaining an interpolation coefficient from a look-up table based on the reduction ratio / enlargement ratio and the horizontal and vertical positions of newly set pixels with respect to the pixel position of the original image.
JP 2001-189850 A (paragraphs [0038] to [0042], FIG. 4)

  In Japanese Patent Application Laid-Open No. 2001-189850, pixel values of newly set pixels are interpolated from pixel values of the pixel group of the original image, but there is no description regarding selection of the pixel group of the original image.

  The present invention has been made to solve the above-described problems, and image resolution that enables selection of a pixel group of an original image related to generation of a new pixel after resolution conversion while suppressing a circuit scale. An object is to provide a conversion device.

  The configuration, corresponding examples, operations and effects of the image transmission apparatus according to the inventions of claims 1 to 4 will be described below.

(Claim 1)
(Constitution)
An image resolution conversion apparatus according to claim 1 is an image resolution conversion apparatus for converting an original image composed of a plurality of pixels into an image having a resolution multiplied by a set resolution conversion magnification. A region in which a pixel is newly provided based on a pixel value storage unit in which the pixel value of a pixel is stored, and an integer value serving as a denominator and an integer value serving as a numerator when the set resolution conversion magnification is expressed as an integer ratio And an output control signal for outputting the pixel value of the original pixel group corresponding to the region from the pixel value storage unit according to the determination result. a pixel value reading control unit which, in each address of the plurality of addresses corresponding to the integer to be the molecule when expressed the resolution conversion magnification by an integer ratio, Kakue straightforward to multiply the interpolation coefficients of the pixel groups Includes an interpolation coefficient storage unit stored for each pixel group, an interpolation coefficient reading control unit for generating a signal designating the address in synchronization with the output control signal, and the interpolation coefficient storage by the address signal. A pixel value calculation unit that calculates a pixel value of the new pixel based on the interpolation coefficient group output from the unit and the value of the pixel group output from the pixel value storage unit, and the output control Based on the pixel value of the original pixel group read from the pixel value storage unit according to the signal and the internal division ratio from adjacent pixels of the original image at the new pixel position specified by the region determination unit. have, an interpolation calculator for interpolation calculation the pixel values of the new pixels.

(Example of corresponding invention)
The embodiment related to the present invention corresponds to the first embodiment.

(Function)
Based on the set resolution conversion magnification (setting magnification), the region determination unit sequentially determines a region (new pixel setting region) in which a pixel is newly provided according to the raster arrangement order of the new pixel, and according to the determination result, With the output control signal generated by the pixel value reading control unit, the pixel value of the pixel group corresponding to the new pixel setting area is output from the pixel value storage unit storing the pixel value of each pixel of the original image, From the pixel value of the pixel group, the pixel value of the new pixel corresponding to the set magnification is interpolated by the interpolation operation unit.
When the resolution conversion magnification is expressed as an integer ratio, resolution conversion is performed from the number of pixels corresponding to the integer serving as the denominator (first pixel number) to the number of pixels corresponding to the integer serving as the numerator (second This corresponds to an operation for generating the number of pixels. This operation is repeated every time the second number of pixels is generated. For this reason, interpolation coefficient groups for generating new pixels are prepared in advance corresponding to the number of second pixels, and repeatedly read out and used in a cycle of the second number of pixels. Here, the interpolation coefficient group that is stored for each pixel group at each address of the plurality of addresses corresponding to the second number of pixels in the interpolation coefficient storage unit is multiplied by each pixel value of the pixel group, and the interpolation coefficient is read. The control unit outputs the pixel according to the address designation signal generated in synchronization with the output control signal. Based on the output interpolation coefficient group and the pixel group value output from the pixel value storage unit, the pixel of the new pixel The value is calculated by the pixel value calculation unit.

(effect)
The new pixel setting area is sequentially determined according to the raster arrangement order of the new pixels, and the pixel value of the pixel group is output and the value of the new pixel is calculated according to the determination result. There is no need for replacement, and the circuit can be made small.
When the resolution conversion magnification is expressed as an integer ratio, the address is repeatedly specified in a cycle corresponding to the integer that becomes the numerator, and the interpolation coefficient multiplied by the pixel group is read from the interpolation coefficient storage part, so the position of the new pixel The calculation for individually obtaining the pixel values is not necessary, and the pixel value of the new pixel can be obtained with a relatively small circuit.

(Claim 2)
(Constitution)
2. The image resolution conversion apparatus according to claim 1, wherein the region determination unit includes a first arithmetic circuit that determines the region based on a resolution conversion magnification in the line direction of the image, and resolution conversion of a non-line component that intersects the line direction. A second arithmetic circuit that determines the region based on a magnification.

(Example of corresponding invention)
The embodiment related to the present invention corresponds to the first embodiment.

(Function)
In the new pixel setting area, the line component of the new pixel setting region is determined by the first arithmetic circuit based on the resolution conversion magnification in the line direction of the image, and the non-line component intersecting the line direction is determined by the second arithmetic circuit. It is determined based on the resolution conversion magnification in the line direction.

(effect)
New pixel setting areas can be sequentially determined in a raster arrangement in two directions, a line direction and a non-line direction.

(Claim 3 )
(Constitution)
The interpolation calculation unit in the image resolution conversion apparatus according to claim 1 includes an interpolation coefficient storage unit that stores an interpolation coefficient corresponding to the density characteristic of the original image, and an image density determination unit that determines the density characteristic of the original image. And a coefficient selection unit that selects the interpolation coefficient in accordance with the determination result.

(Example of corresponding invention)
The embodiment related to the present invention corresponds to the first embodiment.

(Function)
The interpolation coefficient corresponding to the density characteristic of the original image stored in the interpolation coefficient storage unit is selected by the coefficient selection unit according to the density characteristic of the original image determined by the image density determination unit.

(effect)
Since the value of the interpolation coefficient corresponding to the image density can be selected, the image after resolution conversion can have a high image quality.

  According to the present invention, it is possible to select a pixel group of an original image related to generation of a new pixel after resolution conversion while suppressing a circuit scale.

  Embodiments of an image resolution conversion apparatus according to the present invention will be described below with reference to the drawings.

  FIG. 1 is a diagram showing a schematic configuration of an image resolution conversion apparatus according to a first embodiment of the present invention. In the following embodiments, the above-described line direction is a horizontal direction, and the non-line direction is a vertical direction.

  The image resolution conversion apparatus includes a pixel value storage unit 101, a new pixel setting region determination unit (hereinafter simply referred to as a region determination unit) 102, a pixel value reading control unit 103, an interpolation calculation unit 104, and a pixel value writing control. Unit 105.

  An original image scan pixel value raster-scanned by an image sensor such as a CCD is written into the pixel value storage unit 101 under a write control signal S 1 from the pixel value write control unit 105.

  On the other hand, the region determination unit 102 supplies the pixel value reading control unit 103 with a region control signal S2 for determining a new pixel setting region according to the raster arrangement order of the new pixels based on the enlargement / reduction magnification data supplied from the outside. To do.

  The pixel value reading control unit 103 generates a reading control signal S3 as an output control signal from the supplied region control signal S2, and supplies this reading control signal S3 to the pixel value storage unit 101. Thereby, the original image pixel value of the new pixel setting area is read from the pixel value storage unit 101 and supplied to the interpolation calculation unit 104.

  The interpolation calculation unit 104 supports the enlargement / reduction ratio data by multiplying the interpolation coefficient held in the storage unit such as the internal SRAM by the original image pixel value supplied from the pixel value storage unit 101. The resolution-converted new pixel value is output.

Hereinafter, each part will be described in detail.
FIG. 2 is a diagram showing a configuration example of the pixel value storage unit 101. Here, a case will be described in which there are 16 pixel groups of the original image surrounding an area for setting one new pixel.

  In FIG. 2, a pixel value storage unit 101 includes a field memory 201 that stores the pixel values of the original image raster-scanned by the image sensor, and a plurality (four in the figure) that store the pixel values of the original image in line units. ) Line memory 202 and a plurality of (in the figure, 12) registers 203 that hold the pixel values of one pixel of the original image.

  An original image scan pixel value raster-scanned by an image pickup device such as a CCD is associated with address numbers in the order of raster scan by a write control signal S 1 supplied from the pixel value write control unit 105 and stored in the field memory 201. . Image data for one screen is stored in the field memory. This data storage is performed, for example, in synchronization with the timing of performing the raster scan.

  Here, the reading control signal S 3 from the pixel value reading control unit 103 is read into the line memory 202 and the line memory data shift control signal S 31 for shifting the data stored between the field memory 201 and the line memory 202 group. A line memory read control signal S32 for giving an address to read data at a desired position on the line, and a register data shift control signal S33 for shifting data stored between the registers 203, It is supplied to the corresponding field memory 201, line memory 202, and register 203.

Next, the operation of FIG. 2 will be described.
For example, when a new pixel is set from a 4 × 4 16-point original image pixel group, one line of one screen of the field memory 201 is read out by the line memory data shift control signal S31. The data is stored in the line memory 202 at the lowest level in the figure of the memory 202 group. The next line of the field memory 201 is sequentially read in accordance with the shift control timing, and further stored in the line memory 202 in the upper stage of the figure in the line memory 202 group and sequentially shifted. As a result, the pixel values for four horizontal lines of interest are stored in each line memory 202 of the line memory 202 group. The pixel values on the horizontal line stored in each of the four line memories 202 are output, for example, from the four line memories 202 by the address specified by the line memory read control signal S32, for example, the rightmost pixel value. It is stored in each register 203 in the first column of the register 203 group. As a result, four pixels are stored in each register 203 of the register 203 group in the first column and are arranged in the column direction.

  Then, the pixel values of the horizontal lines of the four line memories 202 are sequentially read out from each line memory 202 at the timing of the shift control signal S31 in units of pixels, and the second value of the register 203 group is read at each timing of the register shift control signal S33. The data is sequentially shifted to the respective registers 203 in the column, the third column, and the fourth column.

  As described above, the pixel values D11, D12, D13, D14, D21, D22, D23, D24, D31, D32, D33, D34, D41 of the 16-point original image pixel group arranged 4 × 4 surrounding the new pixel setting area. , D42, D43, and D44 can be acquired simultaneously.

  FIG. 3 shows the configuration of a 16 × original image pixel group arranged in a 4 × 4 array surrounding the new pixel setting area. A new pixel is created at some position in an area surrounded by four pixels (D22, D23, D32, D33) in the central portion. In other words, the surrounding 16 original image pixels are determined so that the position of the newly created pixel is located somewhere in the area surrounded by the four original pixels, and one pixel value is determined from the pixel values of the 16 original pixels. The pixel value of the new pixel is obtained by interpolation calculation.

  Then, for the first 4 × 4 array of 16-point pixels (pixels surrounded by a dotted line) of the original image pixels (shown by ◯) shown in FIG. When the acquisition of the original pixel to be performed is completed, the area setting is performed on the next 4 × 4 array of 16-point pixels (the pixels in the area surrounded by the one-dot chain line) based on the area movement command signal (shown in FIG. 13). Will be moved.

FIG. 5 is a diagram for explaining a new pixel setting area.
First, with reference to FIG. 5, a basic concept for configuring the region determination unit 102 will be described. This figure shows an example of enlargement. The points indicated by squares (□) are pixels of the original image, and the points indicated by circles (◯) are pixels newly set by performing enlargement. To express.

  As shown in FIG. 5, the number of new pixels set in the new pixel setting area differs depending on the area. For example, four pixels at the position of BCEF are set in the area surrounded by the pixel group of “Lohahohe”, while one pixel at the position of G is set in the area surrounded by the pixel group of “Nihonchi”. Only. In this figure, only the nearest pixel group is shown among the pixel groups of the original image surrounding the area where the new pixel is set. That is, only a partial region of 16 pixels is shown.

  FIG. 6 shows an example of enlargement processing. For example, the process of multiplying the original image by 11/9 in the horizontal direction corresponds to the process of generating 11 pixels from 9 pixels of the original image. Nine sections on the upper straight line in FIG. 6 (excluding one on the right end) A to I mean nine pixels of the original image, and eleven sections on the lower straight line in FIG. A to k) means 11 new pixels to be newly generated. The number in the vicinity of the straight line of the upper original image in FIG. 6 represents the number of new pixels generated in one section between two pixels of the original image. For example, “2” new pixels a and b are generated between the pixels A and B. Also, the number (ratio) in the vicinity of the separation on the straight line of the new pixel on the lower side of FIG. 6 represents the new pixel relative to the length (line segment) of the one section on the straight line of the original image on the upper side of FIG. The internal dividing point (that is, the internal ratio of the interval) is shown. The leftmost break a on the straight line of the new pixel on the lower side of FIG. 6 corresponds to the first internal dividing point 0:11 of one section of the original image straight line on the upper side of FIG. The numbers (ratio) of the sequential divisions b to k are internal division ratios 9: 2, 7: 4, 5: 6, 3: 8 of one section of the original image straight line on the upper side of FIG. 1:10, 10: 1, 8: 3, 6: 5, 4: 7, 2: 9.

  These internal ratios are distance ratios that internally divide the interval between the original pixels indicated by the upper straight line, and the interpolation coefficient required in the present application is, for example, simple linear two-point interpolation. Considering that, since the internal division ratio of the new pixel b between the original pixels A and B is 9: 2, the interpolation coefficient multiplied by the original pixel A to obtain the interpolated pixel value of the new pixel b is 2/11, The interpolation coefficient multiplied by the pixel B is 9/11. Thus, the interpolation pixel value b of the new pixel b can be calculated as b = (2/11) · A + (9/11) · B. However, A and B show the pixel values of the original pixels A and B.

FIG. 7 shows an example of reduction processing. The process of multiplying the original image by 5/8 in the horizontal direction corresponds to a process of generating five pixels from eight pixels of the original image. Eight divisions (except one on the right end) A to H on the upper straight line in FIG. 7 mean eight pixels of the original image, and five divisions (right end on the lower straight line in FIG. 7). A to e means five new pixels to be newly generated. The number in the vicinity of the straight line of the upper original image in FIG. 7 represents the number of new pixels generated in one section between two pixels of the original image. Also, the numbers (ratio) in the vicinity of the separation on the straight line of the new pixel on the lower side of FIG. 7 are the numbers of the new pixels relative to the length (line segment) of the one section on the straight line of the original image on the upper side of FIG. The internal dividing point (that is, the internal ratio of the interval) is shown. The leftmost segment “a” on the lower straight line of the new pixel in FIG. 7 corresponds to the first internal dividing point 0: 5 of one section of the upper original image straight line in FIG. The numbers (ratio) of the sequential breaks b to e are the internal division ratios 3: 2, 1: 4, 4: 1, 2: 3 of the upper section of the original image line in FIG. 7 corresponding to each break. It has become.
The relationship between the internal ratio and the interpolation coefficient can be considered as in FIG.

  By the way, in the generation of new pixels on the lower straight line in FIG. 6, the internal ratios of the lengths of the respective sections on the upper straight line from which the interpolation coefficient is calculated are 9: 2, 7: 4. , 5: 6, 3: 8, 1:10, 10: 1, 8: 3, 6: 5, 4: 7, 2: 9 are divided into two in the middle, 9: 2, 7 : 4, 5: 6, 3: 8, 1:10, 10: 1, 8: 3, 6: 5, 4: 7, 2: 9 have symmetry that the left and right numbers are interchanged is doing.

  Similarly, in FIG. 7, in the generation of new pixels on the lower straight line in FIG. 7, the internal division ratio 3: 2 of the length of each section on the upper straight line from which the interpolation coefficient is calculated. , 1: 4, 4: 1, 2: 3, divided into two in the middle, 3: 2, 1: 4, 4: 1, 2: 3, the numbers on the left and right It has a switched symmetry.

  Therefore, the interpolation coefficient to be stored in the SRAMs 603 and 607 as the interpolation coefficient storage unit shown in FIG. When the magnification of enlargement or reduction is expressed in the form of an irreducible fraction, it is not necessary to store the interpolation coefficient by the number of the numerator of the fraction representing the magnification. If the above symmetry is used, only about half ( It is sufficient if it has a capacity capable of storing the interpolation coefficient of the quotient obtained by dividing the numerator value by 2 and adding 1). In other words, the internal division ratio, which is a base of the interpolation coefficient for each new pixel, required when enlarging or reducing the image is 9: 2, 7: 4, 5: 6 surrounded by a circle in the case of FIG. , 3: 8, 1:10, and only 5 types of interpolation coefficients based on 9: 2, 7: 4, 5: 6, 3: 8, 1:10 are stored in the SRAM. Just keep it. In the case of FIG. 7, there are only two methods of 3: 2, 1: 4 surrounded by ○, and therefore, only two types of interpolation coefficients based on 3: 2, 1: 4 may be stored in the SRAM. .

  When calculating the pixel values of the new pixels by 16-point interpolation, the pixel values of the new pixels are calculated while the pixels of the original image are held in the pixel value storage unit 101 shown in FIG. The pixel value of the new pixel can be calculated by multiplying the pixel value by a coefficient corresponding to each pixel (a coefficient corresponding to the distance of the new pixel with respect to the 16 original pixels) and adding them.

  FIG. 8 illustrates an example in which 16-point interpolation is performed using 16 original image pixels around a new pixel. New line pixels to be newly created are marked with ◎, the 16 original image pixels in the surrounding area are marked with ◯, and the 4 points in the horizontal direction of the 16 original image pixels in the surrounding area are connected to form one line segment. Are L1, L2, L3, and L4, and four columns K1, K2, K3, and K4 are formed by connecting four points in the vertical direction of 16 neighboring original image pixels.

  The four temporary new pixels P1 to P4 arranged in the vertical direction at the same horizontal position as the horizontal position of the new pixel ◎ on the line segments L1, L2, L3, and L4 are indicated by ●.

  For the horizontal line segment L1, the pixel values (A, B, C, D) of four-point original image pixels A, B, C, D (indicated by ◯) arranged one-dimensionally on the line segment L1 are used. ) To obtain one temporary new pixel P1 (corresponding to ● on the line segment L1) by interpolation, the distance between each of the four original pixels on the line segment L1 and P1 with respect to the temporary new pixel P1. Assuming that the interpolation coefficients that are the values are α1, α2, α3, α4 (the sum of these coefficients is 1), the interpolated pixel value P1 of the temporary new pixel P1 is P1 = α1 · A + α2 · B + α3 · C + α4 • D can be calculated. Similarly, for the horizontal line segments L2, L3, and L4, interpolated pixel values P2, P3, and P4 of temporary new pixels P2, P3, and P4 corresponding to ● on the line segments L2, L3, and L4 can be calculated. it can.

  Then, an interpolation coefficient which is a value relating to the distance between each of the new pixels P1, P2, P3, and P4 on the horizontal line segments arranged in the four vertical directions with respect to the position of the new pixel ◎ is β1, When β2, β3, β4 (the sum of these coefficients is 1), the interpolated pixel value Q of the new pixel ◎ can be calculated by Q = β1 · P1 + β2 · P2 + β3 · P3 + β4 · P4. However, P1, P2, P3, and P4 indicate pixel values of the pixels P1, P2, P3, and P4.

  In FIG. 8, four temporary new pixels P1 ′ to P4 ′ arranged in the horizontal direction at the same vertical position as the vertical position of the new pixel ◎ on the columns K1, K2, K3, and K4 are indicated by ●. Yes. Instead of the horizontal line segments L1, L2, L3, and L4, first, the pixel values of temporary new pixels P1 ′, P2 ′, P3 ′, and P4 ′ on the columns K1, K2, K3, and K4 are calculated, and then new The interpolation pixel value Q of the pixel ◎ may be calculated.

  By the way, for example, in the enlargement process of 11/9 times in FIG. 6, when new pixels a to k are sequentially created with reference to the original image pixels A to I, vertical and horizontal 16-point interpolation, and when viewed in one dimension, 4-point interpolation Considering, the section of the original image to be referred to shifts sequentially every time two or one new pixel is created for each section. As shown in FIG. 9, the second and third pixels of the surrounding four original pixels (indicated by ◯, which are the first pixel, the second pixel, the third pixel, and the fourth pixel from the left) It can be considered that the new pixels a to f (the new pixels g to k are omitted in view of the above-described symmetry of the pixel positions) are arranged therebetween.

  Here, within the central creation interval between the second pixel and the third pixel, the new pixel corresponding to the second pixel is an internal dividing point a of 0:11 (this is address 0 in the interpolation coefficient storage unit). The internal dividing points b, f, c, d, e, f of 9: 2, 7: 4, 5: 6, 3: 8, 1:10 from the left side in consideration of symmetry are stored in the interpolation coefficient storage unit. 1, 2, 3, 4 and 5. The interpolation coefficient storage unit corresponds to the SRAM of FIG.

  FIG. 10 represents the interpolation coefficient when considering the four-point interpolation of FIG. 9 as the interpolation coefficient for each pixel of the first, second, third, and fourth pixels as the original pixels. For example, when the interpolation pixel value of the new pixel b is calculated, the first coefficient δ1, the second coefficient δ2, and the third coefficient δ3 from the respective addresses 1 of the four first, second, third, and fourth SRAMs. , The fourth coefficient δ4 is read out, multiplied by the pixel values of the first, second, third and fourth pixels, which are the original pixels, and added to calculate the interpolated pixel value of the new pixel b. it can. Similarly, for example, when calculating the interpolation pixel value of the new pixel e, the first coefficient θ1, the second coefficient θ2, and the like from the respective addresses 4 of the four first, second, third, and fourth SRAMs. The third coefficient θ3 and the fourth coefficient θ4 are read out, multiplied by the pixel values of the first, second, third and fourth pixels, which are the original pixels, and added to obtain the interpolated pixel value of the new pixel e. Can be calculated.

  On the other hand, when the interpolated pixel value of the new pixel j shown in FIG. 6 is calculated, the first coefficient ε1 and the second coefficient ε2 from the respective addresses 2 of the four first, second, third and fourth SRAMs. , The third coefficient ε3 and the fourth coefficient ε4 are read out and rearranged in the reverse order, multiplied by the original pixel values of the first, second, third and fourth pixels, and added. The interpolated pixel value of pixel j can be calculated. Similarly, for example, when calculating the interpolated pixel value of the new pixel g, the first coefficient λ1, the second coefficient λ2, from the respective addresses 5 of the four first, second, third and fourth SRAMs, A new pixel is obtained by reading out the third coefficient λ3 and the fourth coefficient λ4 and rearranging them in the reverse order, multiplying them by the pixel values of the first, second, third and fourth pixels, which are the original pixels, and adding them. The interpolated pixel value of g can be calculated. The same applies to the vertical direction.

  Next, a case where a reduction process is performed instead of the above-described enlargement process will be described with reference to FIGS. Note that when the enlargement / reduction magnification is changed, the storage contents of the SRAM constituting the interpolation coefficient storage unit in the interpolation calculation unit (see FIG. 16) are rewritten. That is, the relationship between the address and the interpolation coefficient in FIG. 10 stored in the SRAM is rewritten as shown in FIG.

  For example, in the reduction processing of 5/8 times in FIG. 7, when new pixels a to e are sequentially created with reference to the original image pixels A to H, similarly, 16-point interpolation in the vertical and horizontal directions and 4-point interpolation when viewed in one dimension. Considering, the section of the original image to be referred to is sequentially shifted every time one or zero new pixels are created for each section (in the case of zero, it is not created). As shown in FIG. 11, four surrounding original pixels (indicated by the circles, these are the first pixel, the second pixel, the third pixel, and the fourth pixel from the left, as shown in FIG. ) In which the new pixels a to c (the new pixels d and e are omitted in view of the symmetry of the pixel positions described above) are arranged in the central creation section between the second pixel and the third pixel. Can be considered.

  Here, in the central creation interval between the second pixel and the third pixel, the new pixel corresponding to the second pixel is the internal dividing point a of 0: 5 (this is address 0 in the interpolation coefficient storage unit) and Then, the internal division points b and c of 3: 2 and 1: 4 from the right side in consideration of symmetry are set as addresses 1 and 2 in the interpolation coefficient storage unit. The interpolation coefficient storage unit corresponds to the SRAM of FIG.

  FIG. 12 shows the interpolation coefficient when the four-point interpolation of FIG. 11 is considered as the interpolation coefficient for each pixel of the first, second, third and fourth pixels which are the original pixels. For example, when the interpolated pixel value of the new pixel b is calculated, the first coefficient τ1, the second coefficient τ2, and the third coefficient τ3 from the respective addresses 1 of the four first, second, third, and fourth SRAMs. , The fourth coefficient τ4 is read out, multiplied by the pixel values of the first, second, third and fourth pixels, which are the original pixels, and added to calculate the interpolated pixel value of the new pixel b. it can. Similarly, when calculating the interpolation pixel value of the new pixel c, for example, the first coefficient ψ1, the second coefficient ψ2, from the respective addresses 2 of the four first, second, third, and fourth SRAMs. The third coefficient ψ3 and the fourth coefficient ψ4 are read out, multiplied by the original pixel values of the first, second, third and fourth pixels, and added to obtain the interpolated pixel value of the new pixel c. Can be calculated.

  On the other hand, when the interpolated pixel value of the new pixel e shown in FIG. 7 is calculated, the first coefficient τ1 and the second coefficient τ2 from each address 1 of the four first, second, third and fourth SRAMs. , The third coefficient τ3 and the fourth coefficient τ4 are read out and rearranged in the reverse order, multiplied by the pixel values of the first, second, third and fourth pixels, which are the original pixels, and added. The interpolated pixel value of the pixel e can be calculated. Similarly, when calculating the interpolation pixel value of the new pixel d, for example, the first coefficient ψ1, the second coefficient ψ2, from the respective addresses 2 of the four first, second, third, and fourth SRAMs. A new pixel is obtained by reading out the third coefficient ψ3 and the fourth coefficient ψ4 and rearranging them in the reverse order, multiplying them by the pixel values of the first, second, third and fourth pixels, which are the original pixels. The interpolation pixel value of d can be calculated. The same applies to the vertical direction.

  By the way, for example, the process of multiplying the original image by 11/9 in the horizontal direction corresponds to the process of generating 11 new pixels from 9 pixels of the original image, and from the original image, the difference of 2 pixels The pixel group is repeatedly read at a predetermined area position (specifically, the first area and the fifth area) a number of times corresponding to the above. The same applies to the vertical direction.

  Thus, in enlargement, it is necessary to repeatedly read the same pixel group depending on the region. Therefore, it is necessary to instruct to repeat reading in units of pixel groups in the horizontal direction and to repeat reading in units of lines in the vertical direction.

  In the reduction, there is a region where there are no newly set pixels. For example, the process of multiplying the original image by 5/8 in the horizontal direction is equivalent to the process of generating five new pixels from the eight pixels of the original image, and the original image is equivalent to three pixels of difference. There is no pixel to be newly set at the position of the area (specifically, the third area, the sixth area, and the eighth area). The same applies to the vertical direction.

  Thus, in the reduction, there is a region where there is no newly set pixel. For such a region, it is necessary to prevent the pixel value relating to the newly set pixel of the original image from being output to the subsequent circuit as a result. For example, specifically, (1) the pixel group itself is not output to the interpolation calculation unit 104, (2) the pixel group is output but the interpolation calculation unit 104 does not perform the interpolation calculation, and (3) the interpolation calculation unit 104 Interpolation calculation is performed on the pixel group, but control is performed such that the output is cut off at a later stage. Therefore, in order to perform such control, it is instructed that the pixel group is a pixel group in which there is no pixel to be newly set, in the pixel group unit in the horizontal direction and in the line unit in the vertical direction. There is a need to.

FIG. 13 is a configuration diagram of the region determination unit 102.
The area determination unit 102 shown in FIG. 13 is a block that generates an area control signal S2 that is the source of the above instruction. That is, an area control signal S2 indicating whether or not to move the new pixel setting area in each of the horizontal direction and the vertical direction is generated.

First, the background of the configuration of the area determination unit 102 will be described with reference to FIG.
The resolution conversion magnification is assumed to be M / N times (M and N are positive integers).
As described above, the process related to this conversion is to generate M new pixels from N pixels of the original image. Specifically, the process is sandwiched between N 11 pixels of the original image. When the N regions (regions sandwiched by the segments arranged on the line segment A in FIG. 14) are virtually subdivided into N × M pieces, the subdivision points corresponding to multiples of N (the line segment B in FIG. 14) The upper boundary) is the position where a new pixel is generated.

  The region determination unit 102 generates the region control signal S2 by determining in which region of the N regions of the original image the position where these new pixels are generated is generated.

  Here, the position where the new pixel is generated in the area is from the pixel position of the original image in front of the area (left side in the figure) to the pixel position of the original image behind the area (right side in the figure). The pixel position is represented by the distance (arrow in FIG. 14) from the pixel behind (on the right side in the figure) the area of the original image. Therefore, the position of the new pixel can be expressed by an integer from 1 to M.

  As shown in the figure, the position of the first new pixel is matched with the first pixel position of the original image. The position of this first new pixel is M from the above definition.

  Since the next new pixel is located at the rear (right side in the figure) by N, the position of this new pixel is (MN) from the above definition.

  Thereafter, the position of the next new pixel is obtained by subtracting N from the position of the new pixel. However, if the number is decreased a certain number of times, the pixel position becomes 0 or less. This is the state shown by the arrow (1) in FIG. 14, and the area of the original image exceeds the range for generating a new pixel. In such a case, if M is added, the state shown by the arrow (2) in FIG. 14 is obtained, and the pixel position in the next region is represented.

  Here, the fact that the pixel position amount is 0 or less represents a situation where the movement of the area is necessary, and adding M represents the pixel position in the next area.

  When N is larger than M, the pixel position may remain 0 or less even when the above-described region movement is performed. This means that no new pixel is set in the destination area. In this case, the region is further moved without obtaining the position of the next new pixel in this region.

Next, the configuration of the region determination unit 102 will be described in detail with reference to FIG.
The area determination unit 102 generally includes a first arithmetic circuit 301 that generates an area control signal S21 in the horizontal direction and a second arithmetic circuit 306 that generates an area control signal S22 in the vertical direction. Yes.

First, the first arithmetic circuit 301 will be described.
The first arithmetic circuit 301 operates with a horizontal effective period clock on the basis of the horizontal enlargement / reduction ratio, and issues a horizontal area movement command for instructing movement of the new pixel setting area in the horizontal direction as the area control signal S21. This block generates a signal S211 and a horizontal deletion area signal S212 indicating an area that does not require new pixel setting.

  The first arithmetic circuit 301 includes a comparator 302, a subtracter 303, a comparator 304, and an adder 305.

  The comparator 302 generates a subtraction non-permission signal and outputs it to the subsequent stage subtractor 303. When the parameter HC from the rear stage adder 305 is 0 or less, the subtraction non-permission signal is made active. Note that this subtraction non-permission signal is also output as a horizontal deletion region signal indicating whether or not the region does not require new pixel setting. The parameter HC is input to the subtractor 303 as it is.

  The subtractor 303 outputs the value obtained by subtracting the value of the horizontal magnification denominator from the parameter HC as the parameter HA when the subtraction non-permission signal is inactive. Of the input magnification data, the subtractor 303 relates to the horizontal direction. The denominator value (horizontal magnification denominator) and numerator value (horizontal magnification numerator) of the magnification data, the input value HC, the horizontal valid signal, the subtraction non-permission signal, and the clock are manually operated and operate in units of clocks. The horizontal effective signal is generated based on the horizontal synchronization signal, and is given a delay corresponding to the portion where resolution conversion is performed.

  The subtractor 303 sets the value of the horizontal magnification numerator as an initial value while the horizontal valid signal indicates invalidity, and outputs it as the parameter HA. When the horizontal effective signal indicates that it is valid and the subtraction non-permission signal is inactive, a value obtained by subtracting the value of the horizontal magnification denominator from the parameter HC is output as the parameter HA. On the other hand, when the subtraction non-permission signal is active, no subtraction is performed and the parameter HC is output as it is as the parameter HA.

  The comparator 304 generates an addition permission signal from the parameter HA and outputs the addition permission signal to the subsequent adder 305. When the parameter HA is 0 or less, the comparator 304 activates the addition permission signal. This addition permission signal is also output as a horizontal area movement command signal S211 indicating whether or not to move the new pixel setting area. The parameter HA is input to the adder 305 as it is.

  The adder 305 outputs, as the parameter HC, the value obtained by adding the value of the horizontal magnification numerator to the parameter HA when the addition permission signal is active. When the addition permission signal is inactive, the adder 305 outputs the parameter HA as it is as the parameter HC.

Next, the configuration of the second arithmetic circuit 306 will be described.
The second arithmetic circuit 306 operates at the end of the horizontal line in the vertical effective period based on the enlargement / reduction magnification in the vertical direction, and commands the movement of the new pixel setting area in the vertical direction as the area control signal S22. This is a block for generating a movement command signal S221 and a vertical deletion area signal S222 indicating an area where a new pixel setting is unnecessary.

  The second arithmetic circuit 306 has substantially the same configuration as the first arithmetic circuit 301 and includes a comparator 307, a subtracter 308, a comparator 309, and an adder 310.

  The comparator 307 generates a subtraction non-permission signal and outputs it to the subsequent subtracter 308. When the parameter VC from the rear stage adder 310 is 0 or less, the subtraction non-permission signal is made active. This subtraction non-permission signal is also output as a vertical deletion region signal S222 indicating whether or not the region does not require new pixel setting. Further, the parameter VC is directly input to the subtracter 308 as it is.

  The subtracter 308 outputs, as a parameter VA, a value obtained by subtracting the value of the vertical magnification denominator from the parameter VC when the subtraction non-permission signal is inactive. Of the input magnification data, the subtractor 308 relates to the vertical direction. When the denominator value (vertical magnification denominator) and numerator value (vertical magnification numerator), parameter VC, vertical valid signal, subtraction disabling signal, line end signal, and clock are input, each time a horizontal line ends Operate. The vertical effective signal is generated based on the vertical synchronization signal, and is provided with a delay corresponding to the portion where resolution conversion is performed.

  The subtracter 308 sets the value of the vertical magnification numerator as an initial value while the vertical valid signal indicates invalidity, and outputs it as the parameter VA. When the vertical valid signal is valid and the subtraction non-permission signal is inactive, the value obtained by subtracting the value of the vertical magnification denominator from the parameter VC is output as the parameter VA. On the other hand, when the subtraction non-permission signal is active, the subtraction is not performed and the parameter VC is output as it is as the parameter VA.

  The comparator 309 generates an addition permission signal from the parameter VA and outputs it to the adder 310 at the subsequent stage. When the parameter VA is 0 or less, the comparator 309 activates the addition permission signal. This addition permission signal is also output as a vertical area movement command signal indicating whether or not to move the new pixel setting area. The parameter VA is input to the adder 310 as it is.

  The adder 310 outputs, as the parameter VC, a value obtained by adding the value of the horizontal magnification numerator to the parameter VA when the addition permission signal is active. When the addition permission signal is inactive, the adder 310 outputs the parameter VA as it is as the parameter VC.

  Next, the operation in the first arithmetic circuit 301 will be described. Here, 11/9 times (enlargement) and 5/8 times (reduction) will be described as an example of the magnification data. Note that the operation of the second arithmetic circuit 306 is the same as that of the first arithmetic circuit 301 except for the difference of line by line, and thus the description thereof is omitted.

First, 11/9 times will be described.
It is assumed that the horizontal valid signal is invalid only in the first clock cycle and is valid thereafter. A series of operations from the subtracter 303 to the same subtractor 303 is one clock cycle.

Subtractor 303: The initial value 11 is set and 11 is output.
Since the comparator 304: 11 is not less than 0, the addition permission signal is inactive.
Adder 305: Since the addition permission signal is inactive, 11 is output as it is.
Since the comparator 302: 11 is not less than 0, the subtraction disabling signal is inactive.
Subtractor 303: Since the subtraction non-permission signal is inactive, 2 obtained by subtracting 9 from 11 is output.

Since the comparator 304: 2 is not less than 0, the addition permission signal is inactive.
Adder 305: Since the addition permission signal is inactive, 2 is output as it is.
Since the comparator 302: 2 is not less than 0, the subtraction disabling signal is inactive.
Subtractor 303: Since the subtraction disabling signal is inactive, -7 obtained by subtracting 9 from 2 is output.

Since the comparator 304: -7 is 0 or less, the addition permission signal is active.
Adder 305: Since the addition permission signal is active, 4 is output by adding 11 to -7.
Since the comparator 302: 4 is not less than 0, the subtraction disabling signal is inactive.
Subtractor 303: Since the subtraction disabling signal is inactive, -5 obtained by subtracting 9 from 4 is output.

Comparator 304: Since -5 is 0 or less, the addition permission signal is active.
Adder 305: Since the addition permission signal is active, 6 is output by adding 11 to -5.
Thereafter, the same operation is repeated.

  When the output value of the adder 305 after the horizontal valid signal shows valid is seen for each clock cycle, it is 2, 4, 8, 10, 1, 3, 5, 7, 9, 11, and is 11 in 11 clock cycles. Will go around. In addition, the addition permission signal is inactive in the first clock cycle in which 2 is output and the fifth clock cycle in which 1 is output, and the horizontal region movement command signal S211 is also inactive. At this time, the area for newly generating a pixel is not transferred, that is, a new pixel is generated in the same area. On the other hand, since the subtraction non-permission signal is always inactive and the horizontal deletion region signal S212 is also always inactive, there is no region where setting of a new pixel is unnecessary.

Next, 5/8 times will be described.
Subtractor 303: An initial value of 5 is set and 5 is output.
Since the comparator 304: 5 is not less than 0, the addition permission signal is inactive.
Adder 305: Since the addition permission signal is inactive, 5 is output as it is.
Since the comparator 302: 5 is not less than 0, the subtraction disabling signal is inactive.
Subtractor 303: Since the subtraction disabling signal is inactive, -3 obtained by subtracting 8 from 5 is output.

Since the comparator 304: -3 is 0 or less, the addition permission signal is active.
Adder 305: Since the addition permission signal is active, 2 is obtained by adding 5 to -3.
Since the comparator 302: 2 is not less than 0, the subtraction disabling signal is inactive.
Subtractor 303: Since the subtraction non-permission signal is inactive, -6 obtained by subtracting 2 from 8 is output.

Comparator 304: Since -6 is 0 or less, the addition permission signal is active.
Adder 305: Since the addition permission signal is active, -1 obtained by adding 5 to -6 is output.
Since the comparator 302: -1 is 0 or less, the subtraction disabling signal is inactive.
Subtractor 303: Since the subtraction disabling signal is active, -1 is output as it is.
Since the comparator 304: -1 is 0 or less, the addition permission signal is active.
Adder 305: Since the addition permission signal is active, 4 is obtained by adding 5 to -1.
Thereafter, the same operation is repeated.

  When the output value of the adder 305 after the horizontal valid signal shows valid is seen for each clock cycle, it is 2, -1, 4, 1, -2, 3, 0, -5, and it goes through every 8 clock cycles. Although it rotates, it can be said that it is one rotation in five times except when a horizontal deletion region signal S212 described later is active. The subtraction non-permission signal is active and the horizontal deletion area signal S212 is also active in the third clock period for outputting -1, the sixth clock period for outputting -2, and the eighth clock period for outputting 0. At this time, it is an area where it is not necessary to newly set a pixel. On the other hand, since the addition permission signal is always active and the horizontal area movement command signal S211 is always active, a plurality of new pixels are not generated in the same area.

  Here, the enlargement / reduction magnification data is set and inputted to a register (not shown) from the CPU or the like. Further, as the horizontal effective signal, vertical effective signal, and line end signal, signals supplied from a timing generator or the like may be used. The frequency of the clock signal is not particularly limited, and may be a frequency that allows the circuit to operate.

  Here, by adding and subtracting values (horizontal magnification denominator, horizontal magnification numerator, vertical magnification denominator, vertical magnification numerator, etc.) related to the magnification by the first arithmetic circuit 301 and the second arithmetic circuit 306. Although the area control signal S2 is generated, the area control signal S2 may be generated by a processor such as a pre-programmed CPU or DSP (abbreviation of Digital Signal Processor).

FIG. 15 is a configuration diagram of the pixel value reading control unit 103.
The pixel value reading control unit 103 shown in FIG. 15 includes a horizontal adjustment logic circuit 501, a counter 502 that counts signals from the adjustment logic circuit 501, and a vertical adjustment logic circuit 503. .

  Signals (line memory read control signal S32, register data shift control signal S33, line memory data shift control signal S31) generated by the pixel value read control unit 103 are basically sent from the region determination unit 102 during the horizontal effective period. In accordance with the output horizontal region movement command signal S211 and the vertical region movement command signal S221 output from the region determination unit 102 during the vertical effective period. On the other hand, for example, it is necessary to adjust the operation in a region where no interpolation calculation is performed at the edge of the image. The adjustment logic circuits 501 and 503 are circuits for performing the above adjustment, and adjust the horizontal region movement command signal S211 and the vertical region movement command signal S221 by the horizontal adjustment signal and the vertical adjustment signal. Note that the horizontal adjustment signal and the vertical adjustment signal are generated in consideration of the area where the interpolation calculation is performed based on the horizontal effective signal, the vertical effective signal, and the like.

  The output from the adjustment logic circuit 501 is a register data shift control signal S33. The register data shift control signal S33 is input to the counter 502 and counted up when the signal is active. The output of the counter 502 is a line memory read control signal S32, which is an address value to be read from the line memory.

On the other hand, the output from the adjustment logic circuit 503 is a line memory data shift control signal.
It should be noted that the output control signals only show the main ones when reading the pixel values, and for example, description of signals such as read enable for controlling the memory is omitted.

  FIG. 16 is a configuration diagram of the interpolation calculation unit 104. The interpolation operation unit 104 shown in this figure shows a configuration in which one of two types of interpolation methods A and B can be selected, and A and B types of horizontal and vertical coefficients as interpolation coefficients are selected signals. A selector group 609 can be selected and output.

  FIG. 16 shows a circuit that outputs a horizontal interpolation coefficient, a circuit that outputs a vertical interpolation coefficient, and new pixels from 16 original image pixels D11 to D44 from the horizontal and vertical interpolation coefficients and the pixel value storage unit 101. The circuit is divided into three circuits: a circuit for calculating the interpolated pixel value. This is a description method in which what is originally one circuit configuration is divided into three circuits for easy understanding of signal input / output.

  The interpolation calculation unit 104 includes a first interpolation coefficient reading control unit configured by a count up / down circuit 601 and a determiner 602, a first interpolation coefficient storage unit configured by an SRAM group 603, and a selector group 604. A first interpolation coefficient inversion switching unit configured, a second interpolation coefficient reading control unit configured by a count-up / down circuit 605 and a determiner 606, and a second interpolation coefficient storage configured by an SRAM group 607 , A second interpolation coefficient inversion switching unit composed of a selector group 608, a coefficient selection unit composed of a selector group 609, a multiplier 610, an adder 611, a multiplier 612 and an adder 613. A pixel value calculation unit.

  The count up / down circuit 601 operates in units of clocks and generates an SRAM read address. The initial value is 0, and count-up / count-down is repeated when a new pixel is set in the horizontal direction, that is, when the horizontal valid signal is valid and the horizontal deletion region signal S212 is inactive. The selection of count up or count down follows the up / down signal from the decision unit 602.

  The determination unit 602 determines the SRAM read address output from the count-up / down circuit 601 based on the value related to the horizontal magnification numerator, and outputs an up / down signal for selecting whether to count up or down. To do. A value obtained by cutting the least significant bit of the horizontal magnification numerator is the maximum count-up value, and the count-up / down circuit 601 generates an up / down signal so as to repeat between 0 and the maximum value.

  However, if the least significant bit is ‘1’, it is ordered to count down after repeating the maximum value twice. As a result, the number from 0 to just before the next 0 coincides with the number of horizontal magnification numerators, and becomes the number of patterns of the relationship of the horizontal position of the new pixel in the new pixel setting area.

  The SRAM group 603 stores interpolation coefficients necessary for horizontal interpolation calculation in advance according to the enlargement / reduction ratio. When interpolation is performed with 16 points, four interpolation coefficients in the horizontal direction are required for each interpolation method, and eight SRAMs are arranged in consideration of the assumption that the interpolation methods are A and B types. If a plurality of types of coefficient values are stored in the same SRAM, the number of SRAMs can be changed.

  Each SRAM stores interpolation coefficients at addresses from 0 to the maximum value using the symmetry of the interpolation coefficients described above. The stored interpolation coefficient is read according to the SRAM read address from the count up / down circuit 601.

  The selector group 604 is for switching the correspondence between the four interpolation coefficients output from the SRAM group 603 and the horizontal first to fourth coefficients in accordance with the symmetry of the interpolation coefficients. Specifically, when the up / down signal from the determiner 602 is a signal indicating up, interpolation coefficients for multiplying the pixel values of the original image at the four horizontally arranged points in order from the left are respectively set to the horizontal first. When the coefficient, the horizontal second coefficient, the horizontal third coefficient, and the horizontal fourth coefficient are used, when the signal indicates down, the horizontal first coefficient and the horizontal fourth coefficient are switched, and the horizontal second coefficient and horizontal horizontal coefficient are switched. An appropriate interpolation coefficient can be obtained by replacing the interpolation coefficient that has been the third coefficient.

  The count up / down circuit 605 operates every time one horizontal line is finished, and generates an SRAM read address. The initial value is 0, and count-up / count-down is repeated when a new pixel is set in the vertical direction, that is, when the vertical valid signal indicates validity and the vertical deletion region signal S222 is inactive. The selection of count up or count down follows the up / down signal from the decision unit 606.

  The determination unit 606 determines the SRAM read address output from the count up / down circuit 605 based on the value related to the vertical magnification numerator, and outputs an up / down signal for selecting whether to count up or down. To do. A value obtained by cutting the least significant bit of the vertical magnification numerator is the maximum count-up value, and the up / down signal is generated so that the count-up / down circuit 605 repeats between 0 and the maximum value.

  However, if the least significant bit is ‘1’, it is ordered to count down after repeating the maximum value twice. As a result, the number from 0 to just before the next 0 coincides with the number of vertical magnification numerators, and becomes the number of patterns of the relationship between the vertical positions of the new pixels in the new pixel setting area.

  The SRAM group 607 stores interpolation coefficients necessary for the vertical interpolation calculation in advance according to the enlargement / reduction ratio. When interpolation is performed with 16 points, four interpolation coefficients in the vertical direction are required for each interpolation method, and eight SRAMs are arranged in consideration that the interpolation methods are assumed to be A and B types. If a plurality of types of coefficient values are stored in the same SRAM, the number of SRAMs can be changed.

  Each SRAM stores interpolation coefficients at addresses from 0 to the maximum value using the symmetry of the interpolation coefficients described above. Reading of the stored interpolation coefficient is based on the SRAM read address from the count up / down circuit 608.

  The selector group 608 is for switching the correspondence relationship between the four interpolation coefficients output from the SRAM group 607 and the vertical first to fourth coefficients according to the symmetry of the interpolation coefficients. Specifically, when the up / down signal from the determiner 606 is a signal indicating up, interpolation coefficients for multiplying the pixel values of the original image at the four vertically arranged points in order from the top are respectively set to the vertical first. When the coefficient, the vertical second coefficient, the vertical third coefficient, and the vertical fourth coefficient are used, the vertical first coefficient and the vertical fourth coefficient are exchanged when the signal indicates down, and the vertical second coefficient and the vertical coefficient An appropriate interpolation coefficient can be obtained by replacing the interpolation coefficient that has been the third coefficient.

  In the above configuration, the method of reducing the SRAM storage area to about half using the symmetry of the interpolation coefficient in both the horizontal direction and the vertical direction has been described. However, all patterns of the positional relationship of the new pixels in the new pixel setting area are described. Corresponding to the above, it is also possible to realize the method by storing and reading the interpolation coefficient value in the SRAM. In this case, the count / up / down circuit repeats only 0 reset and count-up, and the inversion function is not required, but the storage area of the SRAM is increased approximately twice.

  The selector group 609 is a selector for selecting two types of interpolation methods A and B, and is selected by a selection signal based on, for example, a pixel value distribution of 16 original image pixel groups surrounding a new pixel setting area.

  The multiplier 610, the adder 611, the multiplier 612, and the adder 613 include four horizontal interpolation coefficients in the horizontal direction, four vertical interpolation coefficients in the vertical direction, and pixel values D11, D12 of the 16 original image pixel groups. The pixel value of the new pixel is calculated from D13, D14, D21, D22, D23, D24, D31, D32, D33, D34, D41, D42, D43, and D44.

  FIG. 17 is a configuration diagram of an image density determination unit 620 that is provided in the interpolation calculation unit 104 and supplies a selection signal to the selector group 609.

  The image density determination unit 620 shown in FIG. 17 includes a horizontal tilt calculator 701, a vertical tilt calculator 702, an average pixel value calculator 703, a variance calculator 704, and a determiner 705, and receives a pixel as an input signal. The pixel values D11 to D44 of the original image from the value storage unit 101 are input.

  The horizontal inclination calculator 701 includes four difference detectors, one adder, and one absolute value circuit, and the pixel value at the left end of a 16-point pixel group surrounding a new pixel setting area arranged 4 × 4 Then, the absolute value of the sum of the difference from the corresponding pixel value on the right end is calculated as the horizontal inclination.

  The vertical tilt calculator 702 includes four difference detectors, one adder, and one absolute value circuit, and is the uppermost pixel of a group of 16 pixels surrounding a 4 × 4 array of new pixel setting areas. The absolute value of the sum of the difference between the value and the corresponding pixel value at the lower end is calculated as the vertical slope.

  The average pixel value calculator 703 includes one adder and one 1/16 multiplier, and calculates an average value of pixel values of 16 pixel groups surrounding the new pixel setting area.

  The variance calculator 704 includes 16 difference detectors, 16 absolute value circuits, and one adder, and each pixel value of the 16 pixel groups surrounding the new pixel setting area and the average value. Is calculated as an index similar to variance.

  The determination unit 705 is a threshold value for setting indexes similar to the horizontal tilt, vertical tilt, and variance output from each of the horizontal tilt calculator 701, the vertical tilt calculator 702, and the variance calculator 704, respectively. Based on the result of the comparison, the density characteristic of the original image is determined, and a selection signal for selecting the type of interpolation method according to the determination result is output.

  Note that although a configuration based on values and slopes similar to dispersion has been described as an example of selecting an interpolation method, edge detection results, dispersion, deviation, and the like can be used as determination elements.

  The present invention is not limited to the case where the pixel value of a newly set pixel is calculated from the values of 16 neighboring pixels, and a new pixel is placed in an area surrounded by at least four or more original image pixel groups. The pixel value can be obtained by interpolation from the value of the pixel group of the original image. It is possible to easily realize control for determining a region where a pixel is newly provided, and to appropriately provide an interpolation coefficient used for interpolation without obtaining the position of the new pixel.

1 is a diagram illustrating a schematic configuration of an image resolution conversion apparatus according to a first embodiment of the present invention. The figure which shows the structural example of a pixel value storage part. The figure which shows the structure of the original image pixel group of 16 points | pieces arranged 4x4 surrounding a new pixel setting area | region. The figure explaining the area | region setting for 16-point interpolation calculation. The figure explaining a new pixel setting area. The figure which shows the example of an expansion process. The figure which shows the example of a reduction process. The figure explaining the example which performs 16-point interpolation using 16 original image pixels surrounding a new pixel. The figure which shows arrangement | positioning of the new pixels af which took in the symmetry of a pixel position in the new pixel preparation area at the time of considering by 4 point interpolation in the enlargement process of 11/9 times. The figure which represented the interpolation coefficient at the time of considering the 4-point interpolation of FIG. 9 as an interpolation coefficient for every pixel of the 1st, 2nd, 3rd, 4th pixel which is an original pixel. The figure which shows arrangement | positioning of the new pixels ac which took in the symmetry of a pixel position in the new pixel preparation area at the time of thinking by 4 point interpolation in the reduction process of 5/8 times. The figure which represented the interpolation coefficient at the time of considering the 4-point interpolation of FIG. 11 as an interpolation coefficient for every pixel of the 1st, 2nd, 3rd, 4th pixel which is an original pixel. The block diagram of an area | region determination part. The figure explaining the background of a structure of an area | region determination part. The block diagram of a pixel value reading control part. The block diagram of the interpolation calculating part in case there are two types of interpolation methods. The block diagram of the image density determination part which is provided in an interpolation calculating part and supplies a selection signal to a selector group.

Explanation of symbols

101 ... Pixel value storage unit 102 ... New pixel setting region determination unit (region determination unit)
103: Pixel value reading control unit 104 ... Interpolation calculation unit 105 ... Pixel value writing control unit
Agent Patent Attorney Susumu Ito

Claims (3)

An image resolution conversion device that converts an original image composed of a plurality of pixels into an image having a resolution multiplied by a set resolution conversion magnification,
A pixel value storage unit storing pixel values of each pixel of the original image;
A region in which pixels are newly provided based on an integer value serving as a denominator and an integer value serving as a numerator when the set resolution conversion magnification is expressed by an integer ratio, and sequentially determined according to the raster arrangement order of the new pixels A decision unit;
In accordance with the determination result, a pixel value reading control unit that generates an output control signal for outputting the pixel value of the original pixel group corresponding to the region from the pixel value storage unit;
When the resolution conversion magnification is expressed as an integer ratio, an interpolation coefficient group that is multiplied by each pixel of the pixel group is stored in each address of a plurality of addresses corresponding to integers that are numerators, for each pixel group. An interpolation coefficient storage unit; an interpolation coefficient reading control unit that generates a signal designating the address in synchronization with the output control signal; and an interpolation coefficient group output from the interpolation coefficient storage unit by the address signal; A pixel value calculation unit that calculates a pixel value of the new pixel based on the value of the pixel group output from the pixel value storage unit, and from the pixel value storage unit according to the output control signal The pixel value of the new pixel is interpolated based on the read pixel value of the original pixel group and the internal division ratio from the adjacent pixels of the original image at the new pixel position specified by the region determination unit. An interpolation calculation unit,
An image resolution conversion device characterized by comprising: The region determination unit
A first arithmetic circuit that determines the tilted castle based on a resolution conversion magnification in the line direction of the image;
A second arithmetic circuit that determines the region based on a resolution conversion magnification of a non-line component that intersects the line direction;
The image resolution conversion apparatus according to claim 1, further comprising: The interpolation calculation unit
An interpolation coefficient storage unit in which an interpolation coefficient corresponding to the density characteristic of the original image is stored;
An image density determination unit for determining density characteristics of the original image;
A coefficient selection unit that selects the interpolation coefficient according to the determination result;
The image resolution conversion apparatus according to claim 1, further comprising:

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