JP4372879B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a circuit including a thin film transistor over a substrate having an insulating surface, and a manufacturing method thereof. For example, the present invention relates to an electro-optical device typified by a liquid crystal display device and a configuration of an electronic apparatus equipped with the electro-optical device. Note that in this specification, a semiconductor device refers to all devices that function by utilizing semiconductor characteristics, and includes the above-described electro-optical device and electronic equipment including the electro-optical device in its category.
[0002]
[Prior art]
Development of a semiconductor device having a large-area integrated circuit formed using a thin film transistor (hereinafter referred to as TFT) over a substrate having an insulating surface is in progress. Active matrix liquid crystal display devices, EL display devices, and contact image sensors are known as representative examples. TFTs are classified according to their structure and manufacturing method. In particular, a TFT (crystalline TFT) in which a semiconductor film having a crystal structure is used as an active layer has high field effect mobility, and thus various functional circuits can be formed.
[0003]
For example, in an active matrix liquid crystal display device, an integrated circuit such as a pixel matrix circuit composed of n-channel TFTs for each functional block, a shift register circuit based on a CMOS circuit, a level shifter circuit, a buffer circuit, a sampling circuit, etc. Was formed on a single substrate. In the contact image sensor, integrated circuits such as a sample hold circuit, a shift register circuit, and a multiplexer circuit are formed using TFTs.
[0004]
Since these circuits do not necessarily have the same operating conditions, the characteristics required for the TFTs are of course different. The pixel matrix circuit has a configuration in which a switch element composed of an n-channel TFT and an auxiliary storage capacitor are provided, and is driven by applying a voltage to the liquid crystal. Here, the liquid crystal needs to be driven by alternating current, and a method called frame inversion driving has been adopted. Therefore, the required TFT characteristics require that the leakage current be sufficiently reduced. In addition, since a high driving voltage is applied to the buffer circuit, it is necessary to increase the breakdown voltage. In addition, in order to increase the current driving capability, it is necessary to secure a sufficient on-current.
[0005]
However, there is a problem that the off-current of the crystalline TFT tends to be high. Crystalline TFTs are still considered to be less reliable than MOS transistors (transistors fabricated on a single crystal semiconductor substrate) used in LSI and the like. For example, a deterioration phenomenon such as a decrease in on-current may be observed in a crystalline TFT. This is due to the hot carrier effect, and it has been considered that hot carriers generated by a high electric field near the drain cause a deterioration phenomenon.
[0006]
As a TFT structure, a lightly doped drain (LDD) structure is known. In this structure, a low concentration impurity region is provided between a channel region and a source region or a drain region to which an impurity is added at a high concentration. This low concentration impurity region is called an LDD region. The LDD structure further includes a GOLD (Gate-drain Overlapped LDD) structure that overlaps with the gate electrode and an offset LDD structure that does not overlap with the gate electrode, depending on the positional relationship with the gate electrode. The GOLD structure could relax the high electric field near the drain to prevent the hot carrier effect and improve the reliability. For example, “Mutsuko Hatano, Hajime Akimoto and Takeshi Sakai, IEDM97 TECHNICAL DIGEST, p523-526, 1997” has a GOLD structure with sidewalls made of silicon, but extremely superior reliability compared to TFTs with other structures. Has been confirmed to be obtained.
[0007]
Further, an active matrix type liquid crystal display device used for direct viewing or projector needs to be provided with a light shielding film to block stray light incident on the TFT. The light shielding film is formed on the substrate on which the TFT is formed or on the opposite substrate in accordance with the TFT arrangement.
[0008]
[Problems to be solved by the invention]
However, the GOLD structure has a problem that the off-current becomes larger than that of a normal LDD structure. In order to prevent an increase in off-state current, a multi-gate / multi-channel structure is provided in which a plurality of channel formation regions and a plurality of gate electrodes provided corresponding to each of the plurality of channel formation regions are provided in one TFT. Although it is possible, the TFT having the GOLD structure is not sufficient by itself. Therefore, it is not always preferable to form all TFTs of a large area integrated circuit with the same structure. For example, in an n-channel TFT constituting a pixel matrix circuit, power consumption increases or abnormality appears in image display when the off-current increases, so it is not preferable to apply a crystalline TFT having a GOLD structure as it is. In addition, the offset LDD structure has a problem in that the on-current decreases due to an increase in series resistance. The on-current can be freely designed according to the channel width of the TFT, but for example, it is not always necessary to provide an offset TFT in the TFT constituting the buffer circuit.
[0009]
Further, in an active matrix liquid crystal display device used for direct viewing and projectors, it has been an important issue to improve the aperture ratio in order to improve the image quality. In order to improve the aperture ratio, the area for forming the light shielding film may be reduced as much as possible, but for that purpose, it is necessary to reduce the area for forming the TFT and the storage capacitor of the pixel matrix circuit. It was. However, if the pixel TFT has a multi-gate / multi-channel structure in order to reduce the off-current, the size of the TFT has inevitably increased due to restrictions on design rules.
[0010]
The present invention is a technique for solving such a problem, and an object thereof is to realize a crystalline TFT capable of obtaining reliability equal to or higher than that of a MOS transistor. An object of the present invention is to improve the reliability of a semiconductor device having a large-area integrated circuit in which various functional circuits are formed using such crystalline TFTs.
[0011]
Another object of the present invention is to improve the aperture ratio of an active matrix liquid crystal display device with respect to the configuration of a TFT and a storage capacitor of a pixel matrix circuit.
[0012]
[Means for Solving the Problems]
In order to solve the above problems, the structure of the present invention includes an island-shaped semiconductor layer, a gate insulating film formed in contact with the island-shaped semiconductor layer on a substrate having an insulating surface, and the gate insulating film. In the semiconductor device having one gate electrode provided in contact with and corresponding to the island-shaped semiconductor layer, the island-shaped semiconductor layer has a plurality of channel formation regions and one conductive layer forming a source region or a drain region. A first impurity region of a type, a third impurity region of one conductivity type formed in contact with the first impurity region, and a one conductivity type formed of one end in contact with the third impurity region A second impurity region, and a second impurity region of one conductivity type formed at both ends thereof in contact with the channel formation region, wherein the second impurity region and the plurality of channel formation regions include: Through the gate insulating film. It is characterized in that overlaps with the electrode. Further, the island-shaped semiconductor layer is formed with a plurality of channel formation regions, a first impurity region of one conductivity type forming a source region or a drain region, and one end formed in contact with the first impurity region. A second impurity region of one conductivity type and a second impurity region of one conductivity type, both ends of which are in contact with the channel formation region; the second impurity region; and the plurality of channel formation regions; May be configured to overlap the gate electrode with the gate insulating film interposed therebetween.
[0013]
Another structure of the present invention is a semiconductor device having a matrix circuit formed of an n-channel thin film transistor, wherein the n-channel thin film transistor forms a plurality of channel formation regions and a source region or a drain region. The first impurity region, the third impurity region of one conductivity type formed in contact with the first impurity region, and the one conductivity type of first impurity region formed in contact with the third impurity region. Two impurity regions and a second impurity region of one conductivity type formed at both ends in contact with the channel formation region, and the second impurity region and the plurality of channel formation regions are gate-insulated. It is characterized in that it overlaps with one gate electrode provided corresponding to the n-channel thin film transistor through a film.
[0014]
According to another configuration of the present invention, in the semiconductor device having a CMOS circuit formed of an n-channel thin film transistor and a p-channel thin film transistor, the plurality of n-channel thin film transistors includes a plurality of channel formation regions, a source region, Alternatively, the first impurity region of one conductivity type forming a drain region, the third impurity region of one conductivity type formed in contact with the first impurity region, and one end in contact with the third impurity region. A second impurity region of one conductivity type formed by the second impurity region and a second impurity region of one conductivity type formed at both ends in contact with the channel formation region, the second impurity region, The channel formation region is overlapped with one gate electrode provided corresponding to the n-channel thin film transistor through a gate insulating film. That. The plurality of n-channel thin film transistors are formed with a plurality of channel formation regions, a first impurity region of one conductivity type that forms a source region or a drain region, and one end in contact with the first impurity region. A second impurity region of one conductivity type, and a second impurity region of one conductivity type formed at both ends in contact with the channel formation region, and the second impurity region and the plurality of channel formations The region may overlap with one gate electrode provided corresponding to the n-channel thin film transistor with a gate insulating film interposed therebetween.
[0015]
Another structure of the present invention is a semiconductor device having a plurality of thin film transistors arranged in a matrix and a storage capacitor provided corresponding to each of the plurality of thin film transistors, the thin film transistor including an island-shaped semiconductor layer A gate insulating film formed in contact with the island-shaped semiconductor layer, and one gate electrode provided in contact with the gate insulating film and corresponding to the island-shaped semiconductor layer. The semiconductor layer includes a plurality of channel formation regions, a first impurity region of one conductivity type forming a source region or a drain region, and a third impurity of one conductivity type formed in contact with the first impurity region. A first conductivity type second impurity region which is provided so as to overlap with the gate electrode through a gate insulating film and has one end in contact with the third impurity region, and a channel forming region at both ends A second impurity region of one conductivity type formed in contact therewith, and the storage capacitor includes a first insulating layer having a first opening on the thin film transistor, and the first insulating layer. A conductive film formed on the thin film transistor; a pixel electrode extending on the conductive film; and a dielectric film provided between the conductive film and the pixel electrode. The thin film transistor is connected to the thin film transistor through one aperture. The thin film transistor includes an island-shaped semiconductor layer, a gate insulating film formed in contact with the island-shaped semiconductor layer, and one gate electrode provided in contact with the gate insulating film and corresponding to the island-shaped semiconductor layer. The island-shaped semiconductor layer is formed in contact with the first impurity region, a plurality of channel formation regions, a first impurity region of one conductivity type forming a source region or a drain region, and The one-conductivity-type third impurity region is provided so as to overlap the gate electrode through the gate insulating film, and one end of the second-conductivity-type impurity is formed in contact with the third impurity region. A first insulating layer having a first opening portion on the thin film transistor, the storage capacitor including a region and a second impurity region of one conductivity type formed in contact with the channel formation region at both ends. And on the first insulating layer A second insulating layer having a second hole portion formed in a turn and overlapping the first hole portion; a conductive film formed on the thin film transistor through the first insulating layer; A pixel electrode extending on the conductive film; and a dielectric film provided between the conductive film and the pixel electrode. The first opening and the second opening The structure may be connected to the thin film transistor.
[0016]
Another configuration of the present invention includes a plurality of thin film transistors arranged in a matrix, a storage capacitor and a pixel electrode provided corresponding to each of the plurality of thin film transistors, an alignment film formed on the pixel electrode, The thin film transistor includes an island-shaped semiconductor layer, a gate insulating film formed in contact with the island-shaped semiconductor layer, and in contact with the gate insulating film and corresponding to the island-shaped semiconductor layer. The island-like semiconductor layer includes a plurality of channel formation regions, a first conductivity region of one conductivity type forming a source region or a drain region, and the first A third conductivity region of one conductivity type formed in contact with the impurity region and a gate electrode provided to overlap the gate electrode with one end formed in contact with the third impurity region The second impurity region and one conductivity type second impurity region formed at both ends in contact with the channel formation region, and the storage capacitor has a first opening on the thin film transistor A first insulating layer; a conductive film formed on the thin film transistor through the first insulating layer; the pixel electrode extending on the conductive film; and the conductive film and the pixel electrode. A dielectric film provided therebetween, connected to the thin film transistor through the first opening, and the alignment film is made of the same material as the dielectric film. It is a feature. The thin film transistor includes an island-shaped semiconductor layer, a gate insulating film formed in contact with the island-shaped semiconductor layer, and one gate electrode provided in contact with the gate insulating film and corresponding to the island-shaped semiconductor layer. The island-shaped semiconductor layer is formed in contact with the first impurity region, a plurality of channel formation regions, a first impurity region of one conductivity type forming a source region or a drain region, and The one-conductivity-type third impurity region is provided so as to overlap the gate electrode through the gate insulating film, and one end of the second-conductivity-type impurity is formed in contact with the third impurity region. A first insulating layer having a first opening portion on the thin film transistor, the storage capacitor including a region and a second impurity region of one conductivity type formed in contact with the channel formation region at both ends. And on the first insulating layer A second insulating layer having a second hole portion formed in a turn and overlapping the first hole portion; a conductive film formed on the thin film transistor through the first insulating layer; The pixel electrode extending on the conductive film, and a dielectric film provided between the conductive film and the pixel electrode, the first opening portion and the second opening portion, The alignment film may be formed of the same material as that of the dielectric film.
[0017]
The method for manufacturing a semiconductor device of the present invention includes a step of forming an island-shaped semiconductor layer over a substrate having an insulating surface, a step of forming a gate insulating film in contact with the island-shaped semiconductor layer, Adding a first impurity element to a selected region of the island-shaped semiconductor layer to form a first impurity region for forming a source region or a drain region; and adding one conductivity type impurity element to the island-shaped semiconductor A third impurity region in contact with the first impurity region, a second impurity region with one end in contact with the third impurity region, and both ends in contact with the channel formation region are added to a selected region of the layer And a step of forming a second impurity region, and a step of forming a gate electrode overlapping with the second impurity region with the gate insulating film interposed therebetween.
[0018]
In addition, another configuration of the present invention includes a step of forming an island-shaped semiconductor layer over a substrate having an insulating surface, a step of forming a gate insulating film in contact with the island-shaped semiconductor layer, and one conductivity type An impurity element is added to a selected region of the island-shaped semiconductor layer to form a first impurity region for forming a source region or a drain region; and an impurity element of one conductivity type is added to the island-shaped semiconductor layer. Adding to the selected region, forming a second impurity region whose one end is in contact with the first impurity region and a second impurity region whose both ends are in contact with the channel formation region; and And a step of forming a gate electrode overlapping with the second impurity region.
[0019]
Another embodiment of the present invention is a method for manufacturing a semiconductor device having a matrix circuit formed using an n-channel thin film transistor, in which the n-channel thin film transistor forms an island-shaped semiconductor layer over a substrate having an insulating surface. A step of forming a gate insulating film in contact with the island-shaped semiconductor layer, and adding an impurity element of one conductivity type to a selected region of the island-shaped semiconductor layer to form a source region or a drain region. A step of forming a first impurity region to be formed; a third impurity region in contact with the first impurity region by adding an impurity element of one conductivity type to a selected region of the island-shaped semiconductor layer; Forming a second impurity region having one end in contact with the third impurity region and a second impurity region having both ends in contact with the channel formation region; It is characterized by being formed and a step of forming a gate electrode overlapping the second impurity region.
[0020]
Another embodiment of the present invention is a method for manufacturing a semiconductor device having a CMOS circuit formed of an n-channel thin film transistor and a p-channel thin film transistor, wherein the n-channel thin film transistor is formed over a substrate having an insulating surface. A step of forming an island-shaped semiconductor layer; a step of forming a gate insulating film in contact with the island-shaped semiconductor layer; and adding an impurity element of one conductivity type to a selected region of the island-shaped semiconductor layer; A step of forming a first impurity region for forming a source region or a drain region; and a step of adding an impurity element of one conductivity type to a selected region of the island-shaped semiconductor layer to be in contact with the first impurity region. Forming a third impurity region, a second impurity region having one end in contact with the third impurity region, and a second impurity region having both ends in contact with the channel formation region; Through the gate insulating film, it is characterized by being formed and a step of forming a gate electrode overlapping the second impurity region.
[0021]
Another embodiment of the present invention is a method for manufacturing a semiconductor device having a CMOS circuit formed of an n-channel thin film transistor and a p-channel thin film transistor, wherein the n-channel thin film transistor is formed over a substrate having an insulating surface. A step of forming an island-shaped semiconductor layer; a step of forming a gate insulating film in contact with the island-shaped semiconductor layer; and adding an impurity element of one conductivity type to a selected region of the island-shaped semiconductor layer; Forming a first impurity region for forming a source region or a drain region, and adding one conductivity type impurity element to a selected region of the island-shaped semiconductor layer, and one end of the first impurity region is formed in the first impurity region; Forming a second impurity region in contact with each other, a second impurity region having both ends in contact with the channel formation region, and the second impurity region through the gate insulating film Forming a gate electrode overlapping, it is characterized by being formed from.
[0022]
Another embodiment of the present invention is a method for manufacturing a semiconductor device having a plurality of thin film transistors arranged in a matrix and a storage capacitor provided corresponding to each of the plurality of thin film transistors. A step of forming an island-shaped semiconductor layer over a substrate having a surface; a step of forming a gate insulating film in contact with the island-shaped semiconductor layer; and an impurity element having one conductivity type selected from the island-shaped semiconductor layer. Forming a first impurity region to form a source region or a drain region, and adding one conductivity type impurity element to a selected region of the island-shaped semiconductor layer, Forming a third impurity region in contact with one impurity region, a second impurity region in which one end is in contact with the third impurity region, and a second impurity region in which both ends are in contact with the channel formation region. And a step of forming a gate electrode that overlaps with the second impurity region through the gate insulating film, and the storage capacitor has a first opening portion on the thin film transistor. Forming an insulating layer, forming a conductive film on the thin film transistor via the first insulating layer, forming a dielectric film on the conductive film, and the dielectric And a step of extending a pixel electrode over the conductive film through a film.
[0023]
Another embodiment of the present invention is a method for manufacturing a semiconductor device having a plurality of thin film transistors arranged in a matrix and a storage capacitor provided corresponding to each of the plurality of thin film transistors. A step of forming an island-shaped semiconductor layer over a substrate having a surface; a step of forming a gate insulating film in contact with the island-shaped semiconductor layer; and an impurity element having one conductivity type selected from the island-shaped semiconductor layer. Forming a first impurity region to form a source region or a drain region, and adding one conductivity type impurity element to a selected region of the island-shaped semiconductor layer, A third impurity region in contact with one impurity region, a second impurity region in which one end is in contact with the third impurity region, and a second impurity region in which both ends are in contact with the channel formation region, Forming a gate electrode that overlaps with the second impurity region through the gate insulating film, and the storage capacitor has a first opening portion on the thin film transistor. Forming a first insulating layer; forming a second insulating layer having a second opening portion overlapping the first opening portion on a part of the first insulating layer; Forming a conductive film on the thin film transistor through the first insulating layer; forming a dielectric film on the conductive film; and over the conductive film through the dielectric film. And a step of extending the pixel electrode to form a pixel electrode.
[0024]
According to another configuration of the present invention, a plurality of thin film transistors arranged in a matrix, a storage capacitor and a pixel electrode provided corresponding to each of the plurality of thin film transistors, and an orientation formed on the pixel electrode In the method for manufacturing a semiconductor device having a film, the thin film transistor includes a step of forming an island-shaped semiconductor layer over a substrate having an insulating surface, and a step of forming a gate insulating film in contact with the island-shaped semiconductor layer Adding a first conductivity type impurity element to a selected region of the island-shaped semiconductor layer to form a first impurity region for forming a source region or a drain region; and A third impurity region in contact with the first impurity region, a second impurity region with one end in contact with the third impurity region, and both ends added to a selected region of the island-shaped semiconductor layer Forming a second impurity region in contact with the channel formation region, and forming a gate electrode overlapping with the second impurity region via the gate insulating film, and Forming a first insulating layer having a first opening on the thin film transistor; forming a conductive film on the thin film transistor through the first insulating layer; and And forming the pixel electrode on the conductive film through the dielectric film, and the alignment film is the same as the dielectric film. It is characterized by being made of material.
[0025]
According to another configuration of the present invention, a plurality of thin film transistors arranged in a matrix, a storage capacitor and a pixel electrode provided corresponding to each of the plurality of thin film transistors, and an orientation formed on the pixel electrode In the method for manufacturing a semiconductor device having a film, the thin film transistor includes a step of forming an island-shaped semiconductor layer over a substrate having an insulating surface, and a step of forming a gate insulating film in contact with the island-shaped semiconductor layer Adding a first conductivity type impurity element to a selected region of the island-shaped semiconductor layer to form a first impurity region for forming a source region or a drain region; and A third impurity region in contact with the first impurity region, a second impurity region with one end in contact with the third impurity region, and both ends added to a selected region of the island-shaped semiconductor layer Forming a second impurity region in contact with the channel formation region, and forming a gate electrode overlapping with the second impurity region via the gate insulating film, and the storage capacitor is formed by: Forming a first insulating layer having a first opening on the thin film transistor; and a second opening overlapping with the first opening on a part of the first insulating layer A step of forming a second insulating layer comprising: a step of forming a conductive film on the thin film transistor via the first insulating layer; a step of forming a dielectric film on the conductive film; A step of extending the pixel electrode on the conductive film through the dielectric film, and the alignment film is formed of the same material as the dielectric film. Yes.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
[Embodiment 1]
An embodiment of the present invention will be described with reference to FIGS. Here, a method for simultaneously manufacturing a pixel matrix circuit and TFTs of a driver circuit provided in the periphery thereof will be described.
[0027]
(Process for forming island-like semiconductor layer and gate insulating film)
In FIG. 1, a quartz substrate is used as the substrate 101 from the viewpoint of heat resistance. A base film 102 made of a silicon oxide film, a silicon nitride film, or a silicon nitride oxide film was formed to a thickness of 100 to 400 nm on the surface of the substrate 101 where a TFT is to be formed by plasma CVD or sputtering. The base film 102 may be formed in a two-layer structure in which a silicon nitride film has a thickness of 25 to 100 nm, here 50 nm, and a silicon oxide film has a thickness of 50 to 300 nm, here 150 nm (not shown). ). The base film 102 is provided to prevent impurity contamination from the substrate, and is not necessarily provided when a quartz substrate is used. Next, an amorphous silicon film having a thickness of 20 to 100 nm was formed on the base film 102 by a known film formation method. Although it depends on the amount of hydrogen contained in the amorphous silicon film, it is preferable that the dehydrogenation treatment is performed by heating at 400 to 550 ° C. for several hours, and the crystallization step is performed with the amount of hydrogen contained being 5 atom% or less. . Although an amorphous silicon film may be formed by other manufacturing methods such as a sputtering method or an evaporation method, it is desirable to sufficiently reduce impurity elements such as oxygen and nitrogen contained in the film. Since the base film and the amorphous silicon film can be formed by the same film formation method, they may be formed continuously. After the formation of the base film, it is possible to prevent surface contamination by preventing exposure to the air atmosphere and to reduce variation in characteristics of the manufactured TFT. A known laser crystallization technique or thermal crystallization technique may be used for the step of forming the crystalline silicon film from the amorphous silicon film. Alternatively, a crystalline silicon film may be formed by a thermal crystallization method using a catalyst element that promotes crystallization of silicon. In addition, a microcrystalline silicon film may be used, or a crystalline silicon film may be directly deposited. Further, a crystalline silicon film may be formed using a known technique of SOI (Silicon On Insulators) in which single crystal silicon is bonded onto a substrate. Unnecessary portions of the crystalline silicon film thus formed were removed by etching to form island-like semiconductor layers 103 to 106. In the region where the n-channel TFT of the crystalline silicon film is formed, in order to control the threshold voltage, 1 × 10 5 in advance. ¹⁵ ~ 5x10 ¹⁷ cm ^-3 Boron (B) may be added at a moderate concentration. Next, a gate insulating film 107 containing silicon oxide or silicon nitride as a main component was formed so as to cover the island-shaped semiconductor layers 103 to 106. The gate insulating film 107 may be formed to a thickness of 10 to 200 nm, preferably 50 to 150 nm. For example, N by plasma CVD method ₂ O and SiH _Four A silicon oxynitride film with a thickness of 75 nm may be formed, and then thermally oxidized at 800 to 1000 ° C. in an oxygen atmosphere or a mixed atmosphere of oxygen and hydrochloric acid to form a 115 nm gate insulating film (FIG. 1A). ).
[0028]
(Formation of low-concentration impurity regions)
In order to form a low concentration impurity region (referred to as a second impurity region and a third impurity region in the present invention) to be an LDD region in the n-channel TFT, the entire surface of the island-shaped semiconductor layer 103, Resist masks 108 to 111 covering channel formation regions of the semiconductor layers 104 to 105 were formed. At this time, a resist mask may be formed in a region where a wiring is to be formed. Then, a step of forming a low concentration impurity region by adding an impurity element imparting n-type was performed. Here, phosphorus is used and phosphine (PH _Three ) Using an ion doping method. In this step, phosphorus is added to the underlying semiconductor layer through the gate insulating film 107. The concentration of phosphorus added is 1 × 10 ¹⁶ ~ 1x10 ¹⁹ atoms / cm ^Three In the range of 1 × 10 ¹⁸ atoms / cm ^Three It was. Then, low-concentration impurity regions 112 to 120 in which phosphorus was added to the island-like semiconductor layers were formed. In order to realize the configuration of the present invention, for example, two or more low-concentration impurity regions are formed in the island-like semiconductor layer 106 of the pixel matrix circuit. Thereafter, heat treatment was performed at 400 to 900 ° C., preferably 600 to 800 ° C. in a nitrogen atmosphere for 1 to 12 hours, and a step of activating the impurity element imparting n-type added in this step was performed (see FIG. 1 (B)).
[0029]
(Formation of conductive film for gate electrode and wiring)
The first conductive film 121 is formed of a conductive material containing an element selected from tantalum (Ta), titanium (Ti), molybdenum (Mo), and tungsten (W) as a main component and has a thickness of 10 to 100 nm. did. Tantalum nitride (TaN) or tungsten nitride (WN) can be used for the first conductive layer. Although not shown, a silicon film having a thickness of about 2 to 20 nm may be formed under the first conductive film. Subsequently, a second conductive film 122 containing aluminum (Al) or copper (Cu) as a main component was formed to a thickness of 100 to 300 nm (FIG. 1C). A wiring 123 made of a second conductive film was formed in a region where wiring from the input / output terminals to the input / output of the driver circuit was formed. For example, if Al is used for the second conductive film, it can be etched with selectivity with the underlying TaN by the phosphoric acid solution. Further, a third conductive film 124 is formed over the first conductive layer 121 and the wiring 123 with a conductive material mainly containing an element selected from Ta, Ti, Mo, and W to a thickness of 100 to 400 nm. did. For example, Ta may be formed to a thickness of 200 nm (FIG. 1C).
[0030]
(Formation of gate electrode (p-ch), wiring electrode and B doping)
Resist masks 125 to 130 are formed, a part of the first conductive film and the third conductive film is removed by etching, wiring 131 from the input / output terminal to the input / output of the driver circuit, and the gate electrode of the p-channel TFT 132, a gate wiring 135 in the driving circuit and a gate wiring 136 in the pixel matrix circuit were formed. The wiring 131 was completed with a clad type structure in which the second conductive film (Al) was covered with the first conductive film (TaN) and the third conductive film (Ta). With such a structure, it was possible to reduce the wiring resistance and at the same time improve the heat resistance. Since the gate electrode of the n-channel TFT is formed in a later step, the first conductive film and the third conductive film are left over the entire surface of the semiconductor layers 104 to 106. Then, a step of adding an impurity element imparting p-type to a part of the semiconductor layer 103 where the p-channel TFT is formed is performed by leaving the resist masks 125 to 130 as they are. Here, boron is used as the impurity element and diborane (B ₂ H ₆ ) Using an ion doping method. Here 2 × 10 ²⁰ atoms / cm ^Three Boron was added to a concentration of. Then, as shown in FIG. 2A, fourth impurity regions 138 and 139 to which boron is added at a high concentration are formed. In this step, part of the gate insulating film 107 is removed by etching using the resist masks 125 to 130 to expose part of the island-shaped semiconductor layer 103, and then an impurity element imparting p-type conductivity is formed. You may perform the process of adding.
[0031]
(Formation of gate electrode (n-ch))
Resist masks 140 to 145 were formed, and n-channel TFT gate electrodes 146 to 148 were formed. At this time, the gate electrodes 146 to 148 were formed so as to partially overlap the low-concentration impurity regions 112 to 120 (FIG. 2B).
[0032]
(P-doping process)
Resist masks 149 to 154 were formed, and a step of forming a first impurity region functioning as a source region or a drain region in the n-channel TFT was performed. The resist masks 151 and 154 are formed so as to cover the gate electrodes 146 and 148 of the n-channel TFT and a part of the second impurity regions 112, 117 and 120. This was for forming a third impurity region to be an offset LDD region. Then, an impurity element imparting n-type conductivity is added to form a first impurity region, and first impurity regions 156, 157, and 192 serving as source regions and first impurity regions 155 and 158 serving as drain regions are formed. , 160 was formed. Again, phosphine (PH _Three The concentration of phosphorus in this region is higher than that in the step of adding the first impurity element imparting n-type, and is 1 × 10 ¹⁹ ~ 1x10 ^{twenty one} atoms / cm ^Three Is preferred, here 1 × 10 ²⁰ atoms / cm ^Three It was. Further, part of the gate insulating film 107 is removed by etching using the resist masks 149 to 154 to expose part of the island-shaped semiconductor layers 104 to 106, and then an impurity element imparting n-type conductivity is added. These steps may be performed (FIG. 2C).
[0033]
(Thermal activation process)
A first interlayer insulating film 161 was formed on the entire surface of the gate insulating film and the gate electrode (also on the upper surface when part of the island-shaped semiconductor layers 103 to 106 is exposed). The first interlayer insulating film may be formed using a silicon nitride film, a silicon oxide film, or a silicon nitride oxide film. Alternatively, a two-layer structure of a silicon nitride film and a silicon oxide film or a silicon nitride oxide film may be used (not shown). In any case, the first interlayer insulating film may be formed to a thickness of 500 to 1000 nm. Thereafter, a heat treatment step for activating the impurity element imparting n-type or p-type added at each concentration was performed. This step can be performed by a thermal annealing method using an electric heating furnace or a rapid thermal annealing method (RTA method) using a halogen lamp. Here, the activation process was performed by thermal annealing. The heat treatment was performed in a nitrogen atmosphere at 300 to 700 ° C., preferably 350 to 550 ° C., here 500 ° C. for 2 hours. Further, a heat treatment was performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen to perform a step of hydrogenating the island-shaped semiconductor layer. In this step, a plasma hydrogenation method may be used, and heat treatment at 200 to 450 ° C. may be performed in a hydrogen atmosphere generated by being converted to plasma (FIG. 3A).
[0034]
(Formation of source / drain electrodes and interlayer insulation film)
Thereafter, contact holes reaching the source region and the drain region of each TFT were formed in the first interlayer insulating film 161. Then, source electrodes 162, 165, 166, 168 and drain electrodes 163, 164, 167, 169 were formed. Although not shown, in this embodiment, this electrode was used as an electrode having a three-layer structure in which a Ti film was formed continuously by 100 nm, an Al film containing Ti having a thickness of 300 nm, and a Ti film having a thickness of 150 nm were formed by sputtering. At the same time, a wiring 200 from the input / output terminal to the input / output of the driving circuit, a source wiring 198 in the driving circuit, and a source wiring 199 in the pixel matrix circuit are formed. Then, a passivation film 170 was formed on the first interlayer insulating film, the source electrode, the drain electrode, and the respective wiring electrodes. The passivation film 170 is formed of a silicon nitride film, a silicon oxide film, or a silicon nitride oxide film with a thickness of 50 to 500 nm. Performing the hydrogenation treatment in this state was preferable for improving the characteristics of the TFT. For example, it is good if heat treatment is performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen, and a hydrogen atmosphere generated by being plasmatized using a plasma hydrogenation method. Among them, a heat treatment at 200 to 450 ° C. may be performed. Thereafter, a part of the passivation film on the drain electrode 169 was removed to form a contact hole, and a second interlayer insulating film 210 made of an organic resin was formed to a thickness of about 1000 nm. As the organic resin film, polyimide, acrylic, polyimide amide, or the like can be used. Advantages of using the organic resin film are that the film forming method is simple, the relative dielectric constant is low, the parasitic capacitance can be reduced, and the flatness is excellent. Organic resin films other than those described above can also be used. Here, it was formed by baking at 300 ° C. using a type of polyimide that is thermally polymerized after being applied to the substrate.
[0035]
(Formation of storage capacitor and pixel electrode)
A step of forming a light shielding film 171 on the second interlayer insulating film was performed. The light shielding film 171 was formed of a film containing an element selected from Ti, Al, Cr, Ta, and W as a main component. A dielectric film 172 having a thickness of 50 to 200 nm was formed on the light shielding film 171 and the second interlayer insulating film. The dielectric film 172 may be formed of an inorganic insulating film such as a silicon oxide film or a silicon nitride film. However, in order to form a dielectric film having no pinhole, it is formed of an organic insulating film mainly composed of polyimide. It was better to do. For example, when polyimide is used, the dielectric constant is 3.0 to 3.8 (1 kHz), and the volume resistivity is 7 × 10. ¹⁵ ~ 1x10 ¹⁷ It was possible to use the liquid crystal alignment film material of Ωcm as it was. Such a polyimide film could be formed by letterpress printing or spin coating. However, when the viscosity of the solution was as low as 25 to 35 cp, it was necessary to perform overcoating to increase the film thickness of the dielectric. Then, the drain electrode 169 is reached by the opening 223 provided in the dielectric film 172, the opening 221 provided in the second interlayer insulating film 210, and the opening 220 provided in the passivation film 170. A contact hole was formed, and a pixel electrode 173 was formed. The pixel electrode 173 may be a transparent conductive film in the case of a transmissive liquid crystal display device, and a metal film in the case of a reflective liquid crystal display device. Here, in order to obtain a transmissive liquid crystal display device, an indium tin oxide (ITO) film was formed to a thickness of 100 nm by sputtering. The pixel electrode 173 is formed to extend over the light shielding film 171 through the dielectric film 172, and a storage capacitor is formed in a region where the pixel electrode 173 overlaps the light shielding film 171 (FIG. 3B).
[0036]
Through the above steps, an active matrix substrate in which a pixel matrix circuit and TFTs of driving circuits provided around the pixel matrix circuit are formed on the same substrate was manufactured.
[0037]
In the p-channel TFT 201 of the CMOS circuit, a channel formation region 174 and fourth impurity regions 175 and 176 are formed. The fourth impurity region 175 is a source region, and the fourth impurity region 176 is a drain region.
[0038]
The n-channel TFT 202 includes a channel formation region 177, first impurity regions 178 and 179, second impurity regions 180 and 181a that overlap with the gate electrode through the gate insulating film, and a third impurity region that does not overlap with the gate electrode. 181b was formed. The first impurity region 178 functions as a source region, and the first impurity region 179 functions as a drain region.
[0039]
In the n-channel TFT 203, a plurality of channel formation regions 182 and 183, first impurity regions 184 and 188, and a plurality of second impurity regions 185 to 187 which overlap with the gate electrode through the gate insulating film are formed. The first impurity region 184 functioned as a source region, and the first impurity region 188 functioned as a drain region.
[0040]
The n-channel TFT 204 of the pixel matrix circuit includes a plurality of channel formation regions 189 to 191, first impurity regions 192 and 197, a plurality of second impurity regions 193 a overlapping with the gate electrode through a gate insulating film, 194, 195, and 196a and third impurity regions 193b and 196b that do not overlap with the gate electrode are formed.
[0041]
In the present invention, in consideration of the driving voltages of the n-channel TFTs of the pixel matrix circuit and the CMOS circuit, the lengths in the channel length direction of the second impurity region and the third impurity region serving as the LDD regions are the same substrate. It was easy to make the above different, and an optimum shape could be made for the TFTs constituting each circuit.
[0042]
The n-channel TFT 202 in FIG. 3B has a single gate structure and is suitable for a shift register circuit or the like with a driving voltage of about 10V. A third impurity region 181b serving as an offset LDD region is provided only on the drain side. The length (Loff) of this region may be 0.5 to 3.0 μm, typically 1.5 μm. Further, the LDD regions (second impurity regions) 181a and 180 that overlap with the gate electrode have a length (Lov) of 1.0 when the length of the channel formation region is 3.0 to 4.0 μm. ˜3.0 μm, preferably 1.5 to 2.5 μm.
[0043]
The n-channel TFT 203 has a structure (single gate / multi-channel structure) in which a plurality of channel formation regions corresponding to one gate electrode are provided and divided by a plurality of second impurity regions forming an LDD region. Is formed. Such a TFT is suitable for a level shifter circuit, a buffer circuit, and the like that require a high driving voltage and a high current driving capability. Therefore, the offset LDD region (third impurity region) is not provided, and when the length of the channel formation region is 3.0 to 4.0 μm, the LDD region (second impurity region) overlapping the gate electrode ) The length (Lov) of 185 to 187 may be 0.5 to 3.0 μm, preferably 1.0 to 20 μm.
[0044]
Similarly, the n-channel TFT 204 of the pixel matrix circuit has a single gate / multi-channel structure. However, since the polarity is inverted, the third impurity regions 193b and 196b serving as offset LDD regions are formed on both the source side and the drain side. Is provided. The length (Loff) of this region may be 0.5 to 3.5 μm, typically 2.0 μm. In addition, the LDD regions (second impurity regions) 193a, 194, 195, and 196a overlapping with the gate electrode have channel lengths of 189, 190, and 191 of 1.0 to 3.0 μm, preferably In the case of 2.5 μm, the length (Lov) may be 1.0 to 3.0 μm, preferably 1.5 to 2.5 μm.
[0045]
In this way, in a single-gate / multi-channel TFT in which a plurality of channel formation regions are divided by a low-concentration impurity region serving as an LDD region with respect to one gate electrode, it corresponds to one gate electrode. The number of the channel formation region and the second impurity region may be appropriately determined by a practitioner in consideration of target TFT characteristics. With such a configuration, the breakdown voltage of the TFT could be increased as in the conventional multi-gate / multi-channel structure.
[0046]
[Embodiment 2]
In this embodiment, a process of manufacturing an active matrix liquid crystal display device from an active matrix substrate will be described. As shown in FIG. 4, an alignment film 401 is formed on the surface of the dielectric film 172 and the pixel electrode 173 on the substrate in the state of FIG. Usually, a polyimide resin is often used for the alignment film of the liquid crystal display element. A transparent conductive film 403 and an alignment film 404 were formed on the opposite substrate 402. After the alignment film was formed, it was rubbed so that the liquid crystal molecules were aligned in parallel with a certain pretilt angle. Then, the pixel matrix circuit, the active matrix substrate on which the CMOS circuit is formed, and the counter substrate are bonded to each other through a sealing material, a spacer (both not shown), or the like by a known cell assembling process. Thereafter, a liquid crystal material 1508 was injected between both substrates and completely sealed with a sealant (not shown). Thus, the active matrix liquid crystal display device shown in FIG. 15 was completed.
[0047]
Next, the configuration of the active matrix liquid crystal display device will be described with reference to the perspective view of FIG. 5 and the top view of FIG. 5 and 6 use the same reference numerals in order to correspond to the cross-sectional structure diagrams of FIGS. 1 to 4. The active matrix substrate includes a pixel matrix circuit 501, a scanning (gate) line driving circuit 502, and a signal (source) line driving circuit 503 formed on the glass substrate 101. The pixel TFT 204 of the pixel matrix circuit is an n-channel TFT, and a driving circuit provided in the periphery is configured based on a CMOS circuit. The scanning (gate) line driving circuit 502 and the signal (source) line driving circuit 503 are connected to the pixel matrix circuit 501 by a gate wiring 148 and a source wiring 199, respectively. Further, wirings 149 and 200 from the external input / output terminal 534 to which the FPC 531 is connected to the input / output terminal of the driving circuit are provided.
[0048]
FIG. 6 is a top view showing a part of the pixel matrix circuit 501. A gate electrode 148 formed continuously with the gate wiring 136 intersects the underlying semiconductor layer 106 through a gate insulating film (not shown). Although not illustrated, a source region, a drain region, a second impurity region, and a third impurity region are formed in the semiconductor layer 106. Further, a storage capacitor is formed on the pixel TFT from a light shielding film 171, a dielectric film (not shown), and a pixel electrode 173. A plurality of channel formation regions and low-concentration impurity regions serving as a plurality of LDD regions are continuously formed by the single-gate / multi-channel TFTs of the present invention, so that the pixel TFTs can be made compact and the source line contact 251 is formed. A drain line contact 252 and an ITO contact 253 are formed on the pixel TFT. Thus, the aperture ratio can be improved by providing the area necessary for contact formation on the pixel TFT. The cross-sectional structure along AA ′ shown in FIG. 6 corresponds to the cross-sectional view along AA ′ of the pixel matrix circuit shown in FIG.
[0049]
【Example】
[Example 1]
In this embodiment, a manufacturing method of an active matrix substrate in which a pixel matrix circuit and a CMOS circuit which is a basic form of a driver circuit provided around the pixel matrix circuit are simultaneously formed will be described with reference to FIGS. First, a silicon nitride oxide film 1102a having a nitrogen content higher than the oxygen content is formed as a first insulating layer over the substrate 1101 to a thickness of 50 to 500 nm, typically 100 nm, and silicon nitride oxide is further formed. The film 302b was formed to a thickness of 100 to 500 nm, typically 200 nm. The silicon nitride oxide film 1102a is made of SiH. _Four And N ₂ O and NH _Three The concentration of nitrogen contained was made 25 atomic% or more and less than 50 atomic%. Further, island-shaped crystalline semiconductor films 1103, 1104, and 1105 and a gate insulating film 1106 were formed. The island-shaped crystalline semiconductor film is formed by forming a crystalline semiconductor film from an amorphous semiconductor film by a crystallization method using a catalytic element and separating it into islands. The gate insulating film 1106 is made of SiH _Four And N ₂ A silicon oxynitride film formed from O, which is formed to have a thickness of 10 to 200 nm, preferably 50 to 150 nm. (Fig. 11 (A))
[0050]
Next, resist masks 1107 to 1110 covering the island-shaped semiconductor film 1103 and the channel formation regions of the island-shaped semiconductor films 1104 and 1105 were formed. At this time, a resist mask 1109 may be formed also in a region where a wiring is formed. And phosphine (PH _Three The second impurity region was formed by adding an impurity element imparting n-type by an ion doping method using the above. In this step, the acceleration voltage was set to 65 keV in order to add phosphorus through the gate insulating film 1106 to the underlying island-like semiconductor film. The concentration of phosphorus added to the island-shaped semiconductor is 1 × 10 ¹⁶ ~ 1x10 ¹⁹ atoms / cm ^Three In the range of 1 × 10 ¹⁸ atoms / cm ^Three It was. Then, regions 1111 to 1116 to which phosphorus was added were formed. Part of this region is a second impurity region that functions as an LDD region. (Fig. 11 (B))
[0051]
Thereafter, the resist mask is removed, and a tantalum nitride (TaN) film 1117 is formed to a thickness of 10 to 50 nm and a tantalum (Ta) film 1118 is formed to a thickness of 100 to 300 nm by sputtering to form a gate electrode. Formed. Here, Ta was formed by sputtering using a mixed gas of Ar and Xe. (Fig. 11 (C))
[0052]
Next, resist masks 1119 to 1122 were formed, and a gate electrode of a p-channel TFT, a gate wiring of a CMOS circuit and a pixel matrix circuit, and a gate bus line were formed. Unnecessary portions of the TaN film 1117 and the Ta film 1118 were removed by a dry etching method. Etching of TaN film and Ta film is CF _Four And O ₂ The mixed gas was used. Then, a gate electrode 1123 of a p-channel TFT, a gate wiring 1125, and gate bus lines 1126 and 1127 were formed. Then, a process of adding a fourth impurity element imparting p-type to a part of the island-shaped semiconductor film 1103 where the p-channel TFT is formed is performed with the resist masks 1119 to 1122 left as they are. Here, boron is used as the impurity element and diborane (B ₂ H ₆ ) Using an ion doping method. The boron concentration in this region is 2 × 10 ²⁰ atoms / cm ^Three It was. Then, as shown in FIG. 12A, third impurity regions 1129 and 1130 to which boron is added at a high concentration are formed.
[0053]
After removing the resist mask provided in FIG. 12A, resist masks 1131 to 1134 were newly formed. This is for forming gate electrodes of n-channel TFTs, and gate electrodes 1135 and 1136 of n-channel TFTs were formed by dry etching. At this time, the gate electrodes 1135 and 1136 were formed so as to overlap with part of the second impurity regions 1111 to 1116. (Fig. 12 (B))
[0054]
Then, new resist masks 1137 to 1140 were formed. The resist masks 1138 and 1140 are formed so as to cover the gate electrodes 1135 and 1136 of the n-channel TFT and a part of the second impurity region, and the offset amount of the LDD region is determined. Then, a step of forming a first impurity region by adding an impurity element imparting n-type conductivity is performed, and the first impurity regions 1144 and 1145 serving as the source region of the n-channel TFT and the first impurity region serving as the drain region are performed. Impurity regions 1143 and 1146 were formed. In addition, regions 1141 and 1142 to which phosphorus is added are also formed in part of the island-shaped semiconductor layer 1103 where the p-channel TFT is formed. However, the phosphorus concentration in this region was about ½ of the boron concentration, and the conductivity type remained p-type. (Fig. 4 (C))
[0055]
When the steps up to FIG. 12C are completed, a first interlayer insulating film 1147 is formed of a silicon nitride oxide film using SiH4, N2O, and NH3 as raw materials by a plasma CVD method. It is desirable that the concentration of hydrogen contained in the silicon oxynitride film is 1 to 30 atomic%. Thereafter, heat treatment was performed in this state in a nitrogen atmosphere at 400 to 800 ° C. for 1 to 12 hours, for example, at 525 ° C. for 8 hours. The impurity element imparting n-type and p-type added by this step could be activated. Further, the regions 1141 to 1146 to which phosphorus was added became gettering sites, and the catalyst elements remaining in the crystallization process could be segregated in this region. As a result, the catalyst element could be removed at least from the channel formation region.
[0056]
A hydrogenation step was performed after this heat treatment. Here, the hydrogenation process may be performed in a 3 to 100% hydrogen atmosphere at 300 to 500 ° C., preferably 350 to 450 ° C. for 2 to 12 hours. Alternatively, the hydrogenation treatment may be performed with hydrogen generated by plasma formation at a substrate temperature of 200 to 500 ° C., preferably 300 to 450 ° C. (FIG. 13 (A))
[0057]
Thereafter, a predetermined resist mask was formed on the first insulating film 1147, and contact holes reaching the source region and the drain region of each TFT were formed by an etching process. Then, source electrodes 1149, 1150, and 1151 and drain electrodes 1152 and 1153 were formed. Although not shown, in this embodiment, this electrode was used as an electrode having a three-layer structure in which a Ti film was formed continuously by 100 nm, an Al film containing Ti having a thickness of 300 nm, and a Ti film having a thickness of 150 nm were formed by sputtering.
[0058]
Then, a passivation film 1154 was formed thereon. The passivation film is SiH by plasma CVD. _Four , N ₂ O, NH _Three A silicon oxynitride film formed from SiH or SiH _Four , N ₂ , NH _Three It may be formed of a silicon nitride film manufactured from the above. First, prior to film formation, N ₂ O, N ₂ , NH _Three Etc. were introduced to carry out the hydrogenation step by plasma hydrogenation. Hydrogen generated in the gas phase by being converted into plasma is supplied into the first interlayer insulating film, and if the substrate is heated to 200 to 400 ° C., the hydrogen is diffused also to the lower layer side to form a semiconductor. The layer could be hydrogenated. The conditions for producing this passivation film are not particularly limited, but a dense film is desirable. In addition, after the passivation film is formed, the hydrogenation process may be performed at 300 to 550 ° C. in an atmosphere containing hydrogen or nitrogen for 1 to 12 hours.
[0059]
Thereafter, a part of the passivation film on the drain electrode 1153 was removed to form a contact hole, and a second interlayer insulating film 1155 made of an organic resin was formed to a thickness of about 1000 nm. As the organic resin film, polyimide, acrylic, polyimide amide, or the like can be used. Advantages of using the organic resin film are that the film forming method is simple, the relative dielectric constant is low, the parasitic capacitance can be reduced, and the flatness is excellent. Organic resin films other than those described above can also be used. Here, it was formed by baking at 300 ° C. using a type of polyimide that is thermally polymerized after being applied to the substrate.
[0060]
A step of forming a light shielding film 1156 made of a Ti film on the second interlayer insulating film was performed. Then, a dielectric film 1157 made of a polyimide film was formed to a thickness of 50 to 200 nm on the light shielding film 1156 and the second interlayer insulating film 1155 in the same manner as in the first embodiment. The drain electrode 1153 includes an opening 1182 provided in the dielectric film 1157, an opening 1181 provided in the second interlayer insulating film 1155, and an opening 1180 provided in the passivation film 1154. A contact hole reaching to is formed, and a pixel electrode 1158 is formed. For the pixel electrode 1158, a transparent conductive film may be used for a transmissive liquid crystal display device, and a metal film may be used for a reflective liquid crystal display device. Here, in order to obtain a transmissive liquid crystal display device, an indium tin oxide (ITO) film was formed to a thickness of 100 nm by sputtering. The pixel electrode 1158 is formed to extend over the light shielding film 1156 through the dielectric film 1157, and a storage capacitor is formed in a region where the pixel electrode 1158 overlaps the light shielding film 1156. Through the above steps, an active matrix substrate in which a pixel matrix circuit and TFTs of driving circuits provided around the pixel matrix circuit are formed on the same substrate was manufactured. The pixel matrix circuit has a structure in which a storage capacitor 1304 is connected to an n-channel TFT 1303. (Fig. 13B)
[0061]
The p-channel TFT was formed in a self-aligned manner (self-alignment), and the n-channel TFT was formed in a non-self-aligned manner (non-self-aligned). A channel formation region 1159 and fourth impurity regions 1160 and 1161 are formed in the p-channel TFT 1301 of the CMOS circuit. In the fourth impurity region, regions 1160a and 1161a to which boron (B) is added are in contact with the channel formation region, and regions to which boron (B) and phosphorus (P) are added that are not in contact with the channel formation region 1160b and 1161b. The fourth impurity region 1160 serves as a source region, and the fourth impurity region 1161 serves as a drain region. On the other hand, the n-channel TFT 1302 includes a channel formation region 1162, first impurity regions 1165 and 1166, second impurity regions 1163a and 1164a that overlap with the gate electrode through the gate insulating film, and a third region that does not overlap with the gate electrode. Impurity regions 1163b and 1164b were formed. The first impurity region 1165 functions as a source region, and the first impurity region 1166 functions as a drain region. The n-channel TFT 1303 of the pixel matrix circuit includes a plurality of channel formation regions 1167 to 1169, first impurity regions 1174 and 1175, and a plurality of second impurity regions 1170a overlapping with the gate electrode with the gate insulating film interposed therebetween. 1171, 1172, and 1173a and third impurity regions 1170b and 1173b that do not overlap with the gate electrode were formed.
[0062]
[Example 2]
In this embodiment, a configuration of a storage capacitor connected to a pixel TFT of an active matrix substrate will be described. FIG. 14 shows a cross-sectional structure diagram of an active matrix substrate manufactured in the same manner as in the first embodiment. A storage capacitor 1413 connected to the pixel TFT 1412 is formed of a light shielding film 1402 formed on the second interlayer insulating film, a dielectric film 1404 formed on the light shielding film 1402, and a pixel electrode 1405. . An insulating spacer 1403 is provided over the second interlayer insulating film, and is provided in the opening 1406 provided in the passivation film 1400, the opening 1407 provided in the second interlayer insulating film, and the spacer 1403. In addition, the pixel electrode 1405 is connected to the drain electrode 1415 through an opening 1409 provided in the dielectric film 1404.
[0063]
An organic resin material is preferably used for the dielectric film 1404 as in the first embodiment. As another method for forming the dielectric film, the light shielding film 1402 may be formed of an Al film and the surface thereof may be anodized. Since the dielectric constant of the anodic oxide film of Al is 7 to 8, a sufficient capacity can be produced.
[0064]
[Example 3]
In this embodiment, another structure of the storage capacitor connected to the pixel TFT of the active matrix substrate will be described. FIG. 15 is a sectional view of an active matrix substrate manufactured in the same manner as in Example 1. A storage capacitor 1513 connected to the pixel TFT 1512 includes a transparent conductive film 1502 formed on the second interlayer insulating film 1501, a dielectric film 1504 formed on the transparent conductive film 1502, and a pixel formed of the transparent conductive film. The electrode 1505 is formed. With such a configuration, the light transmittance of the pixel matrix circuit portion can be improved. Further, an insulating spacer 1503 is provided over the second interlayer insulating film 1501, and an opening 1506 provided in the passivation film 1500, an opening 1507 provided in the second interlayer insulating film, and a spacer 1503 are provided. The pixel electrode 1505 is connected to the drain electrode 1515 through the aperture 1509 provided in the dielectric film 1504.
[0065]
[Example 4]
The procedure for manufacturing the TFT of the present invention is not limited to the order of steps in Embodiment Mode 1 and Example 1, and can be manufactured in the order of other steps. For example, as a procedure for fabricating a p-channel TFT in a self-aligned manner and an n-channel TFT in a non-self-aligned manner, formation of an island-like semiconductor layer and a gate insulating film, formation of a low-concentration impurity region, a gate electrode and a wiring electrode Film formation, gate electrode (n-channel TFT) formation, P-doping process, gate electrode (p-channel TFT) formation and B-doping process, activation process, source / drain electrodes and interlayer insulation It is also possible to form a film, a storage capacitor and a pixel electrode.
[0066]
Further, if the p-channel TFT is not manufactured in a self-aligned manner and the n-channel TFT is not manufactured in a non-self-aligned manner, after the island-like semiconductor layer and the gate insulating film are formed, a B doping step, a low concentration impurity The formation of the region and the P doping step may be performed, or the B doping step, the P doping step, and the low concentration impurity region may be formed. Further, after the island-shaped semiconductor layer and the gate insulating film are formed, a P doping step, formation of a low concentration impurity region, and a B doping step may be performed, or a P doping step, a B doping step, and a low concentration impurity region may be performed. It is also possible to form.
[0067]
[Example 5]
In this embodiment, a method for manufacturing a semiconductor layer which can be applied to the present invention will be described. In FIG. 7, a glass substrate, a ceramic substrate, a quartz substrate, or the like can be used as the substrate 701. Alternatively, a silicon substrate on which an insulating film such as a silicon oxide film or a silicon nitride film is formed or a metal substrate typified by stainless steel may be used. In the case of using a glass substrate, it is desirable to perform heat treatment in advance at a temperature below the strain point. For example, in the case of using a # 1737 substrate manufactured by Corning, heat treatment may be performed at 500 to 650 ° C., preferably 595 to 645 ° C. for 1 to 24 hours.
[0068]
Then, a base film was formed on the main surface of the substrate 701. There is no particular limitation on the material of the base film, but the silicon nitride oxide film 702 is used. In addition, a single layer or a plurality of layers selected from a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, and a tantalum oxide film can be used. When a silicon oxynitride film is used, it may be formed to a thickness of 20 to 100 nm, typically 50 nm. Further, a silicon oxynitride film may be formed on the silicon nitride film to a thickness of 50 to 500 nm, typically 50 to 200 nm. Then, an amorphous semiconductor layer 703 was formed over the first insulating layer. This may be an amorphous semiconductor formed by a film formation method such as a plasma CVD method, a low pressure CVD method, or a sputtering method, and includes silicon (Si), germanium (Ge), a silicon germanium alloy, and silicon carbide. In addition, a compound semiconductor material such as gallium arsenide can be used. The semiconductor layer was formed to a thickness of 10 to 100 nm, typically 50 nm. In addition, the first insulating layer and the amorphous semiconductor layer 2103 can be continuously formed by a plasma CVD method or a sputtering method. After each layer is formed, the surface can be prevented from being contaminated by not touching the air atmosphere. (Fig. 7 (A))
[0069]
Next, a crystallization step was performed. A known laser crystallization technique or thermal crystallization technique may be used for the step of crystallizing the amorphous semiconductor layer. In addition, the amorphous semiconductor layer manufactured by the plasma CVD method contains hydrogen in the film at a rate of 10 to 40 atomic%, and a heat treatment process at 400 to 500 ° C. is performed prior to the crystallization process. It was desirable to desorb hydrogen from the film so that the amount of hydrogen contained was 5 atomic% or less (FIG. 7B). Then, an island-shaped crystalline semiconductor layer 705 was formed from the crystalline semiconductor layer 704, and a gate insulating film 705 was further formed. The gate insulating film 705 may be formed using a material such as a silicon nitride film, a silicon oxide film, or a silicon nitride oxide film. The gate insulating film 705 may be formed with a thickness of 10 to 1000 nm, preferably 50 to 400 nm. (Fig. 7 (C))
[0070]
In FIG. 8, a base film 802 made of a silicon oxynitride film is formed on the main surface of the substrate 801, and an amorphous semiconductor layer 803 is formed on the surface similarly to FIG. The thickness of the amorphous semiconductor layer may be 10 to 200 nm, preferably 30 to 100 nm. Further, an aqueous solution containing 10 ppm of the catalyst element in terms of weight was applied by a spin coating method to form the catalyst element-containing layer 804 over the entire surface of the amorphous semiconductor layer 803. In addition to nickel (Ni), usable catalyst elements include germanium (Ge), iron (Fe), palladium (Pd), tin (Sn), lead (Pb), cobalt (Co), platinum ( Pt), copper (Cu), gold (Au), and the like. The internal stress of the amorphous semiconductor layer was not uniformly determined by the manufacturing conditions. However, it was necessary to desorb hydrogen from the film by performing a heat treatment step at 400 to 600 ° C. prior to the crystallization step (FIG. 8A). Then, heat treatment was performed at 500 to 600 ° C. for 4 to 12 hours, for example, at 550 ° C. for 8 hours, so that the crystalline semiconductor layer 805 was formed. (Fig. 8 (B))
[0071]
Next, a step of removing the catalyst element used in the crystallization step from the crystalline semiconductor film was performed. As the method, the technique described in JP-A-10-135468 or JP-A-10-135469 is used here. The technique described in the publication is a technique for removing using the gettering action of phosphorus. By this gettering step, the concentration of the catalytic element in the crystalline semiconductor film is reduced to 1 × 10. ¹⁷ atms / cm ^Three Or less, preferably 1 × 10 ¹⁶ atms / cm ^Three It was possible to reduce to. First, a mask insulating film 806 was formed to a thickness of 150 nm on the surface of the crystalline semiconductor layer 805, an opening 807 was provided by patterning, and a region where the crystalline semiconductor layer was exposed was provided. Then, a step of adding phosphorus was performed to provide a phosphorus-containing region 808 in the crystalline semiconductor layer (FIG. 8C). In this state, when heat treatment is performed in a nitrogen atmosphere at 550 to 800 ° C. for 5 to 24 hours, for example, 600 ° C. for 12 hours, the phosphorus-containing region 808 functions as a gettering site and remains in the crystalline semiconductor layer 805. The catalyst element was segregated in the phosphorus-containing region 808 (FIG. 8D). Then, the mask insulating film 806 and the phosphorus-containing region 808 are removed by etching, so that the concentration of the catalytic element used in the crystallization process is 1 × 10. ¹⁷ atms / cm ^Three A crystalline semiconductor layer reduced to the following could be obtained. Then, a gate insulating film 810 was formed in close contact with the crystalline semiconductor layer 809 (FIG. 8E).
[0072]
In FIG. 9, a base film 901 and an amorphous semiconductor layer 902 are formed in this order over a substrate 901, and a silicon oxide film 904 is formed on the surface of the amorphous semiconductor layer 902. At this time, the thickness of the silicon oxide film 904 was 150 nm. Further, the silicon oxide film 904 was patterned to selectively form openings 905, and then an aqueous solution containing 10 ppm catalyst element in terms of weight was applied. Thereby, the catalyst element containing layer 906 was formed. The catalyst-containing layer 906 was in contact with the amorphous semiconductor layer 903 only through the opening 905 (FIG. 9A). Next, heat treatment was performed at 500 to 650 ° C. for 4 to 24 hours, for example, 570 ° C. for 14 hours, so that the crystalline semiconductor layer 907 was formed. In this crystallization process, the region of the amorphous semiconductor layer in contact with the catalytic element was first crystallized, and the crystallization proceeded laterally therefrom. The crystalline semiconductor layer 907 thus formed is a collection of rod-like or needle-like crystals, and each crystal grows with a specific direction as viewed macroscopically, so that the crystallinity is uniform. (FIG. 9B).
[0073]
Next, similarly to FIG. 8, a step of removing the catalyst element used in the crystallization step from the crystalline semiconductor film was performed. A step of adding phosphorus was performed on the substrate in the same state as in FIG. 9B to provide a phosphorus-containing region 909 in the crystalline semiconductor layer. The phosphorus content in this region is 1 × 10 ¹⁹ ~ 1x10 ^{twenty one} / Cm ^Three (FIG. 9C). In this state, when heat treatment is performed in a nitrogen atmosphere at 550 to 800 ° C. for 5 to 24 hours, for example, 600 ° C. for 12 hours, the phosphorus-containing region 909 functions as a gettering site and remains in the crystalline semiconductor layer 907. The catalyst element was segregated in the phosphorus-containing region 909 (FIG. 9D).
[0074]
Then, the oxide film for mask and the phosphorus-containing region 909 were removed by etching, so that an island-shaped crystalline semiconductor layer 910 was formed. Then, a gate insulating film 911 was formed in close contact with the crystalline semiconductor layer 910. The gate insulating film 911 is formed of one layer or a plurality of layers selected from a silicon oxide film and a silicon nitride oxide film. The thickness may be 10 to 100 nm, preferably 50 to 80 nm. Then, heat treatment was performed in an atmosphere containing halogen (typically chlorine) and oxygen. For example, 950 ° C. and 30 minutes were set. The treatment temperature may be selected in the range of 700 to 1100 ° C., and the treatment time may be selected between 10 minutes and 8 hours. As a result, a thermal oxide film was formed at the interface between the crystalline semiconductor layer 910 and the second insulating layer 911, and a favorable interface with a low interface state density could be formed. (FIG. 9E).
[0075]
Further, in FIG. 10, after forming the first insulating layer 1002 and the crystalline semiconductor layer 1005 as in FIG. 8, the catalyst element remaining in the crystalline semiconductor layer 1005 can be gettered in the liquid phase. . For example, gettering can be performed by using sulfuric acid as a solution and dipping the substrate in FIG. 10B in a sulfuric acid solution heated to 300 to 500 ° C. In the crystalline semiconductor layer 1005 The remaining catalytic element could be removed. In addition, a nitric acid solution, an aqua regia solution, or a tin solution may be used. After that, an island-shaped semiconductor layer 1009 and a second insulating layer 1010 were formed.
[0076]
[Example 6]
In this embodiment, an example in which the present invention is applied to an active matrix EL display device will be described with reference to FIGS. FIG. 16A is a circuit diagram of an active matrix EL display device. The EL display device includes a display area 11 provided on a substrate 10, an X-direction peripheral drive circuit 12, and a Y-direction peripheral drive circuit 13. The display area 11 is composed of a switching TFT 14, a capacitor 15, a current control TFT 16, an organic EL element 17, X-direction signal lines 18a and 18b, power supply lines 19a and 19b, Y-direction signal lines 20a, 20b, and 20c. The
[0077]
FIG. 16B is a partial cross-sectional view of the display region 11 of the active matrix EL display device. Here, a part of the current control TFT 16 and the organic EL element 17 are shown. The current control TFT 16 is an n-channel TFT and is manufactured in the same manner as in the first embodiment. Then, the organic EL element 17 is provided by removing the insulating film in the region where the TFT is not formed. The organic EL element includes a transparent electrode 21 made of ITO or the like, an organic EL layer 23 formed on the transparent electrode, an upper electrode 24, and the like. An interlayer insulating film 25 is formed so as to cover the current control TFT 16, and a common electrode 26 is provided on and in contact with the upper electrode 24. The electrode 22b is provided to electrically connect the drain electrode of the current control TFT and the transparent electrode 21. The electrode 22a is provided in order to maintain the adhesion between the electrode 22b and the transparent electrode 21.
[0078]
In this embodiment, the organic EL element 17 is provided in contact with the substrate 10. However, the structure is not limited to this structure. For example, the organic EL element 17 is disposed above the TFT via an interlayer insulating film. It is good also as a structure which provides.
[0079]
[Example 7]
In this embodiment, a semiconductor device incorporating an active matrix liquid crystal display device using a TFT circuit of the present invention will be described with reference to FIG.
[0080]
Examples of such a semiconductor device include a portable information terminal (electronic notebook, mobile computer, mobile phone, etc.), a video camera, a still camera, a personal computer, a television, and the like. An example of them is shown in FIG.
[0081]
FIG. 17A illustrates a mobile phone, which includes a main body 9001, an audio output portion 9002, an audio input portion 9003, a display device 9004, operation switches 9005, and an antenna 9006. The present invention can be applied to a display device 9004 including an audio output unit 9002, an audio input unit 9003, and an active matrix substrate.
[0082]
FIG. 17B illustrates a video camera which includes a main body 9101, a display device 9102, an audio input portion 9103, operation switches 9104, a battery 9105, and an image receiving portion 9106. The present invention can be applied to the audio input portion 9103, the display device 9102 including the active matrix substrate, and the image receiving portion 9106.
[0083]
FIG. 17C illustrates a mobile computer, which includes a main body 9201, a camera portion 9202, an image receiving portion 9203, operation switches 9204, and a display device 9205. The present invention can be applied to an image receiving portion 9203 and a display device 9205 including an active matrix substrate.
[0084]
FIG. 17D illustrates a head mounted display which includes a main body 9301, a display device 9302, and an arm portion 9303. The present invention can be applied to the display device 9302. Although not shown, it can also be used for other signal control circuits.
[0085]
FIG. 17E illustrates a rear projector, which includes a main body 9401, a light source 9402, a display device 9403, a polarizing beam splitter 9404, reflectors 9405 and 9406, and a screen 9407. The present invention can be applied to the display device 9403.
[0086]
FIG. 17F illustrates a portable book, which includes a main body 9501, display devices 9502 and 9503, a storage medium 9504, an operation switch 9505, and an antenna 9506, and data stored in a minidisc (MD) or DVD, The data received by the antenna is displayed. The display devices 9502 and 9503 are direct-view display devices, and the present invention can be applied to them.
[0087]
Although not shown here, the present invention can also be applied to a display unit of a car navigation system or an image sensor personal computer. Thus, the applicable range of the present invention is extremely wide and can be applied to electronic devices in all fields.
[0088]
【The invention's effect】
According to the present invention, a plurality of channel formation regions, a first impurity region of one conductivity type for forming a source region or a drain region, and one end of the third semiconductor layer are formed in the island-shaped semiconductor layer that is a component of the TFT. A second impurity region of one conductivity type formed in contact with the impurity region and a second impurity region of one conductivity type formed at both ends in contact with the channel formation region; In addition, the plurality of channel formation regions are formed so as to overlap the gate electrode with the gate insulating film interposed therebetween, whereby reliability can be improved. In addition, a TFT of a pixel matrix circuit can be formed with a low off-state current.
[0089]
Further, according to the present invention, a TFT can be formed more compactly than a conventional multi-gate / multi-channel TFT, and a pixel matrix circuit of an active matrix liquid crystal display device can be formed using such a TFT. Then, the aperture ratio can be improved.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view illustrating a manufacturing process of a pixel matrix circuit and a logic circuit.
FIG. 2 is a cross-sectional view illustrating a manufacturing process of a pixel matrix circuit and a logic circuit.
FIG. 3 is a cross-sectional view illustrating a manufacturing process of a pixel matrix circuit and a logic circuit.
FIG. 4 is a cross-sectional view of an active matrix liquid crystal display device.
FIG. 5 is a perspective view of an active matrix liquid crystal display device.
FIG. 6 is a top view of a pixel matrix circuit.
7 is a cross-sectional view illustrating a manufacturing process of a crystalline semiconductor film. FIG.
FIG. 8 is a cross-sectional view illustrating a manufacturing process of a crystalline semiconductor film.
FIG. 9 is a cross-sectional view illustrating a manufacturing process of a crystalline semiconductor film.
FIG. 10 is a cross-sectional view illustrating a manufacturing process of a crystalline semiconductor film.
FIG. 11 is a cross-sectional view illustrating a manufacturing process of a pixel matrix circuit and a driver circuit.
FIG. 12 is a cross-sectional view illustrating a manufacturing process of a pixel matrix circuit and a driver circuit.
FIG. 13 is a cross-sectional view illustrating a manufacturing process of a pixel matrix circuit and a driver circuit.
FIG. 14 is a diagram showing a cross-sectional structure of a storage capacitor.
FIG. 15 is a diagram showing a cross-sectional structure of a storage capacitor.
16A and 16B are a circuit diagram and a cross-sectional structure diagram of an EL display device.
FIG 17 illustrates an example of a semiconductor device.
[Explanation of symbols]
101 .. Board
102..Under film
103 to 106 .. island-like semiconductor layer
131 .. Wiring from input / output terminal to input / output terminal of drive circuit
132, 146, 147, 148 .. gate electrode
135, 136 .. Gate wiring
161..First interlayer insulating film
162, 165, 166, 168 .. Source electrode
163, 164, 167, 169 ..Drain electrode
198, 200 ... Source wiring
170 .. Passivation film
171 ... Light shielding film
172 ・ ・ Dielectric film
173..Pixel electrode
210 .. Second interlayer insulating film

Claims (4)

An insulating film is formed on the substrate,
A pixel matrix circuit and a drive circuit are formed on the insulating film ,
The pixel matrix circuit includes a first n-channel thin film transistor,
The drive circuit includes a second n-channel thin film transistor,
The first n-channel thin film transistor is formed on an island-shaped first semiconductor layer, a first gate insulating film formed on the first semiconductor layer, and the first gate insulating film. A first gate electrode formed,
The first semiconductor layer includes a pair of a region having a first plurality of channels divided by at least one first impurity region and a pair of the first semiconductor layer in contact with both ends of the region having the first plurality of channels. First low concentration impurity region, a first source region formed in contact with one of the first low concentration impurity regions, and a first source region formed in contact with the other of the first low concentration impurity regions. 1 drain region, and
A region having the first plurality of channels; a part of the first low-concentration impurity region in contact with the first source region; and one of the first low-concentration impurity regions in contact with the first drain region. The portion overlaps the first gate electrode through the first gate insulating film,
The at least one first impurity region and the first low-concentration impurity region have the same conductivity type as the first source region and the first drain region, and the first source region and Having a lower concentration of impurities than the first drain region;
The second n-channel thin film transistor is formed on an island-shaped second semiconductor layer, a second gate insulating film formed on the second semiconductor layer, and the second gate insulating film. A second gate electrode formed,
The second semiconductor layer includes a pair of a region having a second plurality of channels divided by at least one second impurity region, and a pair provided in contact with both ends of the region having the second plurality of channels. The second low concentration impurity region, the second source region formed in contact with one of the second low concentration impurity regions, and the second source region formed in contact with the other of the second low concentration impurity regions. Two drain regions,
The region having the second plurality of channels, all of the second low-concentration impurity regions in contact with the second source region, and all of the second low-concentration impurity regions in contact with the second drain region are , Overlapping the second gate electrode through the second gate insulating film,
The at least one second impurity region and the second low-concentration impurity region have the same conductivity type as the second source region and the second drain region, and the second source region and Having a lower concentration of impurities than the second drain region;
The semiconductor device, wherein the second n-channel thin film transistor forms a level shifter circuit or a buffer circuit .   In claim 1,
  The drive circuit includes a third n-channel thin film transistor,
  The third n-channel thin film transistor is formed on an island-shaped third semiconductor layer, a third gate insulating film formed on the third semiconductor layer, and the third gate insulating film. A third gate electrode formed,
  The third semiconductor layer includes a third channel formation region, a pair of third low concentration impurity regions provided in contact with both ends of the third channel formation region, and the third low concentration impurity region. A third source region formed in contact with one of the third drain region and a third drain region formed in contact with the other of the third low-concentration impurity regions,
  The third channel formation region, all of the third low-concentration impurity region in contact with the third source region, and part of the third low-concentration impurity region in contact with the third drain region are It overlaps with the third gate electrode through a third gate insulating film,
  The third low concentration impurity region has the same conductivity type as the third source region and the third drain region, and has a lower concentration than the third source region and the third drain region. A semiconductor device having the following impurities.   In claim 2,
The third n-channel thin film transistor forms a shift register circuit.   In any one of Claims 1 thru | or 3,
  The drive circuit includes a p-channel thin film transistor,
  The p-channel thin film transistor includes an island-shaped fourth semiconductor layer, a fourth gate insulating film formed on the fourth semiconductor layer, and a fourth gate insulating film formed on the fourth gate insulating film. 4 gate electrodes,
  The fourth semiconductor layer has a fourth channel formation region, and a fourth source region and a fourth drain region provided in contact with both ends of the fourth channel formation region,
  The semiconductor device, wherein the fourth channel formation region overlaps the fourth gate electrode with the fourth gate insulating film interposed therebetween.

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