JP4374416B2 - SPI memory access mode automatic discrimination method and discrimination device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for automatically determining an access mode in a serial memory, in particular, an SPI-compliant serial memory.
[0002]
[Prior art]
In recent years, the capacity of a memory mounted on an electronic device such as a portable terminal has been increasing with the progress of semiconductor technology. As is well known, a memory having a serial interface that can easily cope with downsizing is widely used because the number of input / output ports is small.
FIG. 7 is a block diagram of a general serial memory and an access timing chart. As shown in FIG. 2A, the general serial memory 11 has at least four ports of DI (input), Do (output), Cs (chip select), and SK (serial clock). .
The DI port is a port for inputting a write command or a read command and a series of serial data for designating an address, and the Do port is a port for outputting serial data read from the memory.
The Cs port is a port for making the memory accessible. By setting the Cs port to a predetermined level, the memory becomes active, and data can be written or read. .
Further, the SK port is a port for inputting a serial clock. After setting the Cs port to a predetermined level, the serial clock is input, and predetermined writing and reading are performed in synchronization with the clock signal.
[0003]
FIGS. 7B and 7C respectively show timing charts for writing and reading of the serial memory.
As shown in FIG. 4B, when data is written to the serial memory, the Cs port is once set from the Hi level to the Lo level, and the write command, write address and write data are set to the DI port. Input as data.
When the Cs port is returned from the Lo level to the Hi level, writing to the memory is executed in synchronization with the serial clock signal.
On the other hand, as shown in FIG. 5C, when reading data from the memory, the Cs port is set from the Hi level to the Lo level, and the serial clock signal is input to the SK port. When a read command, a read address, and dummy data of the required number of bytes are input to the DI port as a series of serial data, data corresponding to the read address is output from the Do port in synchronization with the serial clock signal.
[0004]
Generally, serial memories mounted on electronic devices are provided in various memory sizes, but the serial memory differs only in the bit length of the read or write address depending on the memory size. .
Therefore, if only the bit length of the corresponding address is changed according to the memory size, it is possible to execute read / write operations on serial memories having various sizes.
And even if the size of the memory mounted on the device is unknown, the timing of the read data output from the top of the serial data input to the DI port and the Do port varies depending on the memory size. Japanese Laid-Open Patent Publication No. 2000-122921 discloses a method for automatically recognizing a memory size.
[0005]
[Problems to be solved by the invention]
However, the automatic memory size recognition method disclosed in Japanese Patent Laid-Open No. 2000-122921 has the following problems.
In other words, the memory size automatic recognition method described in the above publication is such that when a read command and a read address having a predetermined bit length are input to a DI port of a serial memory whose memory size is unknown, the head of read data output from the Do port is input. The time interval between the response bit and the head of the read command is detected, and the memory size is determined based on this time interval.
However, in this case, it is assumed that the Lo level response bit is added to the head of the read data.
Therefore, for example, there is a problem that this automatic recognition method cannot be applied to a serial memory having a generally widespread interface such as an SPI (Serial Peripheral Interface) to which no response bit is added.
The present invention has been made to solve the above problems, and provides a determination method capable of automatically determining an access mode of a serial memory having an interface conforming to an SPI to which no response bit is added. For the purpose.
[0006]
[Means for Solving the Problems]
In order to solve the above-mentioned problem, the invention of claim 1 is a method of accessing a serial memory compliant with SPI and automatically determining the memory size of the serial memory , wherein the serial memory stores data. If not outputted, the potential of the data output terminals of the serial memory is configured to be held at a constant potential, and supplies the initial data having a predetermined bit configuration including a write command to said serial memory memory, the A step of writing a data value different from the value at the data output terminal when the serial memory does not output data, and read data having a predetermined bit configuration including a read command after the write processing to the serial memory And a step of reading the determination data based on the initial data, and the determination data Based on the data, characterized in that a step of memory performs the processing for judging the access mode of said serial memory at the time of defining a memory access mode that the number of bytes of address data required.
[0007]
According to a second aspect of the present invention, in the first aspect, the potential of the data output terminal of the serial memory is Hi level, and the initial data is a write command and one byte of 00h, 00h, 00h, 00h following the command. Yes, the read data is a read command and 1 byte of 00h, 00h, 00h, 00h respectively following the command, and the determination data is 3-byte output data read from the memory, and the read determination data The access mode of the serial memory is determined from the output pattern of 00h.
[0008]
According to a third aspect of the present invention, there is provided an apparatus for automatically determining the memory size of a serial memory compliant with SPI, comprising a pull-up resistor for setting the potential of the data output terminal of the serial memory to Hi level, and a predetermined bit. An initial data write processing unit for outputting initial write data different from the value of the data output terminal having a configuration, and determination data based on the initial write data while supplying read data having a predetermined bit configuration to the serial memory A determination data read processing unit for reading and a determination processing unit for determining an access mode of the serial memory based on the determination data are provided.
[0009]
According to a fourth aspect of the present invention, in the third aspect, the initial write data is a write command and a fixed bit string of 00h, 00h, 00h, and 00h each following the command, and the read data is a read command and This is a 1-byte standard bit string of 00h, 00h, 00h, and 00h following the command. Based on the read determination data, the determination processing unit accesses the serial memory from the output pattern of 00h in the determination data. The mode is determined.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described based on embodiments shown in the drawings. FIG. 1 is a connection wiring diagram for accessing a serial memory having an interface compliant with the SPI, and a flowchart for the access mode determination process.
As shown in FIG. 1 (a), the discrimination device is composed of a CPU 2 and a pull-up resistor 3, and the Do, DI, SK, and Cs ports of the serial memory 1 whose memory size is unknown are surrounded by dotted lines in the figure. The CPU 2 is connected to a corresponding I / O pin.
The Do port is connected to a power supply circuit by a pull-up resistor 3, and the potential is always at a Hi level.
In the circuit configuration shown in FIG. 5, the CPU 2 determines the memory size of the memory 1 as shown in the flowchart of FIG. This is realized by sequentially performing the procedure of the determination process (f3).
[0011]
Before describing the processing procedure shown in the flowchart, the data structure of the serial memory of the interface conforming to the SPI, and page writing and reading will be described.
Generally, the concept of a page is used for an SPI interface serial memory. This will be described by taking an 8-bit memory as an example.
2A and 2B show the data structure of an 8-bit address memory.
In the 8-bit address memory shown in FIG. 6A, addresses can be specified from 00h to FFh (hexadecimal display, hereinafter, when address, data, etc. are expressed in hexadecimal display, suffix h). , D1 to D256 (each data is in units of 1 byte), a total of 256 bytes of data can be written and stored.
[0012]
A group of several bytes of each data in the memory is called one page.
Normally, one page has a page size that is a multiple of 4 such as 4, 8, 16, 32, and 256 bytes depending on the memory size. Here, one page is described as 4 bytes.
According to the above, assuming 4 bytes / page, the memory of 8-bit address has a data structure of 64 pages.
[0013]
When writing data to the memory, as shown in the timing chart of FIG. 7B, a write command and a 1-byte address are input to the DI port, and subsequently, write data is continuously input for a predetermined number of bytes. . Then, the write data is continuously written in the same page one byte at a time starting from the address. For example, when an address is specified as 00h in an 8-bit address memory, and subsequently 4 bytes of data are input as 00h, 01h, 02h, 03h, as shown in FIG. 2B, addresses 00h-03h Each byte of data 00h, 01h, 02h, 03h is continuously written.
[0014]
On the other hand, in the case of reading, an address is input together with a read command, and then dummy data having the same number as the number of bytes of data to be read is input.
Then, data is successively read out byte by byte in accordance with the input of the dummy data in the order of addresses that are continuous from the address.
In the case of reading, if dummy data is added, it is possible to read continuously regardless of the page. The dummy data may be any data as long as it is 1 byte.
[0015]
Next, the procedure of the initial data write process (f1), the determination data read process (f2), and the determination process (f3) shown in the flowchart of the present invention in FIG.
Here, the number of bytes of address data required by the memory is defined as a memory access mode, and the memory is classified according to the memory capacity as shown in the access mode classification table of FIG.
[0016]
FIG. 4 is a flowchart showing details of the initial data writing process, a standard bit string output from the CPU for initial data writing, and a recognition table for each access mode of the standard bit string.
As shown in the flow of FIG. 4A, in the initial data write process, after the Cs port is set from the Hi level to the Lo level (f11), the CPU 2 sends the DI data to the DI port and the initial data routine shown in FIG. Bit strings (1), (2), (3), (4), and (5) are output. That is, first, the write command (1) is output (f12), and then 4-byte zeros (00h) (2) to (5) are output (f13 to f16).
[0017]
Next, when a predetermined serial clock signal is input to the SK port and the Cs port is returned from the Lo level to the Hi level (f17), the 4-byte zero (00h) is input to the memory 1, and the predetermined address is set. As described later, data is written.
In the case of inputting the initial data or reading of the determination data described later, a predetermined signal is given to the Cs port and the SK port as shown in FIG. Hereinafter, description thereof is omitted.
[0018]
Of the fixed bit string composed of (1) to (5) output from the CPU 2 to the memory 1, the 4-byte zero (00h) of (2) to (5) is recognized differently depending on the access mode of the memory 1. Is done.
FIG. 4C is a table showing the difference in recognition for each access mode with respect to the 4-byte zero (00h).
As shown in the figure, in the case of the access mode 1, the first zero (2) is the address (address 0), and the second to fourth zeros (3) to (5) are the first to third write data. (00h) is recognized.
In access mode 2, the first zero (2) is the upper address, the second zero (3) is the lower address, the fourth zero (4), (5) is the first and second write data. (00h) is recognized.
[0019]
In access mode 3, the first zero (2) is the upper address, the second zero (3) is the middle address, the third zero (4) is the lower address, and the fourth zero (5) is the write. Recognized as data (00h).
Therefore, the initial data write process writes data from address 0 in any case, but the number of bytes written varies depending on the memory access mode. That is, in the case of access modes 1, 2, and 3, 3 bytes, 2 bytes, and 1 byte zero (00h) are written, respectively.
[0020]
FIG. 5 is a detailed flowchart of the determination data reading process, a fixed bit string output from the CPU for reading the determination data, and a recognition table for each access mode of the fixed bit string.
As shown in FIG. 5A, in the determination data reading process, first, the Cs port is set from the Lo level to the Hi level (f21), and then the fixed bit string (1) shown in FIG. ), (2), (3), (4), (5) are output.
That is, the read command (1) is output first (f22), followed by 2-byte zeros (2) and (3). (F23, f24)
[0021]
When the 2-byte zeros (2) and (3) are output, the first determination data is output from the Do port as described later. (F25)
Subsequent to the second zero (3), the third zero (4) and the fourth zero (5) are output from the CPU 2 (f26, f28). 3 is output from the Do port (f27, f29), the Cs port is set from the Hi level to the Lo level, and the determination data reading process ends (f30).
Of the fixed bit string for reading the determination data, the 4-byte zeros (2) to (5) are recognized differently depending on the memory access mode as in the case of the initial data writing process.
[0022]
FIG. 5C is a table showing a difference in recognition for each of the memory access modes with respect to the 4-byte zeros (2) to (5).
As shown in the figure, in the case of the access mode 1, the required number of bytes of address data is 1, so the first zero (2) is the address (address 0), and the second to fourth bytes are 1 byte. Zero (3) to (5) are recognized as dummy data for the output instruction.
In the case of the access mode 2, since the number of bytes of address data required is 2, the first zero (2) is the upper address, the second zero (3) is the lower address, the third, fourth zero ( 4) and (5) are recognized as dummy data for an output instruction.
[0023]
In the case of access mode 3, the number of bytes of address data required is 3, so the first zero (2) is the upper address, the second zero (3) is the middle address, and the third zero (4) Is recognized as the lower address, and the fourth zero (5) is the dummy data for the output instruction.
Therefore, the determination data read processing reads from address 0 in any case, but the number of bytes of data read from the memory differs depending on the memory access mode.
[0024]
FIG. 6 is a detailed flowchart of read data list and determination processing for each access mode in determination data read processing f2.
In the determination data read processing, when the first and second zeros (2) and (3) are input to the memory 1 following the read command (1), as shown in FIG. When the memory is in access mode 1 in exchange for the zero (3), data zero (00h) is read from the address 0 of the memory to the Do port.
However, if the memory is in access mode 2, the first and second zeros (2) and (3) specify the upper and lower addresses, and if the memory is in access mode 3, The first and second zeros (2) and (3) specify the upper and middle addresses.
[0025]
In the case of the access modes 2 and 3, the address of the necessary number of bytes (2 bytes in the access mode 2 and 3 bytes in the access mode 3) is shown in FIG. The data in the state of FFh is output in hexadecimal notation by the potential suspended at Hi by the pull-up resistor 3 connected to the Do port.
In this way, data obtained from the Do port in exchange for the second zero is used as the first determination data.
Similarly, data read out from the Do port in exchange for the third zero (4) and the fourth zero (5) are set as second and third determination data, respectively.
[0026]
FIG. 6B is a detailed flowchart of the determination process. The determination processing is performed based on the first to third determination data. As shown in the figure, if the first determination data is zero (00h) (f31), the memory in the access mode 1 It is determined.
If the first determination data is non-zero and the second determination data is zero (00h) (f32), the access mode 2 and the second determination data are also non-zero and the third determination data is zero (00h). ) (F33), the access mode 3 is determined. If the third determination data is not zero, it is determined that the memory is faulty (f34).
[0027]
As described above, according to the processing steps shown in FIGS. 4, 5, and 6, the SPI-compliant serial memory has one of address modes 1, 2, and 3, that is, the number of address bits is 9 bits or less, 16 bits or less, Alternatively, it can be determined whether it is 24 bits or less.
[0028]
【The invention's effect】
As described above, the serial memory access mode determination method according to the present invention performs write processing on a serial memory having an unknown memory size by giving a 4-byte zero following the write command, Following the read command, a 4-byte zero is given to perform the read process.
Then, the access mode of the memory is determined based on the first, second, and third determination data obtained by the reading process.
Accordingly, the present invention can automatically determine the access mode of the memory reliably even in the case of a memory of a kind in which the response bit is not added to the read data, such as an SPI interface memory.
Therefore, the memory size discrimination method of the present invention is very effective in providing a fast processing speed discrimination method with a very simple low-cost configuration for a serial memory conforming to an SPI whose memory size is unknown.
[Brief description of the drawings]
FIG. 1A is a connection wiring diagram for accessing a memory having an interface conforming to an SPI according to the present invention, and FIG. 1B is an access mode determination process flowchart ;
2A is a data structure of an 8-bit address serial memory, and FIG. 2B is an explanatory diagram of a state in which data is written to the serial memory of FIG.
FIG. 3 is an access mode classification table.
4A is a detailed flowchart of initial data writing processing, FIG. 4B is a configuration diagram of a fixed bit string output from the CPU for writing initial data, and FIG. 4C is a fixed bit string of FIG. 4B. Recognition table for each access mode.
5A is a detailed flowchart of determination data read processing, FIG. 5B is a fixed bit string output from the CPU for reading determination data, and FIG. 5C is an access to the fixed bit string of FIG. 5B. Recognition table for each mode.
6A is a list of read data for each access mode in a determination data read process, and FIG. 6B is a detailed flowchart of the determination process.
7A is a block diagram of a general serial memory, and FIG. 7B is a timing chart of serial memory access.
[Explanation of symbols]
1. Serial memory of unknown size with SPI interface
2 .... CPU, 3 .... Pull-up resistor 11 .... Serial memory with SPI interface

Claims (4)

A method of accessing a serial memory compliant with SPI and automatically determining the memory size of the serial memory,
When the serial memory does not output data, the data output terminal of the serial memory is configured to be held at a constant potential,
Supplying initial data having a predetermined bit configuration including a write command to the serial memory , and performing a process of writing a data value different from a value at a data output terminal when the serial memory does not output data ; ,
Supplying read data having a predetermined bit configuration including a read command to the serial memory after the write process, and performing a process of reading determination data based on the initial data;
And a step of performing a process of determining the access mode of the serial memory when the number of bytes of address data required by the memory is defined as the memory access mode based on the determination data. SPI interface serial memory access mode automatic determination method. The potential of the data output terminal of the serial memory is Hi level, the initial data is a write command and 1 byte of 00h, 00h, 00h and 00h following the command, respectively, and the read data is a read command and the command Are 1 byte of 00h, 00h, 00h, 00h, respectively.
The determination data is 3-byte output data read from the memory,
2. The method for automatically determining an access mode of a memory having an SPI interface according to claim 1, wherein an access mode of the serial memory is determined from an output pattern of 00h in the read determination data. An apparatus for automatically determining the memory size of a serial memory compliant with SPI, comprising a pull-up resistor for setting the potential of the data output terminal of the serial memory to Hi level,
An initial data write processing unit that outputs initial write data different from the value of the data output terminal having a predetermined bit configuration, and based on the initial write data while supplying read data having a predetermined bit configuration to the serial memory A determination data read processing unit for reading the determination data;
An SPI interface serial memory access mode automatic determination device, comprising: a determination processing unit that determines an access mode of the serial memory based on the determination data. The initial write data is a regular bit string of 00h, 00h, 00h, 00h of 1 byte following each of the write command and the command, and the read data is 00h, 00h of 1 byte following each of the read command and the command. It is a standard bit string of 00h, 00h,
4. The SPI interface serial memory according to claim 3, wherein an access mode of the serial memory is determined from an output pattern of 00h in the determination data in the determination processing unit based on the read determination data. Automatic access mode discriminator.

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