JP5794965B2 - Memory inspection apparatus, memory inspection method, and memory inspection program - Google Patents

Description

  The present invention relates to a memory inspection device, a memory inspection method, and a memory inspection program.

  An air conditioner or the like is equipped with a control microcomputer (microcomputer) and a nonvolatile memory in which an operation program and the like are stored. However, in the production process of a product, a memory having a capacity different from the assumed capacity may be mounted. When the capacity of the mounted memory is different from the assumed capacity, there arises a problem that the operation program cannot be stored. Therefore, it is necessary to inspect the mounted memory and determine the capacity. Various means are known as means for determining the memory capacity.

  In Patent Document 1, a write process (step f1) is performed by giving a 4-byte zero (00h) to the DI port of the memory 1 whose memory size is unknown, followed by a write command, and then, 4 bytes following the read command. A technique is disclosed in which determination data is read (step f2) by giving zero (00h) and the memory access mode is determined from the output pattern of 00h in the determination data read in the read process. . However, in the technique disclosed in Patent Document 1, it is assumed that there is a page concept, and a write command to be given to the nonvolatile memory and a standard bit string of 00h, 00h, 00h, 00h of 1 byte following the command are respectively provided. The memory access mode is automatically determined from the coincidence / non-coincidence of the write data and the read data by utilizing the fact that the byte boundary between the address and the data is recognized as being shifted.

JP 2004-265283 A

  However, in the serial access type memory, when the address is directly specified for writing or reading (when the page concept is not provided), the access command length differs depending on the memory capacity. If the access command lengths are different, there is a problem that the received command cannot be recognized and cannot be written or read. Therefore, in the serial access type memory in which the access command length is determined according to the capacity of the memory to be accessed and the address is directly specified to write or read, data cannot be read from or written to the memory whose access command length is unknown. There were problems such as.

  The present invention has been made in view of the above, and it is possible to detect or access an abnormality even if the capacity of the mounted memory is unknown and the access command length of the memory is unknown. One object is to obtain a memory inspection device.

In order to solve the above-described problems and achieve the object, a memory inspection device of the present invention includes a serial access type memory that directly designates an address, a memory capacity from the assumed minimum capacity to an assumed maximum capacity, and access. A memory inspection device configured to be applicable to a product including a memory capacity determination unit that refers to a correspondence relationship between a command length and a bit number k of an address length (k is a natural number). A memory pass / fail judgment unit for judging, wherein the memory capacity judgment unit of the product starts a determination from an assumed minimum capacity of the memory, and a second ^k−1 −1th address of the memory A first step of writing first identification data to one address and confirming that the first identification data has been written to the first address; and If an error occurs due to the confirmation, a second step of determining whether or not a memory capacity twice as large as the memory that has performed the first step is larger than the assumed maximum capacity, and the second step When the double memory capacity is larger than the assumed maximum capacity, the determination is made as abnormal, or when the double memory capacity is equal to or less than the assumed maximum capacity, the access command length is set. A third step that repeats the first and second steps until it returns to the first step and is determined to be error-free or abnormal by the confirmation in the first step; If no error is generated by the confirmation in the first step, the second identification data is written to the second address which is the ( ^2k- 1) th address, and the second identification data is written. The A fourth step of confirming the door, said determining the memory capacity value 2 ^k-1 and in the case the first identification data read from the identification data and the second address read from the address are equal, vary The fifth step of determining the memory capacity value as 2 ^k and the end of the determination after determining that the memory capacity value is abnormal in the third process or after determining the memory capacity value in the fifth process And the memory quality determination unit determines the quality of the memory based on the determined memory capacity value or memory abnormality .

  According to the memory inspection device of the present invention, in a serial access type memory that directly designates an address, even if the capacity of the mounted memory is unknown, an abnormality can be detected or accessed. . Furthermore, there is an effect that the capacity of the memory can be easily determined. Further, by utilizing the present invention, it is possible to prevent the memory from being erroneously mounted on the product.

FIG. 1 is a diagram showing an example of a block diagram showing a configuration of a memory inspection device of the present invention and a product to be inspected by the memory inspection device. FIG. 2 is a diagram showing an example of an access command format used in the memory inspection according to the present invention. FIG. 3 is a flowchart illustrating an example of the memory inspection method of the present invention. FIG. 4 is a diagram illustrating an example of a relationship among a memory identification number, an identification address, an access command length, an address length, identification data, and a memory capacity.

  Embodiments of a memory inspection apparatus and a memory inspection method according to the present invention will be described below in detail with reference to the drawings. Note that the present invention is not limited to the embodiments.

Embodiment.
First, the memory inspection device of the present invention will be described. FIG. 1 is an example of a block diagram showing a configuration of a memory inspection device of the present invention and a product inspected by the memory inspection device. FIG. 1 shows an inspection apparatus 10 and a product 20 to be inspected by the inspection apparatus 10. In FIG. 1, the inspection apparatus 10 includes a communication unit 12 and a memory quality determination unit 14, and the product 20 includes a microcomputer 22 and a memory 30. The microcomputer 22 includes a communication unit 24, a memory capacity determination unit 26, and a memory access unit 28.

  The communication unit 12 provided in the inspection apparatus 10 transmits and receives signals to and from the communication unit 24 provided in the microcomputer 22 by wire or wireless.

  The memory quality determination unit 14 provided in the inspection apparatus 10 transmits and receives signals to and from the communication unit 12 and determines whether the memory 30 provided in the product 20 is normal or abnormal. The memory pass / fail determination unit 14 also determines whether or not the memory 30 has a memory capacity value suitable for the product 20.

  The product 20 is a product on which a microcomputer 22 and a memory 30 are mounted. An example of the product 20 is an air conditioner. When the product 20 is an air conditioner, the microcomputer 22 is a microcomputer that controls the air conditioner.

  The microcomputer 22 has a function of controlling the product 20 and includes a communication unit 24, a memory capacity determination unit 26, and a memory access unit 28. Here, the memory access unit 28 functions as an interface between the communication unit 24 and the memory 30, and performs processing of signals to be transmitted and received as necessary.

  The communication unit 24 communicates with the communication unit 12 provided in the inspection apparatus 10 by wire or wireless.

  The memory capacity determination unit 26 transmits and receives signals to and from the memory 30 via the memory access unit 28 when inspecting the memory 30. The memory capacity determination unit 26 has a storage area, and a program used when the memory 30 is inspected is preferably incorporated in the storage area. The memory capacity determination unit 26 includes a table 26a described later.

  The memory access unit 28 functions as an interface between the memory capacity determination unit 26 and the memory 30, and performs processing of signals to be transmitted and received as necessary.

  The memory 30 is a serial access type memory mounted on the product 20, and performs writing or reading by directly specifying an address. The memory 30 is inspected by the inspection device 10, and further its memory capacity is determined.

  However, the configuration of the memory inspection device of the present invention is not limited to that shown in FIG. 1, and the memory capacity determination unit may be provided in the inspection device 10.

  Next, the memory inspection method of the present invention will be described.

  FIG. 2A shows an example of an access command format in the present invention. The upper part of FIG. 2A shows an example of an access command format in a 64-byte memory, and the lower part of FIG. 2A shows an example of an access command format in a 128-byte memory.

  FIG. 2B also shows an example of the access command format in the present invention. The upper part of FIG. 2B shows an example of an access command format in a 256-byte memory, and the lower part of FIG. 2B shows an example of an access command format in a 512-byte memory.

  2A and 2B, a combination of A and a number represents an address bit, and a combination of D and a number represents a data bit. That is, A0 represents the least significant bit of the address, and D0 represents the least significant bit of the data. In the upper part of FIGS. 2A and 2B, Ax shown in the most significant bit of the address is a dummy bit. In FIG. 2A, the access command length is 18 bits, and in FIG. 2B, the access command length is 20 bits.

  2A and 2B, the bit string of the first to third bits represents a “data write command”, which is a command for executing data write. Here, for example, the data write command is “110”. In FIG. 2A, the fourth to tenth bit strings represent “addresses”. In FIG. 2B, the bit string of the 4th to 12th bits represents “address”. That is, the bit string represents an address accessed by the access command. In FIG. 2A, the 11th to 18th bit strings represent “write data”. In FIG. 2B, the bit string of the 13th to 20th bits represents “write data”. That is, the bit string represents data written by the access command.

  Here, the length of the “data write command” is called “command length”, and in the example shown in FIGS. 2A and 2B, the command length is 3 bits. Thus, in this specification, “access command length” and “command length” are distinguished from each other, “command length” represents the length of the bit string of the command, and “access command length” represents the command , The address bit string, and the data bit string.

In the 64 (2 ⁶ ) byte memory shown in FIG. 2A, all areas can be accessed with an address length of 6 bits, and in the 128 (2 ⁷ ) byte memory, all areas can be accessed with an address length of 7 bits. It is. Note that the 64-byte memory shown in FIG. 2A can be accessed by setting the most significant bit to 0 even for an access command having an address length of 7 bits.

In the memory of 256 (2 ⁸ ) bytes shown in FIG. 2B, all areas can be accessed with an address length of 8 bits, and in the memory of 512 (2 ⁹ ) bytes, all areas can be accessed with an address length of 9 bits. It is. Note that the 256-byte memory shown in FIG. 2B can be accessed by setting the most significant bit to 0 even for an access command having an address length of 9 bits.

  2A and 2B exemplify a case where the command length is 3 bits, the present invention is not limited to this.

  If the access command length of the data to be written is different from the access command length of the memory in the serial access type memory in which the address is directly specified, the erroneous write prevention function of the device works and an error occurs because writing cannot be performed. That is, data with an access command length of 20 bits cannot be written into a memory with an access command length of 18 bits. In this way, by using the fact that data cannot be written when the data access command length is different from the memory access command length, it is possible to determine the memory capacity by writing data in order from the shortest access command length. it can.

  FIG. 3 is a flowchart illustrating an example of the memory inspection method of the present invention. Here, the assumed maximum capacity of the mounted memory is denoted as M. As for the access command length with respect to the capacity of the mounted memory, the table shown in FIG. 4 is included in the memory capacity determination unit 26 (see the table 26a in FIG. 1).

  In the following description, “0x” represents that the numerical value that follows is a hexadecimal number.

  First, a case where the installed memory capacity is 256 bytes will be described as an example. First, the operation is started, and the inspection apparatus 10 sets the memory identification number A = 0 (step S30).

Next, the memory capacity determination unit 26 that has received the notification of the memory identification number A = 0 from the inspection device 10 writes the identification data 1 at the address 1 at the memory identification number A = 0 (step S31). Here, address 1 is assumed to be 64 * 2 ^A −1. With memory identification number A = 0, address 1 is [0x03F]. The identification data 1 is [0x55].

  Then, whether or not the identification data 1 has been correctly written to the address 1 is read, the data at the address 1 at the memory identification number A = 0 is read, and the memory capacity determination unit 26 verifies (step S32). Here, referring to FIG. 4, when the memory identification number A = 0, the access command length is 18 bits, but since the mounted memory is 256 bytes, the access command length is 20 bits. As described above, when the access command length of the data to be written does not match the access command length of the mounted memory, the identification data 1 [0x55] is not written to the address 1 [0x03F], and a write error or verify error occurs. Arise. When a write error or a verify error occurs, an error is transmitted to the inspection apparatus 10, and A = A + 1 is executed by the inspection apparatus 10 (step S38).

Then, after S38, the inspection apparatus 10 determines whether or not the current memory identification number A exceeds the memory identification number A _M in the assumed maximum capacity M (A> A _M ) (step S39).

In S39, if it is A> _{A M} determines that the inspection device 10 is a memory error (step S40). That is, it can be determined that the capacity of the mounted memory is smaller than the assumed minimum capacity (memory capacity at the memory identification number A = 0), larger than the assumed maximum capacity M, or no memory is installed.

In S39, if not A> _{A M} is the memory capacity determination unit 26 writes the identification data 1 to address 1 in the memory identification number A (step S31), and verify again (step S32). If an error occurs, the inspection apparatus 10 further adds one to the memory identification number A (step S38), determines whether or not A> _{A M} (step S39). By this determination, a memory abnormality is detected (step S40), or the process proceeds to a step of writing the identification data 1 again at the address 1 in the memory identification number A (step S31).

Thereafter, either determined to be A> A _M in S39, or until a write error or verification error does not occur in S32, and repeats the above process.

  When 1 is added to the memory identification number A as described above, the access command length increases as shown in the table of FIG. FIG. 4 is a diagram illustrating the relationship between the memory identification number A, the identification address corresponding to the memory identification number A, the access command length, the address length, the identification data, and the memory capacity.

  In FIG. 4, the assumed minimum capacity is 64 bytes and the assumed maximum capacity M is 2048 bytes.

  When the access command length of the data to be written matches the access command length of the mounted memory, the identification data 1 is written to the address 1 in the memory identification number A when the data matches. After that, when verification is performed, it is determined that the identification data 1 is correctly written, except when the memory element itself is defective, and the process proceeds to the next step (step S32).

Here, since the memory identification number A = 1 in S38 and does not exceed the memory identification number A _M = 5 in the assumed maximum capacity M, the process returns from S39 to S31.

Thereafter, identification data 1 is written to address 1 at memory identification number A = 1 (step S31). In memory identification number A = 1, the access command length is 18 bits, but since the mounted memory is 256 bytes, the access command length is 20 bits. The access command length of the data to be written and the access command of the mounted memory The lengths do not match. For this reason, a write error or a verify error occurs (step S32). Then, A = A + 1 is executed again, and the memory identification number A = 2 is obtained (step S38). The memory identification number A = 2 does not exceed the memory identification number A _M = 5 in the assumed maximum capacity M (step S39), and the process returns to S31.

  Thereafter, identification data 1 [0x55] is written to address 1 [0x0FF] at memory identification number A = 2 (step S31). In the memory identification number A = 2, the access command length is 20 bits, and since the installed memory is 256 bytes, the access command length is 20 bits. Therefore, the access command length of the data to be written matches the access command length of the mounted memory, and no error occurs even if verification is performed, and the identification data 1 is recognized as being written correctly.

Next, identification data 2 is written to address 2 (step S33). Here, address 2 is, for example, 64 * 2 ^{A + 1} −1. Here, identification data 2 [0xAA] is written to address 2 [0x1FF]. However, since the installed memory is 256 bytes, the address 2 [0x1FF] does not exist and the most significant bit of the address is not recognized. Therefore, the identification data 2 [0xAA] is actually overwritten on the address 1 [0x0FF].

When the identification data 2 [0xAA] is represented by a binary number, it is (10101010) ₂ , and when the numerical value [0x55] of the identification data 1 is represented by a binary number, it is (01010101) ₂ , and the identification data 2 and the identification data At 1, the bit is inverted.

  Here, the identification data 2 [0xAA] written to the address 2 [0x1FF] is verified. Here, when the mounted memory is 256 bytes, the address 2 [0x1FF] does not exist and the most significant bit of the address is not recognized, so that the address 1 [0x0FF] was written even when reading data The identification data 2 [0xAA] is read out. Therefore, even if “identification data 2” is written in “address 2” in S33 or actually “identification data 2” is written in “address 1”, it is recognized that the data has been written correctly (step). S34).

  However, if the memory element itself is defective in S34, it is not recognized that the memory element is correctly written. In that case, an error occurs and the process proceeds to S38, A = A + 1 is executed (step S39), and the above operation is repeated.

Next, address 1 and address 2 are compared (step S35). When the mounted memory is 256 bytes, the address 2 [0x1FF] does not exist and the most significant bit of the address is a dummy, so the address 2 [0x1FF] is recognized as the address 1 [0x0FF]. In other words, address 1 and address 2 are recognized as the same address. Therefore, the process proceeds to S36, and it is determined that the memory capacity is 64 * 2 ^A = 256 bytes. Here, the numerical value “64” used for determining the memory capacity may be the number of bytes of the assumed minimum capacity, and may be set as appropriate according to the assumed minimum capacity.

  As described above, it is determined whether the memory is normal or abnormal. If the memory is normal, the memory capacity value is determined, and the process ends.

  Next, a case where the installed memory is 512 bytes will be described as an example. When the memory identification number A = 2, the access command length of the data to be written and the access command length of the mounted memory coincide with each other until the step of recognizing that the identification data 1 is correctly written is 256 bytes. Since it is the same as that of the case, the description here is omitted.

After the identification data 1 [0x55] is written to the address 1 [0x0FF] in the memory identification number A = 2 (step S31) and it is determined that the identification data 1 [0x55] is correctly written to the address 1 [0x0FF] (step S31) In S32), the identification data 2 is written in the address 2 (step S33). Here, since the address 2 is, for example, 64 * 2 ^{A + 1} −1, the identification data 2 [0xAA] is written to the address 2 [0x1FF].

  Here, the identification data 2 [0xAA] written to the address 2 [0x1FF] is verified (step S34). Here, it is recognized that the identification data 2 [0xAA] is written correctly with respect to the address 2 [0x1FF] except when there is a defect in the memory element itself (step S34). When there is a defect in the memory element itself, as in the case of 256 bytes, the process proceeds to S38, A = A + 1 is executed, and the above operation is repeated.

Next, address 1 and address 2 are compared (step S35). Here, unlike the case of 256 bytes, address 2 [0x1FF] exists. Therefore, address 1 and address 2 are recognized as different addresses and the process proceeds to S37, and the memory capacity is determined to be 64 * 2 ^{A + 1} = 512 bytes (normal or abnormal, normal In some cases, the memory capacity value is included.) Here, the numerical value “64” used for determining the memory capacity may be the number of bytes of the assumed minimum capacity, and may be set as appropriate according to the assumed minimum capacity.

In the above description, if the number of bits of the address length is k, the capacity value of the determined memory is 2 ^k-1 when address 1 and address 2 are recognized as equal, and address 1 If the address 2 is different from the recognition and is 2 ^k. That is, the description of 256 bytes and 512 bytes described above corresponds to the description of k = 9.

To summarize the memory testing method of this embodiment described above, the memory testing method of the present embodiment, the memory capacity of the assumed minimum amount of memory of the serial access method designating an address directly the envisaged maximum capacity and access bit number k of the command length and address length (k is a natural number) a memory test method which includes a memory capacity determining step of referring to the correspondence relationship between a memory quality determination step, the memory capacity determining step, A starting step of starting determination from the assumed minimum capacity of the memory; and writing first identification data to a first address that is the second ^k−1 −1th address of the memory, and the first identification data is A first step of confirming that data has been written to the first address; and if an error occurs due to the confirmation in the first step, the first step is performed. A second step of determining whether twice the memory capacity of the memory is greater than the assumed maximum capacity, by the determination of the second step, the case 2 times the memory capacity of greater than the assumed maximum capacity If the double memory capacity is less than or equal to the assumed maximum capacity, the access command length is lengthened and the process returns to the first process, and the process in the first process is performed. In the case where no error occurs due to the third step in which the first and second steps are repeated until no error is determined by the confirmation or it is determined to be abnormal, and the confirmation in the first step, a fourth step of confirming that the second address is a second ^k -1 th address write second identification data, the identification data of the second are written, read out from said first address A fifth step of determining the memory capacity value 2 ^k when the identification data read from the second address and the identification data memory capacitance determines that 2 ^k-1 if equal correct, different, An end step of ending the determination after determining the abnormality in the third step or determining the memory capacity value in the fifth step, wherein the memory pass / fail determination step includes the determined memory capacitance or memory abnormally basis characterized in that it comprises a step of determining acceptability of said memory.

  In this embodiment, the access command length is increased by 2 bits when the access command length is increased, and the identification data 1 and the identification data 2 are used as identification data. However, the present invention is not limited to this.

  Note that the memory inspection method described in the present embodiment can be stored in the memory capacity determination unit 26 as a program and executed.

  As described in the present embodiment, according to the present invention, in a serial access type memory that directly specifies an address, even if the capacity of the mounted memory is unknown, an abnormality is detected or accessed. There is an effect that can be. Furthermore, there is an effect that the capacity of the memory can be easily determined. Further, by utilizing the present invention, it is possible to prevent the memory from being erroneously mounted on the product.

  As described above, the memory inspection device, the memory inspection method, and the memory inspection program according to the present invention are useful for inspecting a memory mounted on a product.

  10 inspection devices, 12, 24 communication unit, 14 memory pass / fail judgment unit, 20 products, 22 microcomputer, 26 memory capacity judgment unit, 26a table, 28 memory access unit, 30 memory, S30 to S40 steps.

Claims (5)

A serial access type memory that directly specifies an address, and a memory that refers to the correspondence between the memory capacity from the assumed minimum capacity to the assumed maximum capacity of the memory, the access command length, and the number k of bits of the address length (k is a natural number) A memory inspection device configured to be applicable to a product including a capacity determination unit,
A memory pass / fail judgment unit for judging pass / fail of the memory;
The memory capacity determination unit of the product is
A starting step of starting determination from the assumed minimum capacity of the memory;
The first identification data is written to the first address which is the 2 ^k-1 -th address of the memory, and the first identification data is confirmed to be written to the first address. And the process of
A second step of determining whether or not a memory capacity that is twice as large as the memory that has performed the first step is larger than the assumed maximum capacity when an error occurs due to the confirmation in the first step;
By the determination in the second step,
If the double memory capacity is larger than the assumed maximum capacity, it is determined to be abnormal,
Alternatively, when the doubled memory capacity is less than or equal to the assumed maximum capacity, the access command length is lengthened and the process returns to the first process, and no error occurs due to the confirmation in the first process or an error occurs. A third step that repeats the first and second steps until it is determined that
If no error is generated by the confirmation in the first step, the second identification data is written to the second address which is the 2 ^k −1th address, and the second identification data is written A fourth step to confirm that,
When the identification data read from the first address is the same as the identification data read from the second address, the memory capacity value is determined as 2 ^k−1, and when the identification data is different, the memory capacity value is determined as 2 ^k. And a fifth step
An end step of ending the determination after determining the abnormality in the third step or after determining the memory capacity value in the fifth step,
The memory inspection device, wherein the memory quality determination unit determines quality of the memory based on the determined memory capacity value or memory abnormality .   The memory inspection apparatus according to claim 1, wherein the product is an air conditioner. A memory capacity determining step for referring to a correspondence relationship between a memory capacity from an assumed minimum capacity to an assumed maximum capacity of a serial access type memory that directly designates an address, an access command length, and a bit number k (k is a natural number) of the address length; A memory inspection method including a memory pass / fail judgment step,
The memory capacity determination step includes
A starting step of starting determination from the assumed minimum capacity of the memory;
The first identification data is written to the first address which is the 2 ^k-1 -th address of the memory, and the first identification data is confirmed to be written to the first address. And the process of
A second step of determining whether or not a memory capacity that is twice as large as the memory that has performed the first step is larger than the assumed maximum capacity when an error occurs due to the confirmation in the first step;
By the determination in the second step,
If the double memory capacity is larger than the assumed maximum capacity, it is determined to be abnormal,
Alternatively, when the doubled memory capacity is less than or equal to the assumed maximum capacity, the access command length is lengthened and the process returns to the first process, and no error occurs due to the confirmation in the first process or an error occurs. A third step that repeats the first and second steps until it is determined that
If no error is generated by the confirmation in the first step, the second identification data is written to the second address which is the 2 ^k −1th address, and the second identification data is written A fourth step to confirm that,
When the identification data read from the first address is the same as the identification data read from the second address, the memory capacity value is determined as 2 ^k−1, and when the identification data is different, the memory capacity value is determined as 2 ^k. And a fifth step
An end step of ending the determination after determining that there is an abnormality in the third step or after determining the memory capacity value in the fifth step,
The memory inspection method includes a step of determining the quality of the memory based on the determined memory capacity value or memory abnormality.   4. The memory inspection method according to claim 3, wherein the numerical value of the second identification data is a numerical value twice that of the first identification data.   A memory inspection program for causing a computer to execute the memory inspection method according to claim 3.

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