JP4390639B2 - LSI design system, LSI design program - Google Patents

Description

  The present invention relates to an LSI design system and an LSI design program, and more particularly, to an LSI design system and an LSI design program for designing an LSI on a platform basis using a design asset (IP; Intelligent Property).

  A system-on-chip in which one system is constructed on one chip has been developed with the improvement of the degree of LSI integration. As a result, LSI design is becoming a system design itself, not just a partial circuit design. That is, it is necessary to design an LSI at the system level and to analyze / verify the obtained LSI design at the system level.

  In such LSI design, in order to improve the development efficiency, a technique for diverting existing “design assets (IP)” is known. This IP is a functional block that has been designed and verified. By designing an LSI by combining a plurality of IPs, the design period is shortened and productivity is improved. In particular, according to the platform-based design technology, an IP for realizing a function unique to a product is mounted on a general-purpose platform in which basic IP is integrated. This further improves development efficiency.

  In the LSI design flow, “STA (Static Timing Analysis)” that analyzes / verifies the logic of a circuit before an LSI floor plan is determined is known. This STA is a technique for analyzing whether a synchronization circuit or the like operates correctly at a set clock frequency without using a simulation pattern. Specifically, a delay analysis in a path between designated terminals and a setup time and hold time in a circuit are verified.

  In this STA, various parameters are designated. For example, a false path is designated, and a cycle, a duty ratio, etc. for setting a clock are designated. A false path is a path that is not used due to design constraints, and is a path that is intentionally excluded from the target of timing analysis. These various parameters that are designated indicate design constraints and are parameters that impose constraints on the STA. Hereinafter, this parameter is referred to as “STA constraint”.

  Conventionally, in the platform-based LSI design process, the constraint information indicating the STA constraint at the system level has been manually generated according to the configuration of the system to be developed. In this case, as the number of IPs to be used and the circuit scale increase, the time required for the STA increases, and there is a problem that a mistake such as omission of necessary information occurs. These cause a long time (TAT) from the start of design to the completion of hardware (TAT) and cause development efficiency to decrease. In addition, inadequate STAs cause the quality of the developed LSI to deteriorate.

  An object of the present invention is to provide an LSI design system and an LSI design program capable of improving LSI development efficiency.

  Another object of the present invention is to provide an LSI design system and an LSI design program capable of improving the quality of design work and developed LSI.

  Still another object of the present invention is to provide an LSI design system and an LSI design program that can promote reuse of design assets.

  [Means for Solving the Problems] will be described below using the numbers and symbols used in [Best Mode for Carrying Out the Invention]. These numbers and symbols are added in parentheses in order to clarify the correspondence between the description of [Claims] and [Best Mode for Carrying Out the Invention]. However, these numbers and symbols should not be used for the interpretation of the technical scope of the invention described in [Claims].

  An LSI design system (100) according to the present invention includes a database (10) storing an IP group including a plurality of IPs (15), and a system construction unit (20) connected to the database (10) so as to be accessible. The system constraint information generation unit (30) connected to the database (10) so as to be accessible, and the storage unit (40) connected to the system construction unit (20) and the system constraint information generation unit (30). . Each of the plurality of IPs (15) has IP constraint information (CON-IP) indicating design constraints used for LSI design verification. The system construction unit (20) generates a system net list (NL-SYS) as a system level net list determined by a plurality of combined IPs (15), and generates the system net list (NL-SYS). It outputs to a memory | storage part (40). The system constraint information generation unit (30) includes a plurality of IP constraints each of the system netlist (NL-SYS) stored in the storage unit (40) and the plurality of IPs (15) stored in the database (10). Based on the information (CON-IP), system constraint information (CON-SYS) indicating system level design constraints depending on a combination of a plurality of IPs (15) is generated. The generated system constraint information (CON-SYS) is stored in the storage unit (40).

  In the LSI design system (100), the system constraint information generation unit (30) includes a hierarchy information conversion unit (32). The hierarchical information conversion unit (32) refers to the system netlist (NL-SYS) and converts IP level hierarchical information included in each of the plurality of IP constraint information (CON-IP) into system level hierarchical information. By doing so, a plurality of IP constraint information (CON-IP) is converted into system constraint information (CON-SYS). Here, the hierarchy information is a path of a node included in each IP (15).

  In the LSI design system (100), the system constraint information generation unit (30) further includes a connection constraint detection unit (34). The connection constraint detection unit (34) refers to the system netlist (NL-SYS), thereby obtaining connection constraint information (CON2) indicating system level design constraints depending on the connection relationship of the plurality of IPs (15). Generate. This connection restriction information (CON2) is added to the system restriction information (CON-SYS).

  The plurality of IPs (15) includes a connection IP (15-2) that is used for connection between the IPs (15) and in which a plurality of terminals (T1 to T4) are defined. At this time, the connection constraint detection unit (34) detects a false path between a plurality of terminals (T1 to T4) by referring to the system netlist (NL-SYS). The connection constraint information (CON2) generated by the connection constraint detection unit (34) indicates the detected false path. Further, the connection IP (15-2) may have an extension program (16) for detecting the false path in addition to the IP constraint information (CON-IP). At this time, the connection constraint detection unit (34) reads the extended program (16) from the database (10) and executes it. Thereby, connection restriction information (CON2) is generated.

  The above IP constraint information (CON-IP), connection constraint information (CON2), and system constraint information (CON-SYS) indicate design constraints used for STA (Static Timing Analysis). At this time, the LSI design system (100) according to the present invention may further include an STA unit (80). The STA unit (80) executes the STA based on the system net list (NL-SYS) and the system constraint information (CON-SYS) generated and stored in the storage unit (40).

  Thus, according to the LSI design system (100) of the present invention, the system level constraint information (CON-SYS) used for LSI design verification is automatically generated. Therefore, the time required for verification of the LSI design is shortened, and the LSI development efficiency is improved. In addition, since mistakes in the verification process are suppressed, the design work and the quality of the developed LSI are improved. Further, the system constraint information (CON-SYS) is automatically updated by the extension program (16). Therefore, when reusing an asset designed in the past, there is no need to grasp in detail the difference between the past design and the desired design. Therefore, reuse of design assets is promoted.

  The LSI design program according to the present invention includes (A) a step of generating a system net list (NL-SYS) determined by a plurality of combined IPs (15), and (B) the system net list (NL-SYS). ) To convert the IP level hierarchical information included in each of the plurality of IP constraint information (CON-IP) into system level hierarchical information, and (C) use the system level hierarchical information. Thereby generating a plurality of first constraint information (CON1) as system level IP constraint information from a plurality of IP constraint information (CON-IP), and (D) a system netlist (NL-SYS). To show the system level design constraints that depend on the connection relationship of multiple IPs (15). Generating about information (CON2); and (E) generating a plurality of generated first constraint information (CON1) and second constraint information (CON2) as system constraint information (CON-SYS). Let the computer run.

  Further, the LSI design program according to the present invention may further cause the computer to execute the step of executing the STA by using (F) the design constraint indicated by the system constraint information (CON-SYS).

  According to the LSI design system and the LSI design program of the present invention, the LSI development efficiency is improved.

  According to the LSI design system and the LSI design program according to the present invention, the design work and the quality of the developed LSI are improved.

  The LSI design system and the LSI design program according to the present invention promote the reuse of design assets.

  An LSI design system and an LSI design program according to the present invention will be described with reference to the accompanying drawings.

  FIG. 1 is a block diagram showing a configuration of an LSI design system according to the present invention. The LSI design system 100 includes a database 10, a system construction unit 20, a system constraint information generation unit 30, a storage unit 40, a control unit 50, an input unit 60, and an output unit 70. The system construction unit 20 is connected to the database 10 so as to be accessible. The system constraint information generation unit 30 is connected to the database 10 so as to be accessible. The system constraint information generation unit 30 includes a hierarchy information conversion unit 32 and a connection constraint detection unit 34.

  The database 10 stores a set of IP15 (IP1 to IPn) used for LSI design. This database 10 is connected to the control unit 50. For example, each control unit 50 of the plurality of LSI design systems 100 is connected to the database 10 via a network, and the database 10 is referred to in the plurality of LSI design systems 100.

  The storage unit 40 is connected to the control unit 50. The storage unit 40 stores various data processed by the control unit 50. Examples of the storage unit 40 include a RAM and a hard disk device.

  The input unit 60 is connected to the control unit 50. By using the input unit 60, the user can design an LSI and input various commands and data. Examples of the input unit 60 include a keyboard and a mouse. The output unit 70 is connected to the control unit 50. An example of the output unit 70 is a display. A user can design an LSI with reference to information and drawings displayed on the display.

  The control unit 50 controls the operations of the system construction unit 20 and the system constraint information generation unit 30 described later. For example, the control unit 50 controls the exchange of information (data) between the system construction unit 20 and the system constraint information generation unit 30, the database 10, and the storage unit 40. For example, the control unit 50 includes a CPU (Central Processing Unit). At this time, the system construction unit 20, the system constraint information generation unit 30, the hierarchy information conversion unit 32, and the connection constraint detection unit 34 are computer programs executed by the CPU of the control unit 50.

  FIG. 2 is a conceptual diagram showing in detail the configuration of the database 10 according to the present invention. The database 10 stores a set of IP15 (IP1: 15-1, IP2: 15-2,..., IPn: 15-n) used for LSI design. Each IP 15 has a netlist NL-IP and IP restriction information CON-IP. “Netlist NL-IP” is data representing the connection state (circuit network) of circuits in IP15, and is described in a text list format, for example.

  “IP constraint information CON-IP” is a design constraint and indicates a design constraint such as a timing constraint used for analysis / verification of LSI design. As this design constraint, “STA constraint” used in STA is exemplified. Specifically, this STA constraint includes a false path, clock designation (cycle and duty ratio), node hierarchy name, and the like. That is, the IP constraint information CON-IP is information unique to each IP 15 and indicates an IP level STA constraint.

  Among various IP 15, there is an IP used for connection between IPs such as a bus IP. Such IP is hereinafter referred to as “connection IP”. For example, in FIG. 2, IP2: 15-2 is a connection IP such as a bus IP. This connection IP has an “Add-on program (extended program) 16” which will be described in detail later.

  The netlist NL-IP, the IP restriction information CON-IP, and the Add-on program 16 are packaged and configured as one IP 15. These IP15 sets (IP group) are created in advance by a predetermined application (tool) and stored in the database 10.

  Next, the operation of the LSI design system 100 having the above configuration will be described in detail. FIG. 3 is a diagram conceptually showing the operation of the LSI design system 100 according to the present invention.

  First, a plurality of IPs 15 necessary for a desired LSI are selected from the set of IPs 15 stored in the database 10. The plurality of selected IPs 15 are combined according to the desired LSI configuration. Here, selection / combination of the plurality of IPs 15 is performed by the designer using the input unit 60, the output unit 70, and a predetermined application (tool). Alternatively, the selection / synthesis of the IP 15 may be one of the functions provided by the system construction unit 20 to the user.

  The system construction unit 20 automatically generates a “system netlist NL-SYS” based on the plurality of IPs combined by the above-described work. The system netlist NL-SYS is data representing the connection state (IP network) of IP15 in the system, that is, a system level netlist. This system netlist NL-SYS can be determined by a plurality of combined IPs 15. Then, the system construction unit 20 outputs the generated system netlist NL-SYS. The output system netlist NL-SYS is stored in the storage unit 40 (see FIG. 1).

  Next, the hierarchy information conversion unit 32 reads a plurality of IP constraint information CON-IP included in each of the combined plurality of IPs 15 from the database 10. As described above, the IP constraint information CON-IP indicates an IP level constraint (STA constraint). The hierarchy information conversion unit 32 refers to the system netlist NL-SYS and converts the plurality of IP constraint information CON-IP into a plurality of “conversion constraint information CON1”, respectively. This “conversion constraint information CON1” is IP constraint information at the system level.

  Specifically, the hierarchy information conversion unit 32 converts the IP level hierarchy information included in the IP constraint information CON-IP into system level hierarchy information. “Hierarchy information” is a hierarchy name (path) of a node included in each IP 15. This hierarchical information is described according to a predetermined format in each IP. For example, a certain node in a certain CPU is designated by hierarchical information “CPU_IP.main_alu.adder.reg1” (hereinafter referred to as hierarchical information 1) in the CPU-IP corresponding to the CPU.

  The hierarchy information 1 is IP level hierarchy information (path), but system level hierarchy information (path) is required when designing at the system level. For example, consider the case where the CPU-IP is named “CPU_0” in the designed LSI system. At this time, the node is specified by hierarchical information such as “SOC_TOP.CPU_0.main_alu.adder.reg1” (hereinafter referred to as hierarchical information 2). That is, the hierarchy information conversion unit 32 can automatically convert the hierarchy information 1 to the hierarchy information 2 by referring to the system netlist NL-SYS. Further, the hierarchy information conversion unit 32 converts all hierarchy information included in the combined plurality of IP 15 into system level hierarchy information. In this way, all nodes in the LSI system to be designed are designated by the system level hierarchical information.

  Design constraints (STA constraints) such as a false path indicated by the IP constraint information CON-IP are specified by these node names. That is, converting IP level hierarchical information to system level hierarchical information means converting IP constraint information CON-IP to “conversion constraint information CON1”, which is system level IP constraint information. In this way, the hierarchy information conversion unit 32 automatically converts each of the plurality of IP constraint information CON-IP into a plurality of “conversion constraint information CON1” according to the system configuration.

  This conversion constraint information CON1 constitutes a part of “system constraint information CON-SYS”, which is overall constraint information at the system level. The “system constraint information CON-SYS” indicates system level design constraints depending on a plurality of IPs 15 used in the designed system. Here, the system constraint information CON-SYS may include not only the system level IP constraint information (conversion constraint information CON1) but also constraint information that depends on the “connection relationships” of a plurality of IP15. The constraint information indicating the system level design constraint depending on the connection relationship is hereinafter referred to as “connection constraint information CON2”.

  The connection constraint detection unit 34 automatically generates the connection constraint information CON2 by referring to the system netlist NL-SYS. Specifically, when the connection IP (eg, IP2 (15-2)) is included in the plurality of combined IPs 15, the connection constraint detection unit 34 adds the Add-on program (extended program) that the connection IP has. 16 is executed.

  The Add-on program 16 is described in a language or function group that can process the system netlist NL-SYS. The Add-on program 16 is unique to the connection IP 15. For example, it is assumed that a certain bus IP defines a plurality of terminals, and a master and a slave are connected to the plurality of terminals in the LSI design. Further, according to the specification of the bus IP, it is assumed that data transfer is not directly performed between slaves. In this case, in the STA, the connection between the slaves is designated as a false path. Therefore, in the Add-on program included in the bus IP, a command group having contents to be added to the connection constraint information CON2 as a false path is described as a connection between the slaves.

  As described above, the connection constraint detection unit 34 executes the Add-on program 16 included in the connection IP 15, and the Add-on program 16 outputs the connection constraint information CON2 by referring to the system netlist NL-SYS. To do. This connection constraint information CON2 is added to the system constraint information CON-SYS.

  As described above, the system constraint information generation unit 30 performs system constraint information CON-SYS (conversion constraint information CON1 and connection constraint information based on the system netlist NL-SYS and the plurality of IP constraint information CON-IP. CON2) is generated and output. The output system constraint information CON-SYS is stored in the storage unit 40 (see FIG. 1). This system constraint information CON-SYS is used as a STA constraint in the STA.

  That is, as shown in FIG. 1, the LSI design system 100 may further include an STA unit 80. The STA unit 80 is connected to the control unit 50. As shown in FIG. 3, the STA unit 80 reads the generated system netlist NL-SYS and system constraint information CON-SYS from the storage unit 40, and executes the STA using them. The STA result is output from the STA unit 80 as the analysis result RES. This analysis result RES is displayed on, for example, a display (output unit 70) and notified to the user.

  Next, the operation of the LSI design system 100 according to the present invention will be described in more detail by giving an example. FIG. 4 is a block diagram illustrating an example of a system designed by the LSI design system 100. As shown in FIG. 4, the designed system includes a master 110, a bus 120, a slave A 130, and a slave B 140. Each of the master 110, the bus 120, the slave A 130, and the slave B 140 has IP1 (15-1), IP2 (15-2), IP3 (15-3), and IP4 (15-4) stored in the database 10. ). Here, as shown in FIG. 2, this IP2 (15-2) is a connection IP. Therefore, a plurality of terminals are defined in this IP2. For example, as shown in FIG. 4, the bus 120 includes a plurality of terminals T1 to T4. The master 110 is connected to the terminal T1. Slave A130 is connected to terminal T2. Slave B140 is connected to terminal T4.

  First, the system construction unit 20 generates a system netlist NL-SYS indicating a combination and connection of a plurality of IP1 to IP4 based on the configuration shown in FIG. Then, the system construction unit 20 outputs the generated system netlist NL-SYS.

  Next, the hierarchy information conversion unit 32 automatically performs the above-described conversion of the hierarchy information (path name) for all nodes included in the master 110, the bus 120, the slave A 130, and the slave B 140. This conversion is performed by referring to the system netlist NL-SYS. As a result, all the hierarchy information is converted into system level hierarchy information. As described above, the plurality of IP constraint information CON-IP included in each of the plurality of IP1 to IP4 is corrected based on the system level hierarchical information. That is, the plurality of IP constraint information CON-IP is converted into a plurality of system-level conversion constraint information CON1 according to the system shown in FIG. Each of the plurality of conversion constraint information CON1 specifically indicates a STA constraint in the master 110, a STA constraint in the bus 120, a STA constraint in the slave A 130, and a STA constraint in the slave B 140.

  Next, the connection constraint detection unit 34 executes the Add-on program 16 included in the IP2 (15-2).

  The Add-on program 16 first refers to the system netlist NL-SYS and detects all devices connected to itself (IP2; bus 120) and their connection states. As shown in FIG. 4, in the bus 120, a path Pa defined by the terminal T1-terminal T2, a path Pb defined by the terminal T1-terminal T4, and a path Pc defined by the terminal T2-terminal T4. Exists. A master 110 and a slave A 130 are connected to the path Pa. A master 110 and a slave B 140 are connected to the path Pb. Slave A 130 and slave B 140 are connected to path Pc.

  Further, the Add-on program 16 detects STA constraints for all paths Pa to Pc. For example, according to the specification of IP2 (15-2), it is assumed that data transfer is not directly performed between slaves. In this case, the Add-on program 16 designates the path Pc as a false path. There are no restrictions on other paths. Constraint information indicating STA constraints for all paths detected in this way is output as connection constraint information CON2. The Add-on program 16 is created in advance based on “specifications” specific to each connection IP.

  As described above, according to the LSI design system 100 according to the present invention, the system constraint information CON-SYS indicating the STA constraint used in the STA is automatically generated. Therefore, the time required for the STA is shortened and the LSI development efficiency is improved. In addition, since errors in the STA are suppressed, the design work and the quality of the developed LSI are improved.

  FIG. 5 is a block diagram illustrating another example of a designed system. As shown in FIG. 5, the designed system includes a master 110, a bus 120, a slave A 130, a slave B 140, and a slave C 150. The master 110, the bus 120, the slave A 130, the slave B 140, and the slave C 150 are respectively IP1 (15-1), IP2 (15-2), IP3 (15-3), and IP4 (15) stored in the database 10. -4) and IP5 (15-5). The bus 120 includes a plurality of terminals T1 to T4. The master 110 is connected to the terminal T1. Slave A130 is connected to terminal T2. Slave B140 is connected to terminal T3. Slave C150 is connected to terminal T4.

  First, the system construction unit 20 generates a system netlist NL-SYS indicating combinations and connections of a plurality of IP1 to IP5 based on the configuration shown in FIG. Then, the system construction unit 20 outputs the generated system netlist NL-SYS.

  Next, the hierarchy information conversion unit 32 automatically performs the above-described conversion of the hierarchy information (path name) for all nodes included in the master 110, the bus 120, the slave A130, the slave B140, and the slave C150. . As a result, all the hierarchy information is converted into system level hierarchy information. That is, the plurality of IP constraint information CON-IP is converted into a plurality of system-level conversion constraint information CON1 in accordance with the system shown in FIG. Specifically, each of the plurality of conversion constraint information CON1 includes an STA constraint in the master 110, an STA constraint in the bus 120, an STA constraint in the slave A 130, an STA constraint in the slave B 140, and an STA in the slave C 150. Indicates a constraint.

  Next, the connection constraint detection unit 34 executes the Add-on program 16 included in the IP2 (15-2).

  The Add-on program 16 first refers to the system netlist NL-SYS and detects all devices connected to itself (IP2; bus 120) and their connection states. As shown in FIG. 5, in the bus 120, a path Pa defined by the terminal T1-terminal T2, a path Pb defined by the terminal T1-terminal T3, a path Pc defined by the terminal T1-terminal T4, There is a path Pd defined by the terminal T2-terminal T3, a path Pe defined by the terminal T3-terminal T4, and a path Pf defined by the terminal T2-terminal T4. A master 110 and a slave A 130 are connected to the path Pa. A master 110 and a slave B 140 are connected to the path Pb. A master 110 and a slave C150 are connected to the path Pc. Slave A 130 and slave B 140 are connected to path Pd. A slave B 140 and a slave C 150 are connected to the path Pe. Slave A130 and slave C150 are connected to path Pf.

  Further, the Add-on program 16 detects STA constraints for all paths Pa to Pf. For example, according to the specification of IP2 (15-2), it is assumed that data transfer is not directly performed between slaves. In this case, the Add-on program 16 designates the paths Pd to Pf as false paths. There are no restrictions on other paths. Constraint information indicating STA constraints for all paths detected in this way is output as connection constraint information CON2.

  The system shown in FIG. 5 has a configuration in which a new slave is added to the configuration shown in FIG. Therefore, when designing the system shown in FIG. 5, it is possible to reuse the design shown in FIG. Here, according to the LSI design system 100 according to the present invention, the Add-on program 16 automatically updates the system constraint information CON-SYS based on the updated system netlist NL-SYS. That is, it is not necessary to grasp in detail the difference between the system configuration shown in FIG. 4 and the system configuration shown in FIG. This reduces the load on the designer. That is, the LSI design system 100 according to the present invention promotes the reuse of design assets.

  In the present invention, the system construction unit 20, the system constraint information generation unit 30, the hierarchy information conversion unit 32, the connection constraint detection unit 34, and the STA unit 80 described above can be realized by a computer program. At this time, these computer programs are read into the memory and executed by the CPU of the control unit 50.

  The flowchart shown in FIG. 6 summarizes the LSI design method according to the present invention. First, a plurality of IP15 necessary for a desired LSI are selected from a set of IP15 stored in the database 10, and the selected plurality of IP15 are combined (step S1). Next, based on the combination of the plurality of IPs 15, the system construction unit 20 automatically generates a system netlist NL-SYS (step S2). Next, the hierarchy information conversion unit 32 refers to the system netlist NL-SYS and automatically converts the IP level hierarchy information into the system level hierarchy information (step S3). As a result, the IP level IP constraint information CON-IP is automatically converted into the system level conversion constraint information CON1 (step S4). Next, the connection constraint detection unit 34 executes the Add-on program 16 and automatically generates system level connection constraint information CON2 (step S5). The system constraint information CON-SYS is generated from the conversion constraint information CON1 and the connection constraint information CON2 generated in this way (step S6). Then, the STA unit 80 executes the STA using the generated system constraint information CON-SYS.

  According to the LSI design system 100 and the LSI design program according to the present invention, the system constraint information CON-SYS indicating the STA constraint used in the STA is automatically generated. Therefore, the time required for the STA is shortened and the LSI development efficiency is improved. In addition, since errors in the STA are suppressed, the design work and the quality of the developed LSI are improved. Furthermore, the reuse of design assets is facilitated.

FIG. 1 is a block diagram showing a configuration of an LSI design system according to the present invention. FIG. 2 is a conceptual diagram showing the configuration of a database in the LSI design system according to the present invention. FIG. 3 is a conceptual diagram showing the operation of the LSI design system according to the present invention. FIG. 4 is a block diagram showing a design system example for explaining the operation of the LSI design system according to the present invention. FIG. 5 is a block diagram showing another design system example for explaining the operation of the LSI design system according to the present invention. FIG. 6 is a flowchart showing the operation of the LSI design system according to the present invention.

Explanation of symbols

10 Database 15 IP (Design Asset)
16 Add-on program 20 System construction unit 30 System constraint information generation unit 32 Hierarchical information conversion unit 34 Connection constraint detection unit 40 Storage unit 50 Control unit 60 Input unit 70 Output unit 80 STA unit 100 LSI design system 110 Master 120 Bus 130 Slave A
140 Slave B
150 Slave C
NL-IP netlist NL-SYS system netlist CON-IP IP constraint information CON-SYS system constraint information CON1 conversion constraint information CON2 connection constraint information

Claims (9)

An LSI design system for designing an LSI at a system level by using design assets (IP),
A database for storing an IP group including a plurality of IPs;
A system construction unit connected to the database so as to be accessible;
A system constraint information generator connected to be accessible to the database;
A storage unit connected to the system construction unit and the system constraint information generation unit,
Each of the plurality of IPs has IP constraint information indicating design constraints used for LSI design verification,
The system construction unit generates a system netlist as a system level netlist determined by the plurality of combined IPs, and outputs the system netlist to the storage unit.
The system constraint information generation unit is configured at a system level depending on a combination of the plurality of IPs based on the system netlist stored in the storage unit and the plurality of IP constraint information included in each of the plurality of IPs. An LSI design system that generates system constraint information indicating design constraints and outputs the system constraint information to the storage unit. An LSI design system according to claim 1,
The system constraint information generation unit includes a hierarchy information conversion unit,
The hierarchy information conversion unit refers to the system netlist, converts IP level hierarchy information included in each of the plurality of IP restriction information into system level hierarchy information, and thereby converts the plurality of IP restriction information. An LSI design system that converts the system constraint information. An LSI design system according to claim 2,
The system constraint information generation unit further includes a connection constraint detection unit,
The connection constraint detection unit refers to the system netlist to generate connection constraint information indicating a system level design constraint depending on a connection relationship of the plurality of IPs, and the connection constraint information is used as the system constraint information. LSI design system to add to. An LSI design system according to claim 3,
The plurality of IPs includes a connection IP that is used for connection between IPs and in which a plurality of terminals are defined,
The LSI design system, wherein the connection constraint detection unit detects a false path between the plurality of terminals by referring to the system netlist, and generates the false path as the connection constraint information. An LSI design system according to claim 4, wherein
The connection IP has an extension program for detecting the false path in addition to the IP constraint information,
The LSI design system, wherein the connection constraint detection unit reads and executes the extension program from the database. An LSI design system according to any one of claims 1 to 5,
The LSI design system in which the IP constraint information, the connection constraint information, and the system constraint information indicate design constraints used for STA (Static Timing Analysis). An LSI design system according to claim 6,
An LSI design system further comprising an STA unit that executes STA based on the generated system netlist and the system constraint information. An LSI design program in an LSI design system for designing an LSI at a system level by using design assets (IP),
The LSI design system includes a database that stores an IP group including a plurality of IPs, and each of the plurality of IPs is a design constraint and has IP constraint information indicating a design constraint used for LSI design verification. And
(A) generating a system netlist as a system level netlist determined by the combined plurality of IPs;
(B) converting IP level hierarchical information included in each of the plurality of IP constraint information into system level hierarchical information by referring to the system netlist;
(C) generating a plurality of first constraint information as system level IP constraint information from the plurality of IP constraint information by using the system level hierarchy information;
(D) generating second constraint information indicating system level design constraints depending on the connection relation of the plurality of IPs by referring to the system netlist;
(E) generating the plurality of first constraint information and the second constraint information as system constraint information indicating system-level design constraints depending on a combination of the plurality of IPs. Design program. An LSI design program according to claim 8, wherein
(F) An LSI design program for causing a computer to further execute a step of executing STA (Static Timing Analysis) by using a design constraint indicated by the system constraint information.

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