JP4395737B2 - Analog / digital conversion circuit and conversion error measurement circuit - Google Patents

Description

  The present invention relates to an analog / digital conversion circuit and a conversion error measurement circuit that perform one conversion operation in a plurality of steps, such as a pipeline type analog / digital conversion circuit.

FIG. 5 is a diagram illustrating a configuration example of a general pipeline type analog / digital conversion circuit.
In the following description, words may be abbreviated as follows.
Analog / digital conversion: A / D conversion;
Digital / analog conversion: D / A conversion;

This pipeline type A / D conversion circuit has a plurality of stages of A / D conversion units U1,..., U2, U3 connected in cascade.
A / D conversion units U1,..., U2 before the last stage respectively perform A / D conversion on the residual signal (input signal Vin for the first stage unit U1) input from the preceding A / D conversion unit. A / D conversion circuit 1 for performing D / A conversion, D / A conversion circuit 2 for performing D / A conversion on the conversion result of the A / D conversion circuit 1, and D / A from an input residual signal (or input signal Vin) A subtraction circuit 3 that subtracts the conversion result of the conversion circuit 2 and an amplification circuit 4 that amplifies the subtraction result of the subtraction circuit 3 and outputs the result as a residual signal to the A / D conversion unit in the next stage.

  According to the above configuration, the digital conversion results D1,..., D2 and D3 obtained in the A / D conversion circuit 1 of each unit are most coarsely obtained in the first stage A / D conversion unit U1 and go to the subsequent stage. It becomes finer step by step. That is, a fine A / D conversion result of the input signal Vin is obtained by performing A / D conversion in a plurality of steps from the upper bit side to the lower bit side.

  Thus, in an A / D conversion circuit that performs one conversion operation in a plurality of steps, reducing the linearity error of the output signal with respect to the input signal is an issue in improving the conversion accuracy. The linearity error is mainly caused by the error of the part that returns the coarse A / D conversion result of each step to the analog signal. The main breakdown is the linearity error, full-scale error, error of the D / A conversion circuit. A gain error of the amplifier circuit can be cited.

In Non-Patent Document 1, etc., a plurality of fixed values are input to a D / A conversion circuit (for example, D / A conversion circuit 2 in FIG. 5) at each step, and an error amplification circuit (for example, amplification in FIG. There has been proposed a method for measuring the linearity error by appropriately calculating the A / D conversion result of the residual signal output from the circuit 4).
"Digital-Domain Calibration of Multistep Analog-to-Digital Converters", IEEE Journal of Solid State Circuits (IEEE Journal of Solid State Circuits), (USA), December 1992, Vol. 27, No. 12, p. 1679-1688

  However, in an actual system, fluctuations in the residual signal value are mixed due to circuit noise and system background noise, so that even if this is processed by the proposed method, a correct linearity error measurement value can be obtained. There is a problem that can not be.

If the fluctuation to be mixed is white noise, a measurement value close to the true error can be obtained by averaging a large number of measurement results, but actually, for example, flicker noise having a spectrum of 1 / f. In addition, fluctuations that are slightly synchronized with the system clock and are not completely random are also included, so there is a problem that the average error does not converge to the true error. In particular, in an A / D conversion circuit designed using a deep submicron CMOS process, the influence of flicker noise having a 1 / f spectrum and the low frequency of digital noise that cannot be ignored as the installed system becomes larger in scale There has been a problem that the accuracy of error measurement values is reduced due to random walk noise having a 1 / f ² spectrum due to fluctuations in the component surface and chip surface temperature that cannot be ignored with the increase in size of the mounted chip.

The present invention has been made in view of such circumstances, and an object thereof is to provide a conversion error measurement circuit of an A / D conversion circuit that can reduce the influence of low-frequency noise and improve measurement accuracy.
Another object of the present invention is to provide an A / D conversion circuit capable of improving the accuracy of A / D conversion using a conversion error measured with high accuracy while reducing the influence of low frequency noise. There is.

The first aspect of the present invention is a conversion error measurement circuit of an analog / digital conversion circuit.
The analog / digital conversion circuit has a plurality of stages of analog / digital conversion units that acquire fine digital values in stages from coarse digital values. The analog / digital conversion units before the final stage include: A digital / analog conversion circuit for converting the digital value acquired by the unit into an analog signal, and generating a residual signal corresponding to the signal obtained by subtracting the analog signal of the conversion result from the input signal to the unit And a residual signal generation circuit to be input to the next stage.
The conversion error measurement circuit outputs a digital signal of two values to the digital / analog conversion circuit included in at least one analog / digital conversion unit before the final stage among the plurality of stages. The difference between the two residual signals of the digital signal input circuit that alternately inputs with a shorter cycle than the noise component that can be a signal detection error and the two residual signal generation circuits corresponding to the two digital signals of the digital signal input circuit. A first difference detecting circuit for detecting, and a second for detecting a difference between an ideal value to be possessed by a difference between the two residual signals corresponding to the two digital signals and a detection result of the first difference detecting circuit. Difference detection circuit and an averaging circuit for averaging the detection results of the second difference detection circuit.

The operation of the first invention is as follows.
Among the plurality of stages of analog / digital conversion units, the digital / analog conversion circuit included in at least one analog / digital conversion unit before the final stage has a digital signal of two values by the digital signal input circuit. Are input alternately. The cycle in which the two digital signals are alternately input is set to a cycle shorter than a noise component that can be a detection error of the residual signal. The first difference detection circuit detects a difference between the two residual signals of the residual signal generation circuit corresponding to the two digital signals of the digital signal input circuit. The second difference detection circuit detects a difference between an ideal value that the difference between the two residual signals corresponding to the two digital signals should have and a detection result of the first difference detection circuit. Then, the detection result of the second difference detection circuit is averaged by the averaging circuit.
As a result, noise components having substantially the same magnitude are superimposed on the two residual signals whose differences are detected by the first difference detection circuit, and most of the noise components in the detection results of the differences are included. Offset. As a result, the averaging circuit can obtain a conversion error measurement value in which the influence of the noise component is reduced.

  The second invention of the present invention has a plurality of stages of analog / digital conversion units for acquiring fine digital values in stages from coarse digital values, and the analog / digital conversion units before the final stage include the unit. A digital / analog conversion circuit for converting the digital value acquired in step 1 to an analog signal, and a residual signal corresponding to the signal obtained by subtracting the analog signal of the conversion result from the input signal to the unit to generate the next stage In an error measurement mode for measuring an analog / digital conversion error, at least one analog of the plurality of stages before the last stage is included. For the digital / analog conversion circuit included in the digital / digital conversion unit, two values A digital signal input circuit that alternately inputs a digital signal at a cycle shorter than a noise component that can be a detection error of the residual signal, and the residual signal corresponding to the two digital signals of the digital signal input circuit in the error measurement mode. A first difference detection circuit for detecting a difference between the two residual signals of the difference signal generation circuit; and an ideal value that a difference between the two residual signals corresponding to the two digital signals should have in the error measurement mode. And a second difference detection circuit that detects a difference between the detection result of the first difference detection circuit and an averaging circuit that averages the detection result of the second difference detection circuit in the error measurement mode; In the conversion mode for executing analog / digital conversion, the analog / digital conversion unit of the plurality of stages is based on the average value obtained by the averaging circuit. And a correction circuit for correcting the Tsu City of conversion results

The operation of the second invention is as follows.
In the error measurement mode, the digital / analog conversion circuit included in at least one analog / digital conversion unit before the final stage among the plurality of stages of analog / digital conversion units is connected by the digital signal input circuit. Two values of digital signals are input alternately. The cycle in which the two digital signals are alternately input is set to a cycle shorter than a noise component that can be a detection error of the residual signal. The first difference detection circuit detects a difference between the two residual signals of the residual signal generation circuit corresponding to the two digital signals of the digital signal input circuit. The second difference detection circuit detects a difference between an ideal value that the difference between the two residual signals corresponding to the two digital signals should have and a detection result of the first difference detection circuit. Then, the detection result of the second difference detection circuit is averaged by the averaging circuit.
Next, when the conversion mode is entered, the conversion results of the analog / digital conversion units of the plurality of stages are corrected by the correction circuit based on the average value obtained by the averaging circuit.
As a result, noise components having substantially the same magnitude are superimposed on the two residual signals whose differences are detected by the first difference detection circuit, and most of the noise components in the detection results of the differences are included. Offset. As a result, in the averaging circuit, a conversion error measurement value in which the influence of the noise component is reduced is obtained, and the conversion result of the plurality of stages of analog / digital conversion units is accurately corrected based on the conversion error measurement value. The

  In the first and second aspects of the invention, the digital signal input circuit switches the digital signal input to the digital / analog conversion circuit every cycle in which the analog / digital conversion unit executes analog / digital conversion. May be performed.

  The first difference detection circuit converts the two residual signals of the residual signal generation circuit corresponding to the two digital signals of the digital signal input circuit into an analog / digital conversion unit in the subsequent analog / digital conversion unit. The difference between the two digital signals obtained in this way may be detected.

  Further, the first and second inventions may include an analog signal input circuit for inputting an analog signal of a certain level to the analog / digital conversion unit. Thereby, the difference from the ideal value is detected with high accuracy in the second difference detection circuit.

  In the error measurement mode, the second aspect of the invention relates to each of or one of two values of a digital signal input to the digital / analog conversion circuit and the digital signal having the two values. A storage circuit may be provided which stores the average value of the averaging circuit in association with each other and reads out the storage data of the average value associated with the digital signal input to the digital / analog conversion circuit in the conversion mode. The correction circuit may perform the correction based on an average value read from the storage circuit.

According to the present invention, the influence of low-frequency noise such as flicker noise can be reduced, and the conversion error of A / D conversion can be accurately measured.
Further, the accuracy of A / D conversion can be improved by correcting the conversion result using the conversion error measured with high accuracy while reducing the influence of low frequency noise.

  Hereinafter, three embodiments of the present invention will be described with reference to the drawings.

<First Embodiment>
FIG. 1 is a diagram illustrating an example of a configuration of an A / D conversion circuit according to the first embodiment of the present invention.

The A / D conversion circuit illustrated in FIG. 1 includes an A / D conversion unit 10, a digital signal generation circuit 20, a conversion error calculation circuit 30, a storage circuit 40, and a correction circuit 50.
The A / D conversion unit 10 includes an A / D conversion circuit 12, a selection circuit 13, a D / A conversion circuit 11, a subtraction circuit 14, an amplification circuit 15, an A / D conversion circuit 16, and a conversion result output. Circuit 17.
The conversion error calculation circuit 30 includes registers 31 and 32, subtraction circuits 33 and 34, and an averaging circuit 35.

The digital signal generation circuit 20 and the selection circuit 13 are an embodiment of the digital signal input circuit of the present invention.
The subtraction circuit 33 is an embodiment of the first difference detection circuit of the present invention.
The subtraction circuit 34 is an embodiment of the second difference detection circuit of the present invention.
The averaging circuit 35 is an embodiment of the averaging circuit of the present invention.
The memory circuit 40 is an embodiment of the memory circuit of the present invention.

  First, each of these components will be described.

The A / D converter 10 performs A / D conversion of the input signal Vin and outputs a digital signal S17 as a conversion result to the correction circuit 50.
The A / D conversion unit 10 has a two-stage A / D conversion unit that obtains a fine digital value step by step from a coarse digital value. The first stage A / D conversion unit is an A / D conversion circuit. 12, a selection circuit 13, a D / A conversion circuit 11, a subtraction circuit 14, and an amplification circuit 15, and a second-stage A / D conversion unit is formed of an A / D conversion circuit 16.

  The A / D conversion circuit 12 performs A / D conversion on the input signal Vin and outputs a digital signal S12 as a conversion result.

  The selection circuit 13 selects either the digital signal S12 output from the A / D conversion circuit 12 or the digital signal S20 generated in the digital signal generation circuit 20, and outputs the selected signal to the D / A conversion circuit 11.

The A / D conversion circuit shown in FIG. 1 has a conversion mode for executing A / D conversion and an error measurement mode for measuring an A / D conversion error as operation modes.
The selection circuit 13 selects and outputs the digital signal S12 in the conversion mode, and selects and outputs the digital signal S20 in the error measurement mode.

  The D / A conversion circuit 11 performs D / A conversion on the digital signal output from the selection circuit 13 and outputs the conversion result to the subtraction circuit 14.

The subtracting circuit 14 subtracts the analog signal converted by the D / A converting circuit 11 from the input signal Vin.
The amplification circuit 15 amplifies the subtraction result of the subtraction circuit 14 and outputs the result as an analog residual signal S15 to the A / D conversion circuit 16 which is an A / D conversion unit at the next stage.
The circuit including the subtraction circuit 14 and the amplification circuit 15 is an embodiment of the residual signal generation circuit of the present invention.

  The A / D conversion circuit 16 performs A / D conversion of the analog residual signal S15 output from the preceding A / D conversion unit, and outputs a digital residual signal S16.

  The conversion result output circuit 17 performs processing such as error correction on the digital signals S12 and S16 obtained by the two A / D conversion units, and calculates and outputs the A / D conversion result S17 of the input signal Vin.

In the error measurement mode, the digital signal generation circuit 20 alternately generates two values of the digital signal S20 and outputs them to the selection circuit 13. However, the cycle in which the signals are alternately generated is shorter than the cycle in which the digital residual signal S16 input to the conversion error calculation circuit 30 fluctuates due to low frequency noise (such as flicker noise or low frequency components of digital noise). Set to period.
For example, assuming that the execution of A / D conversion in the A / D conversion unit 10 is synchronized with the clock signal AD_CLK, the digital signal generation circuit 20 uses the 1 of the clock signal AD_CLK whose cycle is sufficiently shorter than the above-described low frequency noise. The value of the digital signal S20 is switched every cycle.

  The conversion error calculation circuit 30 calculates an A / D conversion error S35 based on the residual digital signal S16 output from the A / D conversion circuit 16 and outputs it to the storage circuit 40 in the error measurement mode.

The registers 31 and 32 hold two-value residual signals S16 corresponding to the two-value digital signals S20 generated by the digital signal generation circuit 20, respectively.
For example, assuming that the digital signal S20 having the value '# 1' and the value '# 2' is alternately generated in the digital signal generation circuit 20, the register 31 has a residual when the digital signal S20 has the value '# 1'. The signal S16 is held, and the register 32 holds the residual signal S16 when the digital signal S20 has the value '# 2'.

  The subtraction circuit 33 detects a difference S33 between the two residual signals S16 held in the registers 31 and 32.

  The subtraction circuit 34 has an ideal value Sd that should have a difference between the two-value residual signal S16 corresponding to the two-value digital signal S20 generated by the digital signal generation circuit 20 and the actual value detected by the subtraction circuit 33. A difference from the value S33 is detected.

The averaging circuit 35 averages the difference between the ideal value Sd detected by the subtraction circuit 34 and the actual value S33, and outputs the result as a conversion error measurement result S35.
The averaging circuit 35 has, for example, an integration circuit, and outputs a result obtained by integrating a predetermined number of data output from the subtraction circuit 34 as a conversion error measurement result S35.

In the error measurement mode, the storage circuit 40 receives each or one of two values of the digital signal S20 input to the D / A conversion circuit 11 and a conversion error measurement result S35 corresponding to the digital signal S20 having the two values. Are stored in association with each other.
For example, each or one of two values of the digital signal S20 generated in the digital signal generation circuit 20 is input as a write address, and the conversion error measurement result S35 is written to this address.

Further, the storage circuit 40 reads out stored data of the conversion error measurement result associated with the digital signal S12 based on the digital signal S12 input to the D / A conversion circuit 11 in the conversion mode, and this is read out by the correction circuit 50. Output to.
For example, the digital signal S12 of the A / D conversion circuit 12 input to the D / A conversion circuit 11 is input as a read address, and the conversion error measurement result stored at this address is read.

  The correction circuit 50 corrects the conversion result S17 of the A / D conversion unit 10 based on the conversion error measurement result S40 read from the storage circuit 40 in the conversion mode. Since the conversion error measurement result S40 is a value indicating a deviation from the ideal value, for example, by adding or subtracting it to the conversion result S17 of the A / D conversion unit 10, a conversion in which the deviation from the ideal value is corrected is performed. The result DAT can be obtained.

  Here, the operation of the A / D conversion circuit shown in FIG. 1 having the above-described configuration will be described.

In the error measurement mode, the digital signal S20 generated by the digital signal generation circuit 20 is input to the D / A conversion circuit 11.
Further, the digital signal S20 is alternately set to two predetermined values every cycle shorter than the low frequency noise such as flicker noise, for example, every cycle of the clock signal AD_CLK. At this time, if the input signal Vin is fixed to a constant value, the digital residual signal S16 output from the A / D conversion circuit 16 has two values as shown in FIG.

FIG. 2 is a diagram illustrating an example of the relationship between the residual signal S16 and the input signal Vin. The horizontal axis indicates the input signal Vin, and the vertical axis indicates the residual signal S16.
In the graph shown in FIG. 2, the thin line portion indicates the change in the residual signal S16 when an arbitrary value is input to the D / A conversion circuit 11, and the thick line portion indicates the A / D. The range that the residual signal S16 can take in the actual conversion operation (that is, in the conversion mode) is shown.
When the input signal Vin is made constant and the input signal of the D / A conversion circuit 11 is set to two values, as shown in FIG. 2, a two-value residual signal S16 having a difference corresponding to the two values is obtained. can get.

The residual signal S16 of these two values is held in the registers 31 and 32, respectively, and then the difference S33 between them is detected by the subtraction circuit 33. Further, the difference S33 is detected by the subtraction circuit 34 as an error S34 from the ideal value Sd. Then, the detected error S34 is averaged by the averaging circuit 35, thereby obtaining an A / D conversion error measurement result S35.
In the storage circuit 40, the conversion error measurement result S35 obtained as described above and the value of the digital signal S20 corresponding thereto are stored in association with each other. For example, as shown in FIG. 1, two values of the digital signal S20 are alternately input to the storage circuit 40 as a write address, and the conversion error measurement result S35 is written to this address.

  In the error measurement mode, the digital signal generation circuit 20 inputs all values of the digital signal S20 that can be input from the A / D conversion circuit 12 to the D / A conversion circuit 11 in the conversion mode, for example. The Then, the conversion error measurement result S35 corresponding to each digital value is written in the storage circuit 40.

Next, when the operation mode is set to the conversion mode, the selection circuit 13 selects the conversion result S12 of the A / D conversion circuit 12 and inputs it to the D / A conversion circuit 11. Thereby, A / D conversion of the input signal Vin is executed in the A / D converter 10.
That is, in the A / D conversion unit at the first stage, the A / D conversion circuit 12 performs A / D conversion of the input signal Vin to obtain the digital signal S12. Further, the digital signal S12 is converted back to an analog signal by the D / A conversion circuit 11, and the analog signal is subtracted from the input signal Vin by the subtraction circuit 14. Further, the subtraction result is amplified by the amplification circuit 15 with a predetermined gain. As a result, a residual signal S15 is obtained. In the second stage A / D conversion unit, A / D conversion is performed on the residual signal S15 output from the first stage to obtain a digital signal S16. In this way, the digital signals S12 and S16 obtained by the two-stage A / D conversion unit are processed by the conversion result output circuit 17, whereby the A / D conversion result S17 of the input signal Vin is obtained.

On the other hand, the storage circuit 40 receives the conversion result S12 of the A / D conversion circuit 12 input to the D / A conversion circuit 11, for example, as a read address, and stores the conversion error measurement result S40 stored at this address. Read from circuit 40. That is, the measurement result of the conversion error corresponding to the data value input to the D / A conversion circuit 11 is read from the storage circuit 40.
The read conversion error measurement result S40 is input to the correction circuit 50 together with the conversion result S17 of the A / D converter 10. In the correction circuit 50, the conversion result S17 of the A / D conversion unit 10 is corrected based on the conversion error measurement result S40, thereby obtaining the conversion result DAT in which the deviation from the ideal value is corrected.

  Next, the reason why the influence of low frequency noise is reduced in the A / D conversion circuit shown in FIG.

  When the two detected values of the residual signal S16 corresponding to the two values switched by the digital signal generation circuit 20 are expressed as ‘D1’ and ‘D2’, respectively, the two have the following relationship.

[Equation 1]
D2 = D1 + Did + Derr (1)

Here, “Did” represents an ideal residual step value. 'Derr' represents an error in the residual step value caused by the circuit characteristics, that is, a conversion error to be measured.
Consider a case where an external noise component n (t) is superimposed on the detection values D1 and D2 of the residual signal S16 when such a circuit-specific conversion error is present. The detection values D1A and D2A on which the noise component is superimposed are expressed as follows.

[Equation 2]
D1A = D1 + n (t1) (2)
D2A = D2 + n (t1 + tper) (3)

Here, 't1' represents the time when the detection value D1 was sampled. 'Tper' represents a cycle for switching the value of the digital signal S20 in the digital signal generation circuit 20.
The conversion error measurement result for one sample is obtained by obtaining the difference S33 between the detection values D1A and D2A in the subtraction circuit 33 and further detecting the difference between the difference S33 and the residual step ideal value Did (= Sd). . A result obtained by averaging this over a plurality of samples is a conversion error measurement result S35. The conversion error measurement result Err for one sample before the averaging process is expressed by the following equation.

[Equation 3]
Err = D2A-D1A-Did
= Derr + n (t1 + tper) -n (t1) (4)

  As described above, since the switching period tper of the value of the digital signal S20 is set to be sufficiently shorter than the fluctuation period of the noise component, as shown in the following equation, the noise separated by the time interval 'tper' The components 'n (t1 + tper)' and 'n (t1)' are almost equal.

[Equation 4]
n (t1 + tper) ≒ n (t1)
n (t1 + tper) −n (t1) ≈0 (5)

  Therefore, the conversion error measurement result Err for one sample shown in Expression (4) is hardly influenced by the noise component. This means that a filter effect for low-frequency noise can be obtained by obtaining the difference between the detection values D1 and D2 of the residual signal S16.

As described above, according to the present embodiment, in the digital signal generation circuit 20, the two values of the digital signal S20 are switched at a relatively fast cycle, for example, every clock cycle of A / D conversion. The subtraction circuit 33 detects the difference S33 of the digitally converted residual signal S16 output from the A / D conversion circuit 16 corresponding to each of the above. Further, an error between the difference S33 and the ideal value Sd is detected by the subtracting circuit 34, and the detection result is averaged by the averaging circuit 35, whereby an A / D conversion error measurement result S35 is obtained.
Thereby, in the difference S33 of the residual signal S16, a noise component that changes more slowly than the switching cycle of the digital signal generation circuit 20 can be canceled out, so that fluctuation due to the noise can be greatly reduced. As a result, the conversion error measurement result S35 obtained based on the difference S33 is also hardly affected by noise, and the measurement accuracy of the A / D conversion error can be greatly improved. Further, since the measurement accuracy of the A / D conversion error is improved, the correction accuracy by the correction circuit 50 using the error is also improved, so that the overall A / D conversion accuracy can be improved.

<Second Embodiment>
Next, a second embodiment of the present invention will be described.

FIG. 3 is a diagram illustrating an example of a configuration of an A / D conversion circuit according to the second embodiment of the present invention.
The A / D conversion circuit shown in FIG. 3 has the same configuration as that of the A / D conversion circuit shown in FIG. 1, and the analog signal input of the present invention is input to the portion where the input signal Vin is input to the A / D conversion unit 10. An analog signal input circuit 60, which is an embodiment of the circuit, is inserted.

The analog signal input circuit 60 is a circuit that inputs an analog signal of a certain level to the A / D converter 10 in the error measurement mode, and includes a switch circuit 61 and an analog signal source 62 as shown in FIG. 3, for example. .
The switch circuit 61 inputs an analog signal generated by the analog signal source 62 to the A / D converter 10 in the error measurement mode, and inputs an input signal Vin supplied from the outside to the A / D converter 10 in the conversion mode. input.
The analog signal source 62 generates, for example, a constant level voltage and outputs it to the switch circuit 61.

  According to the configuration described above, since the input signal level of the A / D conversion unit 10 can be kept constant in the error measurement mode, the conversion error measurement accuracy can be improved. In addition, since the analog signal input circuit 60 is formed on the same semiconductor chip as the A / D conversion unit 10, it can be made less susceptible to external noise, thereby further improving the conversion error measurement accuracy. it can.

<Third Embodiment>
Next, a third embodiment of the present invention will be described.

FIG. 4 is a diagram illustrating an example of a configuration of an A / D conversion circuit according to the third embodiment of the present invention.
The A / D conversion circuit shown in FIG. 4 includes an A / D conversion unit 10B, digital signal generation circuits 20-1 and 20-2, conversion error calculation circuits 30-1 and 30-2, and a storage circuit 40-1. 40-2, a correction circuit 50B, and analog signal input circuits 60-1 and 60-2.
The A / D conversion unit 10B includes A / D conversion circuits 12-1 and 12-2, selection circuits 13-1 and 13-2, D / A conversion circuits 11-1 and 11-2, and a subtraction circuit 14. -1 and 14-2, amplifier circuits 15-1 and 15-2, an A / D conversion circuit 16, and a conversion result output circuit 17B.
The conversion error calculation circuit 30-1 includes registers 31-1 and 32-1, subtraction circuits 33-1 and 34-1 and an averaging circuit 35-1.
The conversion error calculation circuit 30-2 includes registers 31-2 and 32-2, subtraction circuits 33-2 and 34-2, and an averaging circuit 35-2.

  First, each of these components will be described.

The A / D conversion unit 10B performs A / D conversion of the input signal Vin and outputs a digital signal S17B as a conversion result to the correction circuit 50B.
The A / D conversion unit 10B has a three-stage A / D conversion unit that acquires a fine digital value stepwise from a coarse digital value.
The first-stage (first-stage) A / D conversion unit includes an A / D conversion circuit 12-1, a selection circuit 13-1, a D / A conversion circuit 11-1, a subtraction circuit 14-1, and an amplification circuit 15-1. Composed.
The second stage A / D conversion unit includes an A / D conversion circuit 12-2, a selection circuit 13-2, a D / A conversion circuit 11-2, a subtraction circuit 14-2, and an amplification circuit 15-2. .
The third-stage (final stage) A / D conversion unit includes an A / D conversion circuit 16.

Of these three A / D conversion units, the first and second A / D conversion units have the same configuration as the first stage unit of the A / D conversion unit 10 described above. It works in the same way.
That is, the A / D conversion circuit 12-n (n represents an integer of 1 or 2; the same applies hereinafter), the selection circuit 13-n, the D / A conversion circuit 11-n, the subtraction circuit 14-n, and FIG. The amplifier circuit 15-n corresponds to the A / D conversion circuit 12, the selection circuit 13, the D / A conversion circuit 11, the subtraction circuit 14, and the amplification circuit 15 in FIG.
As for the operation, both the first-stage and second-stage A / D conversion units perform A / D conversion on the input signal to the unit and output the conversion result to the correction circuit 50B. The conversion result is D / A converted into an analog signal, subtracted from the input signal to the unit, and the subtraction result is amplified by a predetermined gain and output to the next stage. This operation is the same as that of the first stage unit of the A / D conversion unit 10 in FIG.

  The A / D conversion circuit 16 which is the third stage A / D conversion unit A / D converts the residual signal output from the second stage A / D conversion unit, and the digital signal S16 obtained thereby is converted. Is output to the conversion result output circuit 17B.

  The conversion result output circuit 17B includes digital signals S12-1 and S12-2 obtained by the first and second A / D conversion units, and a digital signal S16 obtained by the third A / D conversion unit. Are subjected to processing such as error correction, and the A / D conversion result S17B of the input signal Vin is calculated and output.

In the error measurement mode, the digital signal generation circuit 20-n alternately generates two-value digital signals S20-n and outputs them to the selection circuit 13-n. However, the signal value switching cycle is set smaller than the noise component fluctuation cycle.
The operation of the digital signal generation circuit 20-n is the same as that of the digital signal generation circuit 20 described above.

The conversion error calculation circuit 30-n calculates a conversion error S35-n based on the A / D conversion result of the residual signal in the (n + 1) -th A / D conversion unit, and outputs it to the storage circuit 40-n. To do.
That is, the conversion error calculation circuit 30-1 calculates the conversion error S35-1 based on the digital residual signal S12-2 that is the conversion result of the A / D conversion circuit 12-2. The conversion error calculation circuit 30-2 calculates a conversion error S35-2 based on the digital residual signal S16 that is the conversion result of the A / D conversion circuit 16.

The conversion error calculation circuit 30-n has the same configuration as the conversion error calculation circuit 30 described above, and operates in the same manner.
That is, the registers 31-n and 32-n, the subtraction circuits 33-n and 34-n, and the averaging circuit 35-n are replaced with the registers 31 and 32, the subtraction circuits 33 and 34, and the averaging circuit 35 in FIG. It corresponds.
In terms of operation, the conversion error calculation circuit 30-n detects a difference between two residual signal values corresponding to two signal values alternately set by the digital signal generation circuit 20-n. The difference between the detected value and the ideal value is detected, and the difference from the detected ideal value is averaged to calculate the measurement result of the A / D conversion error. This operation is the same as that of the conversion error calculation circuit 30 in FIG.

In the error measurement mode, the memory circuit 40-n includes each or one of the two values of the digital signal S20-n input to the D / A conversion circuit 11-n and the digital signal S20-n having the two values. Is stored in association with the conversion error measurement result S35-n corresponding to.
Further, the storage circuit 40-n stores stored data of conversion error measurement results associated with the digital signal S12-n based on the digital signal S12-n input to the D / A conversion circuit 11-n in the conversion mode. Is output to the correction circuit 50B.
The operation of the memory circuit 40-n is the same as that of the memory circuit 40 described above.

  The correction circuit 50B corrects the conversion result S17B of the A / D conversion unit 10B based on the conversion error measurement results S40-1 and 40-2 read from the storage circuits 40-1 and 40-2 in the conversion mode. Since the conversion error measurement results S40-1 and 40-2 are both values indicating deviation from the ideal value, for example, by adding or subtracting them to the conversion result S17B of the A / D conversion unit 10B, the ideal value The conversion result DAT in which the deviation from is corrected can be obtained.

The analog signal input circuit 60-n is a circuit for inputting an analog signal of a certain level to the n-th A / D conversion unit of the A / D conversion unit 10B in the error measurement mode, for example, as shown in FIG. As described above, the switch circuit 61-n and the analog signal source 62-n are included.
The switch circuit 61-n inputs an analog signal generated by the analog signal source 62-n to the n-th unit of the A / D converter 10B in the error measurement mode, and inputs to the n-th unit in the conversion mode. A signal (first stage unit: input signal Vin, second stage unit: residual signal of the first stage unit) is input.
The analog signal source 62-n generates, for example, a constant level voltage and outputs it to the switch circuit 61-n.

According to the A / D conversion circuit shown in FIG. 4 having the above-described configuration, in the error measurement mode, each of the first and second A / D conversion units of the A / D conversion circuit has a certain level of analog. A signal is input, and a digital signal S20-n whose value is alternately switched in a cycle shorter than noise is input to the D / A conversion circuit 11-n in each unit.
Accordingly, the A / D conversion error measurement result S35-n of the n-th stage A / D conversion unit with high accuracy in which the influence of noise is reduced by the same operation as the A / D conversion circuit shown in FIG. Is calculated and stored in the storage circuit 40-n.
Next, when the operation mode is set to the conversion mode, the input signal Vin is input to the first-stage A / D conversion unit, and the remaining signal from the first stage is input to the second-stage A / D conversion unit. The difference signal is input. Also, the conversion result of the corresponding A / D conversion circuit 12-n is input to the D / A conversion circuit 11-n of each unit. Thereby, A / D conversion of the input signal Vin is performed in the A / D conversion unit 10B.
At this time, the conversion result S12-n of the A / D conversion circuit 12-n input to the D / A conversion circuit 11-n is input to the memory circuit 40-n as, for example, a read address, and the memory circuit 40-n responds accordingly. Conversion error measurement result S40-n is read out.
The read conversion error measurement results S40-1 and S40-2 are input to the correction circuit 50B together with the conversion result S17B of the A / D conversion unit 10B. In the correction circuit 50B, the conversion result S17B of the A / D conversion unit 10B is corrected based on the conversion error measurement results S40-1 and S40-2, and thereby the deviation from the ideal value is corrected with high accuracy. A conversion result DAT is obtained.

  Thus, even when the A / D conversion unit has three stages, it is possible to accurately measure the A / D conversion error in each of the first and second stage units. Moreover, it is possible to improve the accuracy of A / D conversion by correcting the entire A / D conversion result S17B using this measurement result.

As mentioned above, although several embodiment of this invention was described, this invention is not limited only to these forms, Various modifications are included.
For example, in the correction circuits 50 and 50B, an operation mode for outputting the measurement result of the A / D conversion error as it is may be provided so that the measurement result can be used for discrimination between a non-defective product and a defective product. Alternatively, an operation mode for directly outputting the A / D conversion results S17 and S17B before correction may be provided. These circuits can be easily realized by ordinary logical operations.

  In the above-described embodiment, the case where the A / D conversion unit has two stages and the case where the A / D conversion unit has three stages has been described. That is, even when there are four or more A / D conversion units, it is possible to measure the A / D conversion error of each unit with high accuracy by using the same configuration as described above. High A / D conversion results can be obtained.

It is a figure which shows an example of a structure of the analog / digital conversion circuit which concerns on 1st Embodiment. It is a figure which shows an example of the relationship between a residual signal and an input signal. It is a figure which shows an example of a structure of the analog / digital conversion circuit which concerns on 2nd Embodiment. It is a figure which shows an example of a structure of the analog / digital conversion circuit which concerns on 3rd Embodiment. It is a figure which shows the structural example of a general pipeline type analog / digital conversion circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10, 10B ... A / D conversion part, 12, 12-1, 12-2, 16 ... A / D conversion circuit, 13, 13-1, 13-2 ... Selection circuit, 11, 11-1, 11-2 ... D / A conversion circuit, 14, 14-1, 14-2 ... Subtraction circuit, 15, 15-1, 15-2 ... Amplification circuit, 17, 17B ... Conversion result output circuit, 20, 20-1, 20- 2... Digital signal generation circuit 30, 30-1, 30-2 ... Conversion error calculation circuit 31, 31-1, 31-2, 32, 32-1, 32-2. 33-2, 34, 34-1, 34-2 ... subtraction circuit, 35, 35-1, 35-2 ... averaging circuit, 40, 40-1, 40-2 ... storage circuit, 50, 50B ... correction circuit , 60, 60-1, 60-2... Analog signal input circuit

Claims (9)

It has a multi-stage analog / digital conversion unit that acquires fine digital values in steps from coarse digital values. The analog / digital conversion unit in front of the last stage has the above digital values acquired by the unit as an analog signal. A digital / analog conversion circuit that converts the analog signal of the conversion result to a signal obtained by subtracting an analog signal of the conversion result from the input signal to the unit, A conversion error measurement circuit for an analog / digital conversion circuit, including:
Among the plurality of stages, a noise that may cause a detection error of the residual signal from a digital signal of two values with respect to the digital / analog conversion circuit included in at least one analog / digital conversion unit before the final stage. A digital signal input circuit that alternately inputs in a shorter cycle than the component;
A first difference detection circuit for detecting a difference between two residual signals of the residual signal generation circuit corresponding to two digital signals of the digital signal input circuit;
A second difference detection circuit that detects a difference between an ideal value that the difference between the two residual signals corresponding to the two digital signals should have and a detection result of the first difference detection circuit;
An averaging circuit for averaging the detection results of the second difference detection circuit;
A conversion error measuring circuit. The digital signal input circuit switches a digital signal to be input to the digital / analog conversion circuit every cycle in which the analog / digital conversion unit executes analog / digital conversion.
The conversion error measuring circuit according to claim 1. The first difference detection circuit performs analog / digital conversion on the two residual signals of the residual signal generation circuit corresponding to the two digital signals of the digital signal input circuit in the analog / digital conversion unit in the subsequent stage. Detecting the difference between two resulting digital signals;
The conversion error measuring circuit according to claim 1. An analog signal input circuit for inputting an analog signal of a certain level to the analog / digital conversion unit;
The conversion error measuring circuit according to claim 1. It has a multi-stage analog / digital conversion unit that acquires fine digital values in steps from coarse digital values. The analog / digital conversion unit in front of the last stage has the above digital values acquired by the unit as an analog signal. A digital / analog conversion circuit that converts the analog signal of the conversion result to a signal obtained by subtracting an analog signal of the conversion result from the input signal to the unit, An analog / digital conversion circuit including:
In an error measurement mode for measuring an analog / digital conversion error, two values of digital are compared with the digital / analog conversion circuit included in at least one analog / digital conversion unit before the final stage among the plurality of stages. A digital signal input circuit that alternately inputs a signal at a cycle shorter than a noise component that can be a detection error of the residual signal;
A first difference detection circuit for detecting a difference between the two residual signals of the residual signal generation circuit corresponding to the two digital signals of the digital signal input circuit in the error measurement mode;
In the error measurement mode, a second difference detection circuit that detects a difference between an ideal value that the difference between the two residual signals corresponding to the two digital signals should have and a detection result of the first difference detection circuit. When,
An averaging circuit for averaging the detection results of the second difference detection circuit in the error measurement mode;
A correction circuit for correcting the conversion results of the analog / digital conversion units of the plurality of stages based on an average value obtained by the averaging circuit in a conversion mode for performing analog / digital conversion;
An analog / digital conversion circuit. In the error measurement mode, each or one of the two values of the digital signal input to the digital / analog conversion circuit is associated with the average value of the averaging circuit corresponding to the digital signal of the two values. A storage circuit that reads out the storage data of the average value associated with the digital signal input to the digital / analog conversion circuit in the conversion mode;
The correction circuit performs the correction based on an average value read from the storage circuit.
The analog / digital conversion circuit according to claim 5. The digital signal input circuit switches a digital signal input to the digital / analog conversion circuit every cycle in which the analog / digital conversion unit performs analog / digital conversion in the error measurement mode.
The analog / digital conversion circuit according to claim 5. The first difference detection circuit performs analog / digital conversion on the two residual signals of the residual signal generation circuit corresponding to the two digital signals of the digital signal input circuit in the analog / digital conversion unit in the subsequent stage. Detecting the difference between two resulting digital signals;
The analog / digital conversion circuit according to claim 5. In the error measurement mode, an analog signal input circuit for inputting an analog signal of a certain level to the analog / digital conversion unit is provided.
The analog / digital conversion circuit according to claim 5.

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