JP5351569B2 - Pipeline type A / D conversion circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a pipeline type A/D conversion circuit with a conversion error correction circuit capable of highly accurate conversion error estimation and correction in a relatively short period of time with extremely high convergence when calculating an error estimation value. <P>SOLUTION: The conversion error correction circuit includes: an arithmetic circuit for generating a digital code by adding a sub digital code obtained by subtracting a known test signal from the sub digital code of a sub A/D converter of an error correction object and the sub digital code of the sub A/D converter of a poststage including the error component of the sub A/D converter of the error correction object; an error correction A/D converter for A/D converting analog input signals; a subtractor for subtracting the output of the error correction A/D converter from the output of the arithmetic circuit; a multiplier for multiplying the output of the subtractor by the test signals; a long-time averaging circuit for long-time averaging the output of the multiplier and calculating the error estimation value of A/D conversion in the sub A/D converter of the error correction object; and a correction circuit using the output to correct the component of the error of the A/D conversion included in the digital code output from the arithmetic circuit. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a pipeline type A / D conversion circuit having a background type conversion error correction circuit that self-corrects a conversion error in the background while performing A (analog) / D (digital) conversion. .

  First, the principle of the pipeline type A / D conversion circuit will be described.

  FIG. 7 is a block conceptual diagram showing the configuration of a pipeline type A / D conversion circuit. The pipeline type A / D conversion circuit sequentially converts an analog input signal into a digital code having a predetermined number of bits step by step for each predetermined number of bits (sub-digital code) from the most significant bit side of the digital code. The pipeline type A / D conversion circuit 100 shown in FIG. 1 includes an A / D conversion circuit main body 102 and a decoder 104.

  Here, the A / D conversion circuit main body 102 is configured by connecting ten sub A / D converters 106 in cascade, and each sub A / D converter 106 outputs a 1-bit sub digital code. Shall. That is, the A / D conversion circuit 100 has a 10-bit precision, and the decoder 104 outputs a 10-bit digital code obtained by A / D converting an analog input signal.

  Each sub A / D converter 106 has the same configuration. As shown in FIG. 7, the configuration of the second stage sub A / D converter 106, the A / D conversion unit 110, and the D / A conversion The unit 112, a subtractor 116, and an amplifier 118 are included.

  In the sub A / D converter 106, the A / D conversion unit 110 converts a partial voltage of the analog surplus signal of the previous stage sub A / D converter 106 into a sub digital code of each stage, The analog signal is reconverted by the D / A conversion unit 112. Subsequently, the subtracter 116 subtracts the voltage of the analog signal after the reconversion from the voltage of the analog surplus signal of the sub-A / D converter 106 at the previous stage, and amplifies this by a factor of two by the amplifier 118 to Output as an analog surplus signal.

  Here, if the number of bits of the sub digital code converted by the sub A / D converter 106 is m, the gain of the amplifier 118 is 2 ^ m. In this example, since the sub-digital code of each stage is 1 bit, the gain of the amplifier 118 is 2.

  Note that an analog input signal to be converted into a digital code is input to the first stage sub A / D converter 106 instead of the analog surplus signal of the previous stage sub A / D converter 106. Further, it is not necessary to output an analog surplus signal from the sub A / D converter 106 at the final stage. In other words, the final stage sub A / D converter 106 uses the total voltage of the analog surplus signal of the previous stage sub A / D converter 106 (the voltage corresponding to the least significant bit of the digital code) as the final stage sub digital code. Convert to

  In the pipeline type A / D conversion circuit 100, the voltage of the analog input signal is sequentially converted into the sub digital code step by step from the most significant bit side of the digital code by 10 sub A / D converters 106. To do.

  That is, first, the sub-A / D converter 106 at the first stage converts a part of the voltage of the analog input signal (the voltage corresponding to the most significant bit of the digital code) into the sub-digital code at the first stage. The first stage analog surplus signal is also output from the first stage sub A / D converter 106.

  Subsequently, the second-stage sub A / D converter 106 converts a partial voltage of the first-stage analog surplus signal (voltage corresponding to the second bit from the most significant bit of the digital code) to the second-stage sub-A / D converter 106. Convert to digital code. In the same manner, a partial voltage (voltage corresponding to each bit of the digital code) of the analog surplus signal of the previous stage is sequentially obtained bit by bit to the sub A / D converter 106 of the third to ninth stages. Convert to sub-digital code for each stage.

  Finally, the sub-A / D converter 106 at the final stage converts all voltages of the analog surplus signal at the previous stage (the ninth stage) (voltage corresponding to the least significant bit of the digital code) into the sub-digital code at the final stage. Convert.

  The sub-digital code of each stage output from the sub-A / D converter 106 of the first stage to the last stage is input to the decoder 104. The decoder 104 generates and outputs a 10-bit digital code corresponding to the analog input signal from the sub-digital code of each stage.

  As described above, the pipeline type A / D conversion circuit has a configuration in which a plurality of sub A / D converters are connected in cascade, and the analog input voltage is converted to the most significant bit side by these sub A / D converters. Will be digitized step by step.

  The sub A / D converter serves to separate the analog input signal into a sub-digital code at each stage and an analog surplus signal at each stage. The analog surplus signal of each stage is converted into a sub-digital code of that stage by the sub-A / D converter of the subsequent stage, and the analog surplus signal of that stage is further passed to the sub-A / D converter of the subsequent stage. Is repeated until the digital code obtained reaches the desired number of digits.

  In a pipelined A / D conversion circuit with high precision (requiring a large number of digits in the converted digital code), non-ideality (from the target gain) that exists in each stage of the sub A / D converter It is conceivable that an error exceeding the allowable range occurs in the digital code after A / D conversion due to the deviation of the error. Therefore, many techniques for self-correcting those errors have been proposed so far.

  An outline of a conventional pipelined A / D conversion circuit that self-corrects conversion errors in the background will be described below.

  FIG. 8 is a block conceptual diagram showing a configuration of a pipeline type A / D conversion circuit that self-corrects a conversion error in the conventional background. The pipeline type A / D conversion circuit 120 shown in FIG. 1 includes an A / D conversion circuit main body 122 and a conversion error correction circuit 124.

The A / D conversion circuit main body 122 includes a first-stage sub A / D converter 126 and a second-stage sub A / D converter 128 that collectively represents the second to last sub-A / D converters. They are shown separately. That is, in the pipeline type A / D conversion circuit 120, the conversion error correction is performed on the assumption that the error correction of the sub-A / D converter 128 in the subsequent stage is completed (including one that does not require error correction). the circuit 124, Ru Oh corrects the conversion error of the first-stage sub-a / D converter 126 in the background.

  Similarly, 10 sub A / D converters are connected in cascade, and a 1-bit sub digital code is output from each of the sub A / D converters. That is, the subsequent stage sub-A / D converter 128 outputs a subsequent-stage sub-digital code consisting of 9 bits.

  The first-stage sub A / D converter 126 has basically the same configuration as that shown in FIG. That is, the first-stage sub A / D converter 126 includes an A / D conversion unit 110, a D / A conversion unit 112, a subtractor 116, and an amplifier 118. In the first stage sub A / D converter 126, a subtractor 114 constituting a conversion error correction circuit 124 is arranged between the D / A conversion unit 112 and the subtractor 116.

  The conversion error correction circuit 124 includes the subtractor 114, the subtractor 130, the amplifier 132, the adder 136, the multiplier 140, and the long-time average circuit 142 described above.

  Here, a case is considered where a gain error indicated by 'g' exists in the amplifier 118 of the first stage sub A / D converter 126. In this case, the amplifier 118 doubles the output of the subtractor 116 and outputs the result by multiplying the output by (2 + g).

  Hereinafter, the operation of the pipeline type A / D conversion circuit 120 will be described.

  In the first stage sub A / D converter 126, the analog input signal y is A / D converted by the A / D conversion unit 110, and the first stage sub digital code D is output. D / A conversion is performed by the D / A conversion unit 112.

  In the conversion error correction circuit 124, the subtracter 114 in the first stage sub A / D converter 126 subtracts the known test signal ts from the output of the D / A conversion unit 112, and outputs the subtraction result D￣. . Here, the test signal ts is an analog signal when calculating with an analog signal, and is a digital signal when calculating with a digital signal. However, for convenience, the analog signal and the digital signal can be considered equivalent. Handle with the same symbol ts. Hereinafter, the signal ts in this specification is handled in the same manner. Further, it can be considered that the output of the D / A conversion unit 112 and the sub-digital code D are equivalent, and the output of the subtractor 114 can be expressed as D−ts = D￣.

  The subtracter 130 subtracts the same test signal ts from the sub digital code D of the first stage sub A / D converter 126, and outputs the subtraction result D￣. That is, D￣ = D−ts, and the outputs (subtraction results) of the two subtractors 114 and 130 are the same D￣. Subsequently, the output 132 of the subtractor 130 is amplified twice by the amplifier 132 and output. That is, the output of the amplifier 132 is 2D.

  In the first-stage sub A / D converter 126, the subtractor 116 subtracts the output D￣ of the subtractor 114 from the analog input signal y, and the amplifier 118 further outputs the output (y−D￣) of the subtractor 116. ) Is amplified (2 + g) times and output. That is, the output of the amplifier 118 is (2 + g) (y−D￣).

The sub-A / D converter 128 at the subsequent stage outputs a sub-digital code D _BE having 9 bits. Here, the sub-digital code D _BE in the subsequent stage is a digital signal, but as described above, since it can be considered equivalent to the analog surplus signal in the first stage, the output D of the sub-A / D converter 128 in the subsequent stage. _BE = (2 + g) (y−D￣).

Subsequently, the adder 136 adds the output 2D￣ of the amplifier 132 and the output D _BE of the sub A / D converter 128 in the subsequent stage, and outputs D _OUT . That is, the output D _OUT of the adder 136 = 2D￣ + D _BE = (2 + g) y−gD￣.

Subsequently, the multiplier 140 multiplies the output D _OUT of the adder 136 by the test signal ts. That is, the output D _OUT * ts of the multiplier 140 is (2 + g) y * ts−gD * ts + g * ts ² .

Finally, the long-time average circuit 142 calculates a long-time average of the output of the multiplier 140 (an average of the cumulative addition results of the output of the multiplier 140 for each sampling), and an estimated value of the gain error of the amplifier 118 ′ g _est ˜ ′ is calculated. That is, the estimated value g _est ˜ = E (D _OUT * ts) = E [(2 + g) y * ts−gD * ts + g * ts ² ] = g * E (ts ² ). Here, E is a symbol representing the long-time average.

As long as the analog input signal y and the test signal ts are uncorrelated, the terms E [(2 + g) y * ts] and E [gD * ts] in the calculation formulas of the estimated values g _est ˜ By increasing the length, it becomes asymptotic to '0', and the estimated value g _est ˜ = E [g * ts ² ] = g * E (ts ² ). In other words, the conversion error correction circuit 124 can obtain the estimated value “ _gest ”. Further, conversion error correction can be performed by a correction circuit (not shown) using the estimated gain error 'g'.

  As described above, the conventional conversion error correction circuit is based on the premise that the analog input signal and the test signal are uncorrelated, and there is a possibility that error estimation may not succeed depending on the analog input signal. In addition, in order for the error estimation to be accurate, averaging for a very long time is necessary, and depending on the required accuracy, it may take a long time for the estimated value to converge. That is, there is a trade-off between the accuracy of A / D conversion and the speed of error correction.

  For example, there is a technique as described in Non-Patent Document 1 as a method capable of self-correcting a conversion error in the background.

Hung-Chih Liu, Zwei-Mei Lee, Jieh-Tsorng Wu, `` A 15-b 40-MS / s CMOS Pipelined Analog-to-Digital Converter With Digital Background Calibration '', IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 5, MAY 2005, p.1047-1056

  It is an object of the present invention to provide a pipeline type A / C having a conversion error correction circuit that has very high convergence when calculating an error estimated value and can perform highly accurate conversion error estimation and correction in a relatively short time. It is to provide a D conversion circuit.

In order to achieve the above object, the present invention provides an A / D conversion unit for A / D converting an analog input signal and outputting a sub-digital code;
A D / A conversion unit for D / A converting the sub-digital code;
A first subtracter for subtracting a test signal from the output of the D / A conversion unit;
A second subtracter for adding the output of the first subtracter and the analog input signal;
A plurality of sub A / D converters comprising a first amplifier for amplifying the output of the second subtractor and outputting an analog surplus signal;
The plurality of sub A / D converters are connected in cascade, and each of the sub A / D converters converts the analog input signal into a digital code with a predetermined bit precision and the most significant bit side of the digital code. An A / D conversion circuit main body that performs A / D conversion sequentially from
A conversion error correction circuit that performs error correction of A / D conversion in the sub A / D converter to be corrected among the plurality of sub A / D converters;
The conversion error correction circuit adds the sub-digital code obtained by subtracting the test signal and the sub-digital code of the sub-A / D converter at the subsequent stage to which the analog surplus signal including the error component is input to obtain a digital code. An arithmetic circuit to be generated;
An A / D converter for error correction for A / D converting the analog input signal into a digital code;
A third subtracter for subtracting the output of the error correction A / D converter from the output of the arithmetic circuit;
A multiplier for multiplying the output of the subtracter by the test signal;
The smoothed output of the multiplier flat, and average circuit you calculate the estimated error value of the A / D conversion in the error corrected sub A / D converter, with the output of the previous Kitaira equalizing circuit And a correction circuit that corrects a sub-digital code obtained by subtracting the test signal included in the digital code output from the arithmetic circuit. A pipeline A / D conversion circuit is provided.

Here, it is preferable that the error correction A / D converter converts the analog input signal into a digital code having a bit accuracy lower than that of the pipeline type A / D conversion circuit.
Further, the correction circuit, within a period of Hitoshi Taira, it is preferable to carry out a plurality of times to correct the output of the error correction A / D converter.
The correction circuit adjusts the gain change of the second amplifier that amplifies the sub-digital code obtained by subtracting the test signal and the third amplifier that amplifies the output of the error correction A / D converter. It is preferable.
The test signal is preferably a square wave.
The correction circuit includes a second multiplier that multiplies the error component of the A / D conversion and a coefficient that adjusts a change in gain of the first and second amplifiers, and the second multiplier. A cumulative adder that cumulatively adds the outputs of
It is preferable to control the amplification factors of the second and third amplifiers by the output of the cumulative adder.

  According to the present invention, the convergence at the time of error estimation is greatly improved, and conversion error estimation and correction can be performed with high accuracy in a relatively short time. That is, the case where the error estimation does not converge can be almost eliminated, and the trade-off existing between the required accuracy of A / D conversion and the convergence speed of the conversion error estimation can be dramatically eliminated. Also, the convergence stability of error estimation is not affected by the specific waveform of the analog input signal, and the stability and reliability of error estimation in the background can be dramatically improved.

It is a block conceptual diagram showing the structure of the pipeline type A / D conversion circuit of this invention. It is a block conceptual diagram showing the structure of the specific example of the pipeline type A / D conversion circuit of this invention. It is a graph showing the state of an analog input signal. It is a graph showing the state of a test signal. It is a graph showing the state of the residual output code after conversion error correction is completed. It is another graph showing the state of a test signal. It is a block conceptual diagram showing the structure of a pipeline type A / D conversion circuit. It is a block conceptual diagram showing the structure of the specific example of the pipeline type A / D conversion circuit which self-corrects the conversion error in the conventional background. It is a block conceptual diagram showing the structure of the pipeline type A / D conversion circuit shown in FIG.

  Hereinafter, a pipeline A / D conversion circuit of the present invention will be described in detail based on a preferred embodiment shown in the accompanying drawings.

  FIG. 1 is a block conceptual diagram showing a configuration of a pipeline type A / D conversion circuit of the present invention. The pipeline type A / D conversion circuit 10 shown in FIG. 1 includes an A / D conversion circuit main body 12 and a conversion error correction circuit 14.

  The A / D conversion circuit main body 12 sequentially converts an analog input signal into a digital code with a predetermined bit precision (a predetermined number of bits) every one sampling time step by step from the most significant bit side of the digital code. / D conversion.

  The A / D conversion circuit main body 12 is configured by cascading a plurality of sub A / D converters, but in FIG. 1, the first stage sub A / D converter 16 to be error-corrected and the subsequent stage A / D conversion circuit 12 are connected. A sub A / D converter (second stage to final stage sub A / D converter) 18 is shown separately. FIG. 1 is an example in the case of correcting the conversion error of the first stage sub A / D converter 16 on the assumption that the error correction of the second stage A / D converter 18 has been completed.

  An analog input signal is input to the first-stage sub A / D converter 16. From the first-stage sub A / D converter 16, the first-stage sub-digital code and the first-stage analog surplus signal are output. The first-stage analog surplus signal is input to the subsequent-stage sub A / D converter 18. The sub-A / D converter 18 at the subsequent stage outputs the sub-digital code at each stage (second stage to final stage) as the sub-digital code at the subsequent stage.

Subsequently, the conversion error correction circuit 14 is a background type that performs error correction of A / D conversion in the first stage sub A / D converter 16 of the error correction target among the plurality of sub A / D converters. is there. The conversion error correction circuit 14 is a pipeline type A / D conversion obtained by A / D converting the same analog input signal from the digital code output from the A / D conversion circuit main body 12 every sampling time. After subtracting the error correction digital code with a bit accuracy lower than that of the circuit 10, the known test signal is multiplied (integrated), and an average value for a long period of time is obtained to calculate an estimated value “g _est ” of the gain error.

  The conversion error correction circuit 14 includes an error correction A / D converter 20, amplifiers (digital multipliers) 22 and 24, an adder 26, a subtractor 28, a multiplier 30, and a long-time averaging circuit 32. It is constituted by.

  Here, the amplifier 22 and the adder 26 are combined with a circuit (for example, see FIG. 2) that is built in the first stage sub-A / D converter 16 and that uses the test signal. Configure the circuit. The arithmetic circuit includes a digital code output from the A / D converter body 12, a test signal component, and an A / D conversion error component in the error correction target sub A / D converter. Is generated.

  A known test signal is input to the first-stage sub A / D converter 16 to be corrected. The first stage sub-digital code output from the first stage sub A / D converter 16 is input to the amplifier 22.

  The error correction A / D converter 20 receives the same analog input signal as that input to the first-stage sub A / D converter 16. The error correction A / D converter 20 converts an analog input signal into an error correction digital code (that is, one of 1 to 9 bit precision) with a bit accuracy lower than that of the pipeline type A / D conversion circuit 10. / D conversion, and consumes less power and area than the A / D conversion circuit main body 12. The error correction digital code output from the error correction A / D converter 20 is input to the amplifier 24.

The output of the amplifier 22 and the subsequent sub-digital code output from the subsequent sub-A / D converter 18 are input to the adder 26. The output (digital code) of the adder 26 is input to the + terminal of the subtracter 28, and the output of the amplifier 24 is input to the − terminal. The output of the subtractor 28 (residual digital code (residual error)) and the test signal are input to the multiplier 30, and the output of the multiplier 30 is input to the long-time average circuit 32, and the gain error is estimated from the long-time average circuit 32. The value 'g _est ~' is output.

  That is, the conversion error correction circuit 14 has a subtracter 28 inserted between the adder 26 and the multiplier 30 as compared with the conventional conversion error correction circuit 150 shown in FIG. From the output (digital code) of the adder 26, the error correction A / D converter 20 converts the analog input signal into a low-precision digital code, and the error correction digital code amplified by the amplifier 24 is doubled. After the subtraction by the subtracter 28, the output of the subtracter 28 is input to the multiplier 30.

  Next, a schematic operation of the pipeline type A / D conversion circuit 10 shown in FIG. 1 will be described.

  The analog input signal is A / D converted by the first stage sub A / D converter 16, and the first stage sub digital code is output from the first stage sub A / D converter 16, and the analog input signal and the first stage sub A / D converter 16 are output. A first-stage analog surplus signal is output based on the digital code and the test signal. The first-stage analog surplus signal is further A / D-converted step by step by the subsequent-stage sub A / D converter 18, and the subsequent-stage sub-digital code is output.

  The analog input signal is A / D converted by the error correction A / D converter 20, and a low-precision error correction digital code is output.

  The first stage sub-digital code is amplified twice by the amplifier 22, and the error correction digital code is also amplified twice by the amplifier 24. Here, the gains of the amplifiers 22 and 24 are set to ideal values of the gains of the amplifiers in the output stage of the first stage sub A / D converter 16.

The adder 26 adds the output of the amplifier 22 and the subsequent sub-digital code, and outputs a digital code having a predetermined number of bits. Subsequently, the subtracter 28 subtracts the output of the amplifier 24 from the output of the adder 26 and outputs a residual digital code. Subsequently, the multiplier 30 multiplies the output of the subtractor 28 and the test signal, the long-time averaging circuit 32 averages the output of the multiplier 30 for a long time, and the long-time averaging circuit 32 outputs the error correction target. The A / D conversion error estimated value “g _est ” in the first stage sub A / D converter 46 is output.

When the analog input signal and the test signal are uncorrelated, the conversion error correction circuit 14 obtains the term including the analog input signal from the calculation formula of the gain error estimated value 'g _est- ' by taking a long-time average. And a term including a sub-digital code can be removed. The error correction A / D converter 20, the amplifier 24, and the subtractor 28 subtract the value of the term including the analog input signal from the calculation formula of the gain error estimated value 'g _est ~' before taking a long-term average. To do.

Thereby, the value of the term including the analog input signal in the calculation formula of the estimated value “g _est ” of the gain error can be significantly reduced. For example, if the analog input signal is 'y', the gain error of the first stage sub-A / D converter 16 is 'g', and 2y is subtracted from the value (2 + g) y of the term including the analog input signal y, the analog The value of the term including the input signal is gy. As a result, it is possible to greatly improve the convergence when calculating the gain error estimated value “g _est ”, and to perform highly accurate conversion error correction in a relatively short time.

  Next, a specific example of the pipeline type A / D conversion circuit of the present invention will be described.

  FIG. 2 is a block conceptual diagram showing the configuration of a specific example of the pipeline type A / D conversion circuit of the present invention. A pipeline type A / D conversion circuit 40 shown in FIG. 1 includes an A / D conversion circuit main body 42 and a conversion error correction circuit 44.

  The A / D conversion circuit main body 42 is configured by cascading 10 sub A / D converters, and each sub A / D converter outputs a 1-bit sub digital code. The As in the case of FIG. 1, in the example shown in FIG. 2, the A / D conversion circuit main body 42 includes the first stage sub-A / D converter 46 to be error-corrected and the subsequent stage (second stage to final stage). A sub A / D converter (9-bit precision) 48 is shown separately.

  The first stage sub A / D converter 46 includes an A / D conversion unit 70, a D / A conversion unit 72, a subtractor 76, and an amplifier 78. In the example shown in FIG. 2, a subtracter 74 constituting the conversion error correction circuit 44 is disposed between the D / A conversion unit 72 and the subtractor 76.

  An analog input signal y is input to the A / D conversion unit 70. The A / D conversion unit 70 outputs the first stage sub-digital code D and also inputs it to the D / A conversion unit 72. The output of the D / A conversion unit 72 is input to the + terminal of the subtracter 74, and the known test signal ts is input to the − terminal. The analog input signal y is input to the + terminal of the subtractor 76, and the output of the subtracter 74 is input to the − terminal. The output of the subtractor 76 is input to the amplifier 78, and the first stage analog surplus signal is output from the amplifier 78.

  Each sub A / D converter is a 1.5-bit type, and an analog surplus signal obtained by accurately doubling the output voltage of the subtractor 76 by the amplifier 78 is input to the sub A / D converter in the subsequent stage. Ideally. On the other hand, in the example of FIG. 2, the gain of the amplifier 78 of the first-stage sub A / D converter 46 is assumed to be “1.9”. That is, as in the case of FIG. 8, if the gain of the amplifier 78 is represented by “2 + g”, the gain error “g” = “− 0.1”.

  That is, the amplifier 78 of the first-stage sub A / D converter 46 doubles the output of the subtractor 76 if it is originally (an ideal state with no conversion error), and outputs 1.9 times. Will be output.

  The conversion error correction circuit 44 includes a subtractor 74, a subtractor 80, an amplifier 52, an adder 56, an A / D converter for error correction (4-bit accuracy) 50, an amplifier 54, The subtractor 58, the multiplier 60, the long-time averaging circuit 62, the multiplier 64, and the cumulative addition circuit 66 are configured.

Here, the subtractors 74 and 80, the amplifier 52, and the adder 56 constitute an example of the arithmetic circuit of the present invention. The arithmetic circuit of the present embodiment subtracts a known test signal ts from the sub-digital code of the first stage sub-A / D converter 46 to be error-corrected and an analog signal obtained by D / A-converting the sub-digital code. The sub-digital code D￣ obtained by subtracting the signal, the component of the test signal ts subtracted from the D / A converted analog signal, and the error component of the A / D conversion in the first stage sub-A / D converter 46 to be corrected. A digital code D _OUT is generated by adding the sub digital code D _BE of the sub A / D converter 48 in the subsequent stage.

The multiplier 64 and the cumulative adder 66 together with the feedback adjustment function of the amplifiers 52 and 54 constitute a correction circuit of the present invention. The correction circuit uses the output of the long-time averaging circuit 62 and uses the output of the A / D conversion error included in the digital code D _OUT output from the arithmetic circuit (the adder 56 in the output stage in the example of FIG. 2). Is to correct.

  As described above, the subtracter 74 is disposed inside the first-stage sub A / D converter 46.

  The first stage sub-digital code output from the first stage sub-A / D converter 46 is input to the + terminal of the subtractor 80, and the test signal ts is input to the − terminal. The output of the subtracter 80 is input to the amplifier 52.

  The analog input signal y is input to the error correction A / D converter 50. The output of the error correction A / D converter 50 is input to the amplifier 54.

  The adder 56 receives the output of the amplifier 52 and the 9-bit downstream sub-digital code output from the downstream sub-A / D converter 48. The output of the adder 56 is input to the + terminal of the subtractor 58, and the output of the amplifier 54 is input to the − terminal. The multiplier 60 receives the output of the subtractor 58 and the test signal ts, and the output of the multiplier 60 is input to the long time averaging circuit 62. The multiplier 64 receives the output of the long-time averaging circuit 62 and the gain correction weighting coefficient, the output of the multiplier 64 is input to the cumulative adder 66, and the output of the cumulative adder 66 is input to the amplifiers 52 and 54. The

  Here, it is assumed that the analog input signal y is a signal having a predetermined intensity having a spectrum in a band of 0 to 9 MHz, which changes at each sampling time, as shown in the graph of FIG. The vertical axis of the graph in FIG. 3 represents the signal intensity of the analog input signal y, and the horizontal axis represents the frequency. Further, it is assumed that the sampling rate of the pipeline type A / D conversion circuit 40 shown in FIG. 2 is 20 MHz. That is, the Nyquist frequency is 10 MHz.

On the other hand, it is assumed that the test signal ts is a pseudo-random signal (PRBS signal) that is repeated at a sampling interval of 2 ^ 32 and changes at each sampling time. As shown in the graph of FIG. 4, the test signal ts is a substantially white signal (the signal intensity hardly depends on the frequency) having a frequency lower than the Nyquist frequency. The vertical axis of the graph in FIG. 4 represents the signal strength of the test signal ts, and the horizontal axis represents the frequency. The figure also shows the output (residual digital code) D _{RES of the} subtractor 58 multiplied by the test signal ts.

  Next, the operation of the pipeline type A / D conversion circuit shown in FIG. 2 will be described.

  In the following description, it is assumed that A / D conversion is performed by the A / D conversion circuit main body 42 every sampling time. In addition, when taking the long-time average, the long-time average is taken once for 2 ^ 12 = 4096 samples. That is, as described above, considering that the sampling rate is 20 MHz, a long-time average is taken once per 204.8 μS.

  In the first stage sub A / D converter 46, the analog input signal y is A / D converted by the A / D conversion unit 70, and the first stage sub digital code D is output. D / A conversion is performed by the / A conversion unit 72.

  In the conversion error correction circuit 44, a known test signal ts is subtracted from the output of the D / A conversion unit 72 by a subtracter 74 in the first stage sub A / D converter 46, and the subtraction result D 結果 = D−ts. Is output.

  The subtracter 80 subtracts the same test signal ts from the first stage sub-digital code D output from the first stage sub A / D converter 46, and outputs the subtraction result D 結果. That is, D￣ = D−ts, and the outputs of the two subtracters 74 and 80 are the same D￣. Subsequently, the output D 出力 of the subtractor 80 is amplified by a factor of 2 and output by the amplifier 52. That is, the output voltage of the amplifier 52 is 2D.

  Here, the gain ‘G’ of the amplifier 52 is set to an initial value of 2 which is the originally expected gain of the amplifier 78 of the sub A / D converter 46 in the first stage.

  Further, the analog input signal y is A / D converted into a digital code with 4-bit accuracy by the error correction A / D converter 50, and the output D of the error correction A / D converter 50 is Amplified twice and output. That is, the output of the amplifier 54 is 2D.

  Here, the gain ‘G’ of the amplifier 54 is also set to an initial value of 2 which is the originally expected gain of the amplifier 78 of the sub A / D converter 46 in the first stage.

  In the first stage sub A / D converter 46, the subtracter 76 subtracts the output D￣ of the subtractor 74 from the analog input signal y, and the amplifier 78 further outputs the output (y−D￣) of the subtractor 76. ) Is amplified by 1.9 times and output. That is, the output of the subtracter is 1.9 (y−D￣).

The sub-A / D converter 48 at the subsequent stage outputs a sub-digital code D _BE having 9 bits. Here, the subsequent stage of the sub digital code D _BE, as described above, since it can be considered to be equivalent to the first stage of the analog surplus signals, in a subsequent sub digital code _{D BE = 1.9 (y-D¯} ) I can express.

Subsequently, the adder 56 adds the output 2D￣ of the amplifier 52 and the output D _BE of the sub A / D converter 48 in the subsequent stage, and outputs a digital code D _OUT . That is, the output D _OUT of the adder 56 is 2D￣ + D _BE = 1.9y + 0.1D￣. Since the gain “g” of the amplifier 78 of the first stage A / D converter 46 = 1.9, the gain “G” = 2 of the amplifier 52 of the conversion error correction circuit 44, the difference between the two becomes 0.1. The component of the test signal ts is mixed in the digital code D _OUT with a proportional intensity.

Subsequently, the subtracter 58 subtracts the output 2D of the amplifier 54 from the output D _OUT of the adder 56, and outputs a residual digital code D _RES . Here, assuming that the output 2D of the amplifier 54 is substantially equivalent to the voltage 2y that is twice the analog input signal y, the output D _RES of the subtractor 58 = 1.9y + 0.1D￣−2D = −0.1y + 0. The component of the analog input signal y included in the output D _RES of the subtractor 58 is greatly reduced from “1.9” to “−0.1”.

In this way, by reducing the component of the analog input signal y from the output D _OUT of the adder 56, the convergence when calculating the error estimated value 'g _est ~' can be greatly increased. It is possible to perform highly accurate conversion error correction in a short time.

  In other words, depending on the analog input signal, the case where the error estimation does not converge can be almost eliminated, and the trade-off between the required accuracy of A / D conversion and the convergence speed of the conversion error estimation is also dramatically eliminated. be able to. Also, the convergence stability of error estimation is not affected by the specific waveform of the analog input signal, and the stability and reliability of error estimation in the background can be dramatically improved.

Subsequently, the multiplier 60 multiplies the output D _RES of the subtractor 58 and the test signal ts. That is, the output D _RES * ts = −0.1y * ts + 0.1D * ts−0.1 * ts ^{2 of} the subtractor 58 is obtained.

Subsequently, the long-time average circuit 62 calculates the long-time average of the output of the multiplier 60 (cumulative addition average of the number of samples N = 2 ^ 12 = 4096), and the gain error estimate value ' _gest ~ 'Is calculated. That is, the estimated value g _est ˜ = E (D _OUT * ts) = E (−0.1y * ts + 0.1D * ts−0.1 * ts ² ) ≈−0.1 * E (ts ² ). Similarly, E is a symbol that represents a long-term average.

When the long-time average of the integration of the residual digital code D _RES and the test signal ts is taken, only the difference between the gain “G” and the gain “g” of the sub A / D converter 46 is weighted only for the test signal ts and its correlation component. Is output. In this specific example, since most of the components of the analog input signal y are removed from the digital code D _OUT by the error correction A / D converter 50, the amplifier 54, and the subtractor 58, the analog input signal y and the test signal are removed. The correlation component of ts can be almost ignored.

If the correlation component of the analog input signal y and the test signal ts is negligible, of the calculation formula of the estimation value _{'g est ~', E (} -0.1y * ts), E (0.1D * ts) , respectively Asymptotically approaching “0” by taking a long-time average of the predetermined number of samples N, the estimated value g _est ˜ = E (−0.1 * ts ² ) = − 0.1 * E (ts ² ). Further, E (ts ² ) is asymptotic to a known value by taking a long-time average of the predetermined number of samples N, in this example, “1”, and the estimated value g _est ˜−−0.1 = “g” Become.

That is, when the correlation component between the analog input signal y and the test signal ts can be ignored, the conversion error correction circuit 44 can obtain the estimated value “g _est ”. Further, as described above, by removing most of the components of the analog input signal y from the output D _OUT of the adder 56, the convergence when calculating the error estimated value 'g _est ~' as compared with the conventional case. Therefore, the conversion error can be corrected with high accuracy in a relatively short time.

Subsequently, the multiplier 64 multiplies the output of the long time averaging circuit 62 by a gain correction weighting coefficient. Here, the value of the gain correction weighting coefficient is set to the magnitude of the coefficient by which the gain error “g” is corrected by half per one time average (number of samples N = 2 ^ 12 = 4096). By changing the value of the gain correction weighting coefficient, it is possible to change (adjust) the convergence time when calculating the error estimated value 'g _est ~'.

  If the value of the gain correction weighting factor is decreased, the change in the gain of the amplifiers 52 and 54 can be delayed. However, if the value is excessively decreased, the gain of the amplifiers 52 and 54 is changed from the initial value to the optimum value (1 in this example). .9) The convergence time until convergence is increased. On the other hand, when the value of the coefficient is increased, the gains of the amplifiers 52 and 54 change rapidly. However, if this value is increased too much, the gains of the amplifiers 52 and 54 pass the optimum value from the initial value, and the convergence time is rather long. There is a case. Since the value of the coefficient depends on the test signal ts, it is desirable to appropriately determine the coefficient according to the test signal ts.

  Subsequently, the output of the multiplier 64 is sequentially cumulatively added by the cumulative adder 66. The output of the cumulative adder 66 is fed back to the two amplifiers 52 and 54, and the gain 'G' of these amplifiers 52 and 54 is changed (adjusted). Thereafter, the above operation is repeated until the gain “G” of the amplifiers 52 and 54 is corrected to the optimum value. When G is corrected to the optimum value, the output of the cumulative adder 66 is fixed and the conversion error correction is completed.

  As described above, since the value of the gain correction weighting coefficient is the magnitude of the coefficient by which the gain error “g” is corrected by half per one time average (number of samples N = 2 ^ 12 = 4096), The gain “G” after averaging once is corrected from 2 to 1.95. Similarly, after gain ‘G’ = 1.95, if the average is taken again for a long time, gain ‘G’ is updated from 1.95 to 1.925. The gain 'G' asymptotically approaches 1.9 as this is repeated many times.

Since the state of the residual output code D _RES after the gain “G” has converged to about 1.9 is equal to the quantization noise of the error correction A / D converter 50, as shown in the graph of FIG. It is white and the signal strength is much smaller than the analog input signal. That is, the term in which the gain “G” is corrected at random is dramatically reduced by providing the error correction A / D converter 50. Similarly, the vertical axis of the graph of FIG. 5 represents the signal strength of the residual output code D _RES , and the horizontal axis represents its frequency.

  In the present invention, the waveform of the analog input signal (frequency band and signal strength), the waveform of the test signal (random, square wave, etc.), the average number of samples for a long time (within an arbitrary range where stable error estimation can be expected) are It is not limited at all. Also, the number of bits of the A / D conversion circuit body (bit accuracy of the digital code) and sampling frequency, the position and number of bits of the sub-A / D converter subject to error correction, and the number of bits of the A / D converter for error correction It is not limited at all.

According to the present invention, as described above, the correlation component between the analog input signal and the test signal in the error estimation value calculation formula can be ignored. Therefore, a square wave as shown in the graph of FIG. 6 can be used as a test signal instead of a random signal. The graph of FIG. 6 shows a 500 KHz square wave and a part of its harmonics as test signals. The vertical axis of the graph in FIG. 6 represents the signal strength of the test signal, and the horizontal axis represents the frequency. In the same figure, the residual digital code D _RES is also shown.

  Further, the method using the conversion error correction circuit 44 is not limited to the gain error “g” of the amplifier 78 at the output stage of the sub A / D converter 46, and is based on the error model and the degree of error in other various components. Is also applicable. In addition, the calculation circuit (calculation method) of the error estimation value in the conversion error correction circuit is not limited at all (calculation formula, values of various coefficients appearing in the error correction calculation, use of LUT (lookup table), etc.).

The present invention is basically as described above.
Although the present invention has been described in detail above, the present invention is not limited to the above-described embodiment, and it is needless to say that various improvements and modifications may be made without departing from the gist of the present invention.

10, 40, 100, 120, 150 Pipeline type A / D conversion circuit 12, 42, 102, 122 A / D conversion circuit main body 14, 44, 124 Conversion error correction circuit 16, 18, 46, 48, 106, 126 , 128 Sub A / D converter 20, 50 A / D converter for error correction 22, 24, 52, 54, 78, 118, 132 Amplifier 26, 56, 136 Adder 28, 58, 74, 76, 80, 114, 116, 130 Subtractor 30, 60, 64, 140 Multiplier 32, 62, 142 Long-time averaging circuit 66 Cumulative addition circuit 70, 110 A / D conversion unit 72, 112 D / A conversion unit 104 Decoder

Claims (5)

An A / D conversion unit for A / D converting an analog input signal and outputting a sub-digital code;
A D / A conversion unit for D / A converting the sub-digital code;
A first subtracter for subtracting a test signal from the output of the D / A conversion unit;
A second subtracter for adding the output of the first subtracter and the analog input signal;
A plurality of sub A / D converters comprising a first amplifier for amplifying the output of the second subtractor and outputting an analog surplus signal;
The plurality of sub A / D converters are connected in cascade, and each of the sub A / D converters converts the analog input signal into a digital code with a predetermined bit precision and the most significant bit side of the digital code. An A / D conversion circuit main body that performs A / D conversion sequentially from
A conversion error correction circuit that performs error correction of A / D conversion in the sub A / D converter to be corrected among the plurality of sub A / D converters;
The conversion error correction circuit adds the sub-digital code obtained by subtracting the test signal and the sub-digital code of the sub-A / D converter at the subsequent stage to which the analog surplus signal including the error component is input to obtain a digital code. An arithmetic circuit to be generated;
An A / D converter for error correction for A / D converting the analog input signal into a digital code;
A third subtracter for subtracting the output of the error correction A / D converter from the output of the arithmetic circuit;
A multiplier for multiplying the output of the subtracter by the test signal;
The smoothed output of the multiplier flat, and average circuit you calculate the estimated error value of the A / D conversion in the error corrected sub A / D converter, with the output of the previous Kitaira equalizing circuit And a correction circuit for correcting a sub-digital code obtained by subtracting the test signal included in the digital code output from the arithmetic circuit. The correction circuit, within a period of Hitoshi Taira, the pipelined A / D converter circuit according to claim 1, characterized in that a plurality of times to correct the output of the error correction A / D converter.   The correction circuit adjusts a change in gain of a second amplifier that amplifies the sub-digital code obtained by subtracting the test signal and a third amplifier that amplifies the output of the error correction A / D converter. The pipeline type A / D conversion circuit according to claim 1 or 2,   4. The pipeline type A / D conversion circuit according to claim 1, wherein the test signal is a square wave.   The correction circuit includes a second multiplier that multiplies the error component of the A / D conversion by a coefficient that adjusts a change in gain of the first and second amplifiers, and an output of the second multiplier. A cumulative adder for cumulatively adding
  5. The pipeline type A / D conversion circuit according to claim 1, wherein amplification factors of the second and third amplifiers are controlled by an output of the cumulative adder.

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