JP4401006B2 - Nonvolatile semiconductor memory device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory device having a floating gate and a manufacturing method thereof.
[0002]
[Prior art]
14A and 14B illustrate a typical structure of a nonvolatile semiconductor memory device including a floating gate. FIG. 14A is a plan view of the apparatus as viewed from above, and schematically shows the structure under the mask insulating film covering the entire upper surface. FIG. 14B shows a cross section cut along the line XX in FIG. Referring to FIG. 14, the conventional nonvolatile semiconductor memory device includes a semiconductor substrate 100 (hereinafter referred to as a substrate) on which a first impurity diffusion layer (source) 102 and a second impurity diffusion layer (drain) 104 are formed. )) Between the first and second impurity diffusion layers 102 and 104 and on the surface of the substrate 100, the first gate insulating film 106, the first gate electrode 108 that is a floating gate, and the second gate insulating film 110, a gate stacked structure 116 in which a second gate electrode 112 that is a control gate, and a gate hard mask insulating film 114 are stacked in this order, and a substrate exposed from the surface of the gate stacked structure 116 and the gate stacked structure 116 And a mask insulating film 118 covering the surface of 100.
[0003]
Further, the nonvolatile semiconductor memory device having such a structure is manufactured through the following processes, for example. FIG. 15A to FIG. 16B are schematic manufacturing process diagrams of this apparatus, and are shown by cross sections of the apparatus at the end of each process. FIG. 15 shows a structure in the middle of manufacturing the structure of the cut surface of the cross section cut along the YY line of FIG. FIG. 16 is a view corresponding to the cut surface of the cross section taken along the line XX in FIG.
[0004]
First, the element isolation film 124 is formed on the semiconductor substrate 100 by the LOCOS method, and the region of the substrate 100 is divided into an active region (element formation region) 126a and an element isolation region 126b. For this reason, after the pad oxide film 120 and the element isolation film forming nitride film are formed on the semiconductor substrate 100, the element isolation film forming nitride film is patterned. Thereafter, an element isolation film 124 is formed by thermal oxidation using the patterned nitride film 122 as a mask. As a result, the region covered with the nitride film 122 becomes the active region 126a, and the element isolation film 124 is formed in the portion exposed from the nitride film 122 to become the element isolation region 126b (FIG. 15A).
[0005]
Next, after removing the pad oxide film 120, a first insulating film 128 is formed on the exposed surface of the substrate 100 by thermal oxidation. Thereafter, a first electrode film made of polysilicon is formed on the first insulating film 128 and the adjacent element isolation film 124 by using the CVD method. Thereafter, the first electrode film 130 is divided on the element isolation film 124 by patterning the first electrode film by the photolithography technique and the subsequent anisotropic dry etching technique (FIG. 15B). ).
[0006]
Next, the second insulating film 132 is formed on the divided first electrode film 130 and the element isolation film 124 exposed from the film, and then the second electrode film 134 is formed on the second insulating film 132. To do. Further, a third insulating film 136 made of an oxide film or a nitride film is formed over the second electrode film 134 (FIGS. 15C and 16A). Note that FIGS. 15C and 16A. Is shown with cross-section cuts taken along different lines of the structure of the structure at the same point in time).
[0007]
Next, the first insulating film 128, the first electrode film 130, the second insulating film 132, the second electrode film 134, and the third insulating film 136 are formed by photolithography and subsequent anisotropic dry etching. Perform patterning. Accordingly, the first gate insulating film 106 that is the remaining portion of the first insulating film 128, the first gate electrode 108 that is the remaining portion of the first electrode film 130, and the second gate insulating that is the remaining portion of the second insulating film 132. A gate stacked structure 116 is formed which includes the film 110, the second gate electrode 112 which is the remaining portion of the second electrode film 134, and the gate hard mask insulating film 114 which is the remaining portion of the third insulating film 136 (FIG. 16). (B)).
[0008]
After that, a thin mask insulating film 118 is formed on the exposed substrate 100 so as to cover the gate stacked structure 116 (FIG. 14B).
[0009]
Next, ion implantation for forming the source diffusion layer 102 and the drain diffusion layer 104 on both sides of the gate stacked structure 116 is performed from above the mask insulating film 118. Here, arsenic ions (As⁺) At a voltage of 50 to 80 keV. After that, heat treatment is performed at 900 ° C. for 20 minutes to activate the implanted dopant (ions) and to form an overlap layer between the drain 104 and the first gate electrode 108 (FIG. 14B).
[0010]
Thereafter, a wiring layer is formed on the gate stacked structure described above using a normal wiring forming technique (not shown).
[0011]
Through such steps, the nonvolatile semiconductor memory device shown in FIG. 14 is formed.
[0012]
[Problems to be solved by the invention]
However, in the nonvolatile semiconductor memory device having the floating gate as described above, it is necessary to further reduce the thickness of the second gate insulating film 110 as the device becomes finer, but this reduction in thickness is approaching the limit. . This improves the coupling ratio, which is the ratio of the capacitance between the first gate electrode 108 and the second gate electrode 112 to the capacitance between the drain diffusion layer 104 and the first gate electrode 108. I can't hope. Therefore, the write characteristics cannot be improved.
[0013]
In the case of the PMOS structure, the channel dopant for the buried channel is excessively diffused by the heat treatment during the manufacturing process, so that there is a problem that an appropriate junction cannot be formed. In addition, there is a possibility that ions for forming the source diffusion layer 102 and the drain diffusion layer 104 are excessively diffused by the heat treatment and a short channel effect is generated. In order to avoid such a problem, if the heat treatment temperature is lowered, a sufficient overlap layer cannot be formed between the diffusion layer 104 and the first gate electrode 108, and there is a possibility that the write characteristics are deteriorated. is there.
[0014]
In addition, gate oxide film breakdown easily occurs due to electric field concentration caused by a potential difference between the end portion of the first gate electrode 108 and the drain diffusion layer 104.
[0015]
Therefore, the coupling ratio can be improved, a sufficient overlap layer between the diffusion layer and the first gate electrode can be obtained, and a non-volatile semiconductor memory device and a method for manufacturing the same that does not cause gate oxide film breakdown have appeared. It was desired.
[0016]
[Means for Solving the Problems]
  For this reason, according to the nonvolatile semiconductor memory device of the present invention,pluralA memory cell is provided,eachThe memory cell is exposed to the upper surface of the semiconductor substrate in the region of the first conductivity type of the semiconductor substrate, and is formed to be spaced apart from each other. A first gate insulating film, a first gate electrode, a second gate insulating film, and a semiconductor substrate and straddling the first diffusion layer and the second diffusion layer;As a control gateA gate laminated structure in which the second gate electrode is laminated in this order, and a sidewall electrode formed on the side wall of the gate laminated structure and electrically connected to the first gate electrode are provided.. A floating gate is formed by the first gate electrode and the sidewall electrode, and two memory cells adjacent to each other along the gate length direction share the first diffusion layer among the memory cells. The sidewall electrode is provided on one side wall on the second diffusion layer side in the gate length direction of the gate stacked structure, and is not provided on the one side wall on the first diffusion layer side.It is characterized by that.
[0017]
Since the sidewall electrode is electrically connected to the first gate electrode, the electrode constituted by the first gate electrode and the sidewall electrode substantially functions as a floating gate (floating gate). This increases the area of the insulating film between the second gate electrode serving as the control gate and the floating gate, so that the capacitance between the control gate and the floating gate can be increased. Therefore, since the coupling ratio is improved, the writing characteristics of this device can be improved. Further, due to the sidewall electrode, the end portion of the floating gate is in a position that bites into the diffusion layer region formed in the semiconductor substrate as compared with the conventional case. Therefore, a sufficient overlap layer between the diffusion layer and the floating gate can be obtained. Thereby, it is possible to alleviate the electric field concentration generated at the end of the floating gate as compared with the prior art, and to reduce the possibility of gate oxide film destruction.
[0019]
MaSide wall electrodes are provided on one side wall.For,A certain coupling ratio can be secured,further,The occurrence rate of a short circuit with the side wall electrode of the memory cell adjacent in the gate length direction on the side where the side wall electrode is not provided can be reduced.
[0020]
In the above nonvolatile semiconductor memory device, it is preferable that an insulating film is interposed between the sidewall electrode, the second gate insulating film, and the second gate electrode.
[0021]
Thereby, the sidewall electrode can be electrically connected only to the first gate electrode.
[0022]
In manufacturing the nonvolatile semiconductor memory device described above, the memory cell is preferably formed by including the following steps (1) to (8).
[0023]
(1) A step of separating an active region and an element isolation region by forming an element isolation region on a first conductivity type semiconductor substrate.
[0024]
(2) After sequentially forming the first insulating film and the first electrode film over the entire upper surface of the semiconductor substrate, the first electrode film provided on the active region adjacent to the element isolation region is formed on the element isolation region. Electrical cutting process.
[0025]
(3) A step of sequentially forming a second insulating film, a second electrode film, and a third insulating film over the entire upper surface of the semiconductor substrate so as to cover the first electrode film.
[0026]
  (4) By patterning the second insulating film, the second electrode film, and the third insulating film using a mask,Including a second gate electrode as a control gate formed as a remaining portion of the second electrode filmForming a preliminary gate stacked structure;
[0027]
(5) After forming an insulating film over the upper surface of the first electrode film exposed from the preliminary gate stacked structure, the side walls and the upper surface of the preliminary gate stacked structure, the insulating film is formed on the active regions on both sides of the preliminary gate stacked structure from above On the other hand, a step of implanting ions for forming the first and second diffusion layers.
[0028]
(6) A step of leaving an insulating film only on the side wall of the preliminary gate stacked structure and then forming a third electrode film on the surface of the remaining insulating film so as to be electrically connected to the first electrode film.
[0029]
  (7) removing the region of the first electrode film exposed from the third electrode filmAs a result, the first gate electrode is formed as the remaining portion of the first electrode film.Process.
[0030]
  (8)Formed on adjacent active regions across the isolation regionElectrically cut the third electrode film on the device isolation filmAs a result, a floating gate composed of the sidewall electrode formed as the remaining portion of the third electrode film and the first gate electrode is formed.Process.
[0031]
Thus, the first gate insulating film composed of the remaining portion of the first insulating film and the first gate composed of the remaining portion of the first electrode film on the semiconductor substrate provided with the first diffusion layer and the second diffusion layer. The electrode, the second gate insulating film composed of the remaining portion of the second insulating film, the second gate electrode composed of the remaining portion of the second electrode film, and the gate hard mask insulating film composed of the remaining portion of the third insulating film are laminated in this order. Thus, it is possible to form a memory cell including the gate stacked structure formed in this manner and a sidewall electrode formed on the side wall of the gate stacked structure and made of the remaining portion of the third electrode film. An insulating film is interposed between the second gate electrode and the sidewall electrode. Therefore, the sidewall electrode can be electrically connected only to the first gate electrode.
[0032]
According to this manufacturing method, it is possible to obtain an overlap layer of the diffusion layer and the first gate electrode and the sidewall electrode that become the floating gate without performing a high-temperature heat treatment step. For this reason, the short channel effect which may arise by a high-temperature heat treatment process can be suppressed. Further, it is possible to avoid the possibility that the write characteristics are deteriorated.
[0033]
  In the method for manufacturing a nonvolatile semiconductor memory device, the third electrode film formed on both sides of the preliminary gate stacked structure between the steps (7) and (8),On the active region side where ions for forming the first diffusion layer are implanted.Including a step of removing the third electrode filmThe
[0034]
Thus, a device in which the sidewall electrode film is provided on one side of the gate stacked structure can be formed. Therefore, in the case of a fine device, it is possible to avoid the possibility that a short circuit will occur between this memory cell and the side wall electrode film of the memory cell adjacent in the gate length direction on the side where the side wall electrode is not provided. it can.
[0035]
In addition, a nonvolatile semiconductor memory device having a memory cell in which a sidewall electrode is provided on one side of a gate stacked structure can also be obtained by a manufacturing method including the following steps (1) to (10).
[0036]
(1) A step of separating an active region and an element isolation region by forming an element isolation region on a first conductivity type semiconductor substrate.
[0037]
(2) After sequentially forming the first insulating film and the first electrode film over the entire upper surface of the semiconductor substrate, the first electrode film provided on the adjacent active region with the element isolation region interposed therebetween is placed on the element isolation region. The process of cutting electrically.
[0038]
(3) A step of sequentially forming a second insulating film, a second electrode film, and a third insulating film over the entire top surface of the semiconductor substrate so as to cover the first electrode film.
[0039]
(4) By patterning the second insulating film, the second electrode film, and the third insulating film using a mask, a laminated structure having a size that is twice the pitch in the gate length direction of the desired gate laminated structure. Forming step.
[0040]
  (5) After forming an insulating film over the upper surface of the first electrode film exposed from the laminated structure, the sidewalls and the upper surface of the laminated structure, the active film on both sides of the laminated structure from the upper side of the insulating filmThe second(2) Implanting ions for forming a diffusion layer.
[0041]
(6) A step of forming the third electrode film on the surface of the remaining insulating film so as to be electrically connected to the first electrode film after the insulating film is left only on the side wall of the laminated structure.
[0042]
(7) A step of removing the region of the first electrode film exposed from the third electrode film.
[0043]
  (8) A slit for dividing the third insulating film, the second electrode film, the second insulating film, and the first electrode film is formed in the stacked structure.At the same time, the first gate electrode is formed as the remaining portion of the first electrode film, and the second gate electrode as the control gate is formed as the remaining portion of the second electrode film.Process.
[0044]
  (9) From above the first insulating film exposed in the slit,1'sA step of implanting ions for forming a diffusion layer.
[0045]
  (10) The third electrode film formed on the active region adjacent to the element isolation regionThe elementElectrically cut on the child separation membraneAs a result, a floating gate composed of the side wall electrode and the first gate electrode provided on one side wall on the side where ions for forming the second diffusion layer are implanted is formed as the remaining portion of the third electrode film.Process.
[0046]
Accordingly, the remaining portion of the first insulating film becomes the first gate insulating film, the remaining portion of the first electrode film becomes the first gate electrode, the remaining portion of the second insulating film becomes the second gate insulating film, and the second The remaining portion of the electrode film becomes the second gate electrode, and the remaining portion of the third insulating film becomes the gate hard mask insulating film. A gate stack structure is formed of these films. Further, a side wall electrode is formed by the remaining portion of the third electrode film on one side wall in the gate length direction of the gate laminated structure. In the gate stacked structure, only the first gate electrode is electrically connected to the sidewall electrode. As a result, a floating gate composed of the first gate electrode and the sidewall electrode and having a sufficient overlap layer with the diffusion layer is obtained.
[0047]
In addition, since the side wall electrode is provided on one side of the gate stacked structure, when the device is fine, the memory cell and the memory cell adjacent in the gate length direction on the side where the side wall electrode is not provided are provided. It is possible to avoid the possibility of a short circuit occurring between the two.
[0048]
DETAILED DESCRIPTION OF THE INVENTION
  Embodiments of the present invention will be described below with reference to the drawings.And reference examplesI will explain. Each drawing merely schematically shows the shape, size, and arrangement relationship of each component so that the invention can be understood. Therefore, the present invention is not limited to the illustrated examples.
[0049]
  <Reference example>
  Referring to FIG. 1, the nonvolatile semiconductor memory device of the present inventionReference exampleI will explain. FIG. 1 is a diagram for explaining a main part of the nonvolatile semiconductor memory device (hereinafter referred to as a device), and this main part is shown by a cross section. The device includes a plurality of memory cells formed on a semiconductor substrate 10, and the memory cells are of a second conductivity type formed in the first conductivity type region of the semiconductor substrate 10 so as to be separated from each other. A first diffusion layer 12 and a second diffusion layer 14 are provided. The surfaces of the first and second diffusion layers 12 and 14 are exposed on the upper surface of the substrate 10.
[0050]
In this example, a p-type Si substrate 10 is provided with a source that is an n-type first diffusion layer 12 and a drain that is a second diffusion layer 14.
[0051]
The first gate insulating film 16, the first gate electrode 18, the second gate insulating film 20, and the second gate are formed on the semiconductor substrate 10 and across the first diffusion layer 12 and the second diffusion layer 14. The electrode 22 includes a gate stacked structure 24 formed by stacking in this order.
[0052]
In this example, the first SiO 2 that is the first gate insulating film 16 extends over the exposed surface of the source 12 and the exposed surface of the drain 14.₂A film is formed and this first SiO₂A first polysilicon electrode which is the first gate electrode 18 and a second SiO which is the second gate insulating film 20 are formed on the film 16.₂A film and a second polysilicon electrode which is the second gate electrode 22 are sequentially formed, whereby the gate stacked structure 24 is provided. In the configuration example described here, a gate hard mask insulating film 26 made of a silicon oxide film or a silicon nitride film is further provided above the second polysilicon electrode 22, and the gate including the insulating film 26 is included in the gate. A laminated structure 24 may be used.
[0053]
A sidewall electrode 28 is provided on the side wall of the gate stacked structure 24 so as to be electrically connected to the first gate electrode 18.
[0054]
In this example, an insulating film 30 made of a silicon oxide film is formed on both sides in the gate length direction of the gate laminated structure 24 excluding the first gate insulating film 16 and the first polysilicon electrode 18, and the surface of the insulating film 30 A third polysilicon electrode is formed as a sidewall electrode 28. The first polysilicon electrode 18 is formed so as to protrude longer than the length in the gate length direction of each constituent film of the gate laminated structure 24 excluding the electrode 18 and the first gate insulating film 16. The third polysilicon electrode 28 is provided on the protruding region 18 a of the first polysilicon electrode 18. Thereby, the first polysilicon electrode 18 and the third polysilicon electrode 28 are electrically connected. Therefore, the first polysilicon electrode 18 and the third polysilicon electrode 28 constitute a floating gate (floating gate).
[0055]
A mask insulating film 32 is provided on the entire top surface of the structure (FIG. 1).
[0056]
Such a nonvolatile semiconductor memory device is manufactured as follows.
[0057]
  2 (A) to 8 (C) show thisReference exampleFIG. 6 is a process diagram sequentially illustrating the manufacturing process of the nonvolatile semiconductor memory device, and is a sectional view of the device being manufactured or a plan view viewed from above.
[0058]
First, an element isolation region is formed in a first conductivity type semiconductor substrate, and an active region and an element isolation region are separated.
[0059]
  thisReference exampleThen, as in the conventional case, the element isolation film is formed by the LOCOS method. First, a pad oxide film 40 is formed on the p-type Si substrate 10 by thermal oxidation, and then a nitride film 42 for forming an element isolation film is formed on the pad oxide film 40 using a CVD method (FIG. 2 ( A)). Thereafter, the nitride film 42 is patterned. By this patterning, the nitride film 42x is left on the region to be the active region 43a, and the nitride film on the region to be the element isolation region 43b is removed (FIG. 2B). Next, an element isolation film 44 is formed in the region from which the nitride film has been removed by thermal oxidation (FIG. 2C). Thereafter, the remaining portion 42x of the nitride film is removed by wet etching using hot phosphoric acid, and the pad oxide film 40 is removed by wet etching using hydrofluoric acid.
[0060]
Next, after the first insulating film 46 and the first electrode film 48 are sequentially formed over the entire upper surface of the semiconductor substrate 10, the first electrode provided over the adjacent active regions 43a with the element isolation region 43b interposed therebetween. The film 48 is cut on the element isolation film 44.
[0061]
  Because of thisReference exampleThen, the first SiO as the first insulating film 46₂The film is formed by thermal oxidation. Thereafter, a first polysilicon film as the first electrode film 48 is formed by a CVD method (FIG. 2D). Thereafter, photolithography and subsequent anisotropic dry etching are performed on the first polysilicon film 48 to pattern the first polysilicon film 48. By this patterning, the first polysilicon film 48 provided over the adjacent active region 43a with the element isolation region 43b interposed therebetween is cut on the element isolation film 44 (FIG. 3A).
[0062]
Next, the second insulating film 50, the second electrode film 52, and the third insulating film 54 are sequentially formed over the entire upper surface of the semiconductor substrate 10 so as to cover the cut first electrode film 48x.
[0063]
  Because of thisReference exampleThen, the second SiO as the second insulating film 50₂The film is formed by thermal oxidation. Then this second SiO₂A second polysilicon film as the second electrode film 52 is formed on the film 50 using a CVD method. Further, a SiO method is used on the second polysilicon film 52 by the CVD method.₂Film or Si_ThreeN_FourA third insulating film 54 made of a film is formed (FIGS. 3B, 4 and 5A). Here, FIG. 3B shows a cut surface of a cross section cut along the line II in the plan view of the structure shown in FIG. 4 as viewed from above. FIG. 5A shows a cut surface of a cross section taken along the line II-II in FIG. FIG. 4 is a plan view of the structure as viewed from above, and shows the configuration on the lower side of the second insulating film 50.
[0064]
  Then thisReference exampleIn the manufacturing method, the preliminary gate stacked structure 56 is formed by patterning the second insulating film 50, the second electrode film 52, and the third insulating film 54 using a mask.
[0065]
  Because of thisReference exampleThen, the second SiO 2 is formed by photolithography and subsequent anisotropic dry etching.₂The film 50, the second polysilicon film 52, and the third insulating film 54 are patterned. As a result, a preliminary gate stacked structure 56 composed of the remaining portions 50x, 52x and 54x of the film is formed (FIG. 5B).
[0066]
Next, after an insulating film 58 is formed over the upper surface of the first electrode film 48 x exposed from the preliminary gate stacked structure 56, the side wall and the upper surface of the preliminary gate stacked structure 56, Ions for forming the first and second diffusion layers are implanted into the active regions on both sides of the structure 56.
[0067]
  Because of thisReference exampleThen, the insulating film 58 is formed on the upper surface of the exposed first polysilicon film 48x, the side wall and the upper surface of the preliminary gate stacked structure 56 by thermal oxidation as an insulating film 58.₂A film is formed. After that, using the preliminary gate stacked structure 56 as a mask, the active regions on both sides of the mask are SiO 2₂Arsenic ions (As +) are implanted from the upper side of the film 58 at an acceleration voltage of 50 to 80 keV. Thereafter, heat treatment for activating arsenic ions as dopants is performed at a temperature of 900 ° C. by RTA (Rapid Thermal Anneal). Thereby, the source 12 as the first diffusion layer and the drain 14 as the second diffusion layer are formed (FIG. 5C).
[0068]
Next, after the insulating film 30 is left only on the side wall of the preliminary gate stacked structure 56, the third electrode film 60 is electrically connected to the surface of the remaining insulating film 30 so as to be electrically connected to the first electrode film 48x. (28) is formed.
[0069]
  Because of thisReference exampleThen, the surface SiO₂By performing anisotropic dry etching on the film 58, SiO provided on the upper surface of the preliminary gate stacked structure 56 and the upper surface of the first polysilicon film 48 x exposed from the preliminary gate stacked structure 56.₂The portion of the film 58 is removed, and the SiO provided on the side wall of the preliminary gate laminated structure 56 is removed.₂Only the film 58 (30) remains. Thereafter, after depositing a third polysilicon film 60 as a third electrode film on the entire upper surface of the substrate 10 by the CVD method (FIG. 6A), anisotropic dry etching is performed to perform preliminary gate lamination. SiO on sidewall of structure 56₂The third polysilicon film 60 (28) is left on the surface of the film 30 in a sidewall shape. The bottom surface of the third polysilicon film 60x (28) left in the sidewall shape is in contact with the first polysilicon film 48x (FIG. 6B).
[0070]
  Then thisReference exampleAccording to this manufacturing method, the region of the first electrode film 48x exposed from the third polysilicon film 28 is removed.
[0071]
  Because of thisReference exampleThen, anisotropic dry etching is further performed following the etching of the third polysilicon film 60. Thereby, the region of the first polysilicon film 48x exposed from the portion of the sidewall-like third polysilicon film 28 can be removed. Accordingly, the remaining portion 18 of the first polysilicon film is formed (FIGS. 6C and 7A), where FIG. 6C is cut along the line II-II in FIG. It is a figure showing the cut end of the cross section.) 7A and 7B are plan views of the structure as seen from above, as in FIG. 7A shows a configuration before the resist pattern 64 is provided, and FIG. 7B shows a configuration after the resist pattern 64 is removed.
[0072]
Next, the third electrode film 60 (28) formed on the active region 43a adjacent to the element isolation region 43b is electrically cut on the element isolation film 44.
[0073]
  Because of thisReference exampleThen, on the remaining third electrode film 60 (28), a resist pattern 64 is provided in which a window 62 is formed so that the third electrode film 60 (28) is divided on the element isolation region 43b (FIG. 8 ( A)) Isotropic dry etching or wet etching is performed using the resist pattern 64 as a mask (FIG. 8B). 8A to 8C are views corresponding to the cut surface of the cross section taken along the line III-III in FIG. 7A and FIG. 7B. By the etching, the portion of the third electrode film 60 (28) exposed from the window 62 of the mask 64 is removed by etching. Therefore, thereafter, by removing the resist pattern 64, the sidewall electrode 28 composed of the remaining portion 60x of the third electrode film can be provided for each active region 43a (FIG. 7B and FIG. 8C). ))).
[0074]
As a result, the first SiO 2 is formed on the substrate 10 on which the source 12 and the drain 14 are formed.₂The first gate insulating film 16 made of the film 46, the first polysilicon electrode 18 as the first gate electrode made of the remaining portion 48x of the first polysilicon film, the second SiO₂The second gate insulating film 20 made of the remaining portion 50x of the film, the second polysilicon electrode 22 as the second gate electrode made of the remaining portion 52x of the second polysilicon film, and the third SiO₂Film (Si_ThreeN_FourA gate laminated structure 24 in which a gate hard mask insulating film 26 composed of the remaining portion 54x of the film) is laminated in this order, and a third electrically connected to the first polysilicon electrode 18 on both side walls of the gate laminated structure 24. A structure including a third polysilicon electrode 28 as a sidewall electrode made of the remaining portion 60x of the polysilicon film is obtained (FIGS. 1, 6C, 7B, and 8C). ).
[0075]
Thereafter, an insulating film 32 is formed on the entire upper surface of the substrate 10 by thermal oxidation.
[0076]
  In this wayReference exampleMemory cells of the nonvolatile semiconductor memory device are formed (FIG. 1).
[0077]
If a nonvolatile semiconductor memory device is manufactured using this method, the heat treatment conventionally performed for activating the dopant and forming the overlap layer between the gate electrode film and the drain is performed. It may be performed only for the purpose of activating. Therefore, it is not necessary to diffuse the dopant as conventionally. Therefore, heat treatment can be performed in a short time by RTA. Therefore, the short channel effect can be suppressed. Further, since the first gate electrode 18 and the sidewall electrode 28 constitute a floating gate, a sufficient overlap layer between the drain 14 and the floating gate (18 and 28) can be obtained. Thereby, the electric field concentration generated at the end of the floating gate is alleviated, and the resistance to gate oxide film breakdown can be improved. Furthermore, the capacitance between the floating gate (18 and 28) and the control gate (second gate electrode 22) is equal to the capacitance between the first gate electrode 18 and the second gate electrode 22, and the side wall. Since it becomes the capacity | capacitance which combined the electrostatic capacitance between the electrode 28 and the 2nd gate electrode 22, it becomes larger than before. Thereby, since the coupling ratio can be improved, the writing characteristics of the device can be improved.
[0078]
  <First embodiment>
  First embodimentAs described above, the second conductivity type first diffusion layer 12 and the second diffusion layer 14 formed in the first conductivity type region of the semiconductor substrate 10 so as to be spaced apart from each other, the first diffusion layer 12 on the semiconductor substrate 10 and the first diffusion layer 14 Straddling the diffusion layer 12 and the second diffusion layer 14,Reference exampleA description will be given of a configuration in which the same gate stacked structure 24 is formed, and a side wall electrode 70 electrically connected to the first gate electrode 18 is provided on one side wall of the gate stacked structure 24.
[0079]
  Less than,Reference exampleTo explain the differencesReference exampleThe detailed description of the same points as in FIG.
[0080]
  FIG.First embodimentFIG. 2 is a diagram for explaining a main part of the nonvolatile semiconductor memory device, and this main part is shown by a cut section. This deviceReference exampleIn the same manner as the device, a p-type Si substrate 10 is provided with a source 12 as an n-type first diffusion layer and a drain 14 as a second diffusion layer. Then, the first SiO, which is the first gate insulating film, is straddled between the source and the drain so as to be in contact with the exposed surfaces of the source 12 and the drain 14.₂The film 16, the first polysilicon electrode 18 as the first gate electrode, and the second SiO as the second gate insulating film₂A gate stacked structure 24 including a film 20 and a second polysilicon electrode 22 as a second gate electrode is provided. And also in this embodiment,Reference exampleSimilarly to the above, a gate hard mask insulating film 26 made of a silicon oxide film or a silicon nitride film is provided above the second polysilicon electrode 22.
[0081]
A sidewall electrode 70 is formed on the sidewall of the gate stacked structure 24 so as to be electrically connected to the first gate electrode 18. In this embodiment, the first SiO₂An insulating film 30 made of a silicon oxide film is formed on one side wall in the gate length direction of the gate laminated structure 24 excluding the film 16 and the first polysilicon electrode 18, and the insulating film 30 has a surface serving as a side wall electrode. A third polysilicon electrode 70 is formed. Further, in this embodiment, the side wall electrode 70 is provided on each outer side wall of the gate stacked structure 24 arranged side by side. The first polysilicon electrode 18 includes the electrode 18 and the first SiO.₂The constituent films of the gate stacked structure 24 excluding the film 16 are formed so as to protrude longer on one side in the gate length direction than the length in the gate length direction. The third polysilicon electrode 70 is provided on the protruding region 18 a of the first polysilicon electrode 18. Thereby, the first polysilicon electrode 18 and the third polysilicon electrode 70 are electrically connected. Therefore, the first polysilicon electrode 18 and the third polysilicon electrode 70 constitute a floating gate (floating gate).
[0082]
A mask insulating film 32 is provided on the entire top surface of the structure (FIG. 9).
[0083]
Such a nonvolatile semiconductor memory device is manufactured as follows.
[0084]
  FIG. 10A to FIG.First embodimentFIG. 6 is a process diagram sequentially illustrating the manufacturing process of the nonvolatile semiconductor memory device, and is a sectional view of the device being manufactured or a plan view viewed from above.
[0085]
First, the element isolation film 44 is formed on the first conductivity type semiconductor substrate 10 to separate the active region 43a and the element isolation region 43b.
[0086]
  here,Reference exampleSimilarly to the above, an element isolation film 44 made of a silicon oxide film is formed on the p-type Si substrate 10 by using the LOCOS method. Thus, the active region 43a and the element isolation region 43b are separated (see FIGS. 2A to 2C).
[0087]
Next, after the first insulating film 46 and the first electrode film 48 are sequentially formed over the entire upper surface of the semiconductor substrate 10, the first electrode film provided on the adjacent active region 43a with the element isolation region 43b interposed therebetween. 48 is electrically cut on the element isolation film 44.
[0088]
  For this reason, in this embodiment,Reference exampleIn the same manner as the first SiO 2 as the first insulating film 46.₂After the film is formed by thermal oxidation, a first polysilicon film that is the first electrode film 48 is formed using a CVD method. Thereafter, by patterning the first polysilicon film 48, the first polysilicon film 48 continuously formed on the adjacent active region 43a with the element isolation region 43b interposed therebetween is cut on the element isolation film 44. The That is, for each active region 43a, a first polysilicon film 48x that is electrically insulated from the first polysilicon film on the other active region 43a is formed (FIGS. 2D to 3A). reference).
[0089]
Next, the second insulating film 50, the second electrode film 52, and the third insulating film 54 are sequentially formed over the entire upper surface of the semiconductor substrate 10 so as to cover the first electrode film 48x.
[0090]
  For this reason, in this embodiment,Reference exampleSimilarly to the second SiO 2 film, the second SiO film, which is the second insulating film, covers the remaining first polysilicon film 48x.₂A film 50, a second polysilicon film 52 as a second electrode film, and a silicon oxide film or silicon nitride film 54 as a third insulating film are sequentially formed (FIG. 3B, FIG. 4 and FIG. 5A). reference).
[0091]
Next, by using the mask, the second insulating film 50, the second electrode film 52, and the third insulating film 54 are patterned to form a preliminary laminated structure. This preliminary laminated structure is formed in a size including a desired gate laminated structure planned region and a gate laminated structure planned region adjacent to each other with the first diffusion layer interposed therebetween.
[0092]
Therefore, in this embodiment, the second SiO 2 is formed by photolithography and the subsequent anisotropic dry etching process.₂The film 50, the second polysilicon film 52, and the third insulating film 54 are patterned. At this time, the size of the covering portion of the mask formed on the third insulating film 54 by photolithography is such that the region 74a that finally becomes the gate stacked structure and the region 76 that becomes the first diffusion layer in the gate length direction. And a gate stacked structure planned region 74b adjacent to each other. Thereafter, by etching, the second SiO 2 having the above size is obtained.₂A pre-laminated structure 72 is formed which includes the remaining portion 50y of the film, the remaining portion 52y of the second polysilicon film, and the remaining portion 54y of the third insulating film (FIG. 10A).
[0093]
Next, after forming the insulating film 78 over the upper surface of the first electrode film 48x exposed from the preliminary laminated structure 72, the side walls and the upper surface of the preliminary laminated structure 72, both sides of the preliminary laminated structure 72 from above the insulating film 78 are formed. Diffusion layer forming ions are implanted into the active region.
[0094]
For this reason, in this embodiment, SiO is used as an insulating film over the upper surface of the first polysilicon film 48x exposed from the preliminary stacked structure 72, the side wall and the upper surface of the preliminary stacked structure 72₂The film 78 is formed by thermal oxidation. Thereafter, using the preliminary laminated structure 72 as a mask, SiO₂Arsenic ions are implanted from the upper side of the film 78 at an acceleration voltage of 50 to 80 keV. As a result, ions for forming the drain 14 which is a diffusion layer are introduced into both sides of the preliminary laminated structure 72 (FIG. 10B).
[0095]
Next, after the insulating film 78x is left only on the side wall of the preliminary laminated structure 72, the third polysilicon film 80 is formed on the surface of the remaining insulating film 78x so as to be electrically connected to the first electrode film 48x. Form.
[0096]
Therefore, in this embodiment, the surface SiO₂By performing anisotropic dry etching on the film 78, the SiO formed on the side wall of the preliminary laminated structure 72₂Only the film 78x is left. Thereafter, a third polysilicon film is deposited on the entire upper surface of the substrate 10 using a CVD method, and then anisotropic dry etching is performed on the third polysilicon film. Thereby, SiO on the side wall of the preliminary laminated structure 72₂The third polysilicon film 80 remains in a sidewall shape on the surface of the film 78x. In addition, the first polysilicon film 48x exposed from the sidewall-like third polysilicon film 80 is removed by this etching. Then, the first polysilicon film 48xx remains (FIG. 10C).
[0097]
Next, a slit for dividing the third insulating film 54y, the second electrode film 52y, the second insulating film 50y, and the first electrode film 48xx is formed in the preliminary laminated structure 72.
[0098]
For this reason, in this embodiment, a resist serving as a mask for forming slits is provided on the entire top surface of the substrate 10. Then, a resist pattern 86 is formed by photolithography so that the slit forming region 82 becomes the window 84. The slit forming region 82 is formed with a source which is a common diffusion layer of two adjacent gate stacked structures having a stacked structure obtained by being divided later by a slit. Therefore, the width H in the gate length direction of the slit formation region 82 is set to a width that can be used as a diffusion layer (FIG. 11A). Thereafter, using the resist pattern 86 as a mask, the third insulating film 54y, the second polysilicon film 52y, and the second SiO exposed from the window 84 are exposed.₂The portions of the film 50y and the first polysilicon film 48xx are etched. As a result, a slit 88 is formed in the preliminary laminated structure 72, and two gate laminated structures 24 are formed by the slit 88.
[0099]
Next, ions for forming a diffusion layer are implanted from the upper side of the first insulating film 46 (16) exposed in the slit 88.
[0100]
Therefore, in this embodiment, SiO exposed in the slit 88 using the two gate stacked structures 24 as a mask.₂Arsenic ions are implanted from the upper side of the film 46 (16) with an acceleration voltage of 50 to 80 keV. Thus, the dopant for forming the source 12 is introduced into the slit 88 (FIG. 11B).
[0101]
Thereafter, heat treatment is performed by RTA to activate the dopant for forming the source 12 in the slit 88 and the dopant for forming the drain 14 that has already been implanted.
[0102]
FIG. 12A shows the structure at this time when viewed from above. FIG. 11B shows a cross section cut along the line II-II in FIG.
[0103]
Next, the third electrode film 80 continuously formed on the active region 43a adjacent to the element isolation region 43b is electrically cut on the element isolation film 44.
[0104]
Therefore, in this embodiment, a resist pattern (not shown) is provided on the remaining third polysilicon film 80 in which a window is formed so that the film is divided on the element isolation region. Thereafter, isotropic dry etching or wet etching is performed using this resist pattern as a mask. As a result, the portion 80x of the third polysilicon film 80 exposed from the mask window is removed. Thereby, the third polysilicon film 70 is formed for each active region 43a (FIG. 12B). FIG. 12B is a plan view of the structure as viewed from above, and is a process diagram subsequent to FIG. However, the configuration shown by the cut along the line II-II in FIG. 12B is the same as the II-II cross-sectional view in FIG. 12A, that is, FIG.
[0105]
As a result, the first SiO 2 is formed on the substrate on which the source 12 and the drain 14 are formed.₂The first gate insulating film 16 made of the film 46, the first polysilicon electrode 18 as the first gate electrode made of the remaining portion 48xx of the first polysilicon film, the second SiO₂The second gate insulating film 20 made of the remaining portion 50y of the film, the second polysilicon electrode 22 as the second gate electrode made of the remaining portion 52y of the second polysilicon film, and the third SiO₂Film (Si_ThreeN_FourA gate laminated structure 24 in which a gate hard mask insulating film 26 composed of the remaining portion 54y of the film) is laminated in this order, and a third polysilicon electrode 18 electrically connected to one side wall of the gate laminated structure 24. A structure including the third polysilicon electrode 70 as a side wall electrode made of the remaining portion of the polysilicon film 80 is obtained (FIG. 11B).
[0106]
Thereafter, a mask insulating film 32 is formed on the entire upper surface of the substrate 10 by thermal oxidation (FIG. 9).
[0107]
  ThisFirst embodimentThus, a memory cell of the nonvolatile semiconductor memory device can be obtained.
[0108]
  By manufacturing the device using such a method, the heat treatment may be performed only for activating the dopant, so that the heat treatment can be performed in a short time by RTA. Therefore, the short channel effect can be suppressed. Also,Reference exampleSimilarly to the above, the electric field concentration generated at the end of the floating gate is alleviated, and the resistance to gate oxide film breakdown can be improved. In addition, since the coupling ratio can be improved, the writing characteristics of the device can be improved.
[0109]
Furthermore, in this embodiment, since the patterning for forming the laminated structure is performed at twice the pitch of the desired laminated structure, the patterning process can be easily performed even if the apparatus is miniaturized.
[0110]
Further, in the manufactured device, since the sidewall-like third polysilicon film is not formed on the opposite side walls of the two adjacent gate stacked structures, the third polysilicon films between the adjacent gate stacked structures are not formed. Short-circuit occurrence rate can be reduced. Therefore, the reliability of the apparatus can be improved.
[0111]
  <Second embodiment>
  Second embodimentAsFirst embodimentSimilarly, a device in which a side wall electrode electrically connected to the first gate electrode film is provided on one side wall of the gate stacked structure,First embodimentAn example of manufacturing with a different manufacturing method will be described.
[0112]
  First,Reference exampleIn the same manner, the element isolation film 44 is formed on the p-type Si substrate 10 by LOCOS (see FIGS. 2A to 2C).
[0113]
  next,Reference exampleSimilarly to the first SiO 2 on the entire upper surface of the substrate 10.₂A film 46 is formed, and this first SiO₂A first polysilicon film 48 is formed on the film 46 (see FIG. 2D). Thereafter, the first polysilicon film 48 is patterned, and the first polysilicon film 48 continuously formed on the adjacent active region 43a with the element isolation region 43b interposed therebetween is cut on the element isolation film 44. (See FIG. 3A).
[0114]
Thereafter, the second SiO film is covered so as to cover the remaining first polysilicon film 48x.₂A film 50 is formed and this second SiO₂A second polysilicon film 52 is formed on the film 50. Further, a third insulating film (third SiO film) is formed on the second polysilicon film 52.₂Film) 54 (see FIGS. 3B, 4 and 5A). Next, these second SiO₂Film 50, second polysilicon film 52 and third SiO₂The film 54 is patterned to form a preliminary gate stacked structure 56 composed of the remaining portions 50x, 52x and 54x of the film (see FIG. 5B).
[0115]
  afterwards,Reference exampleSimilarly to the upper surface of the first polysilicon film 48x exposed from the preliminary gate stacked structure 56, the side wall and the upper surface of the preliminary gate stacked structure 56, SiO.₂A film 58 is formed. Next, using the preliminary gate laminated structure 56 as a mask, arsenic ions are implanted into the active regions on both sides of the mask 56. Thereafter, arsenic ions are activated by RTA (see FIG. 5C).
[0116]
  next,Reference exampleSimilarly to SiO 2, SiO 2 is applied only to the side wall of the preliminary gate laminated structure 56 by anisotropic etching.₂After the film 30 is left, a third polysilicon film 60 is deposited on the entire upper side of the substrate 10 (see FIG. 6A). Thereafter, anisotropic dry etching is performed to leave the third polysilicon film 60x in a sidewall shape on the side wall of the preliminary gate stacked structure 56 (see FIG. 6B). Further, dry etching is performed to remove the portion of the first polysilicon film 48x exposed from the sidewall-like third polysilicon film 60x. As a result, the first polysilicon film 18 remains (see FIG. 6C).
[0117]
As a result, the first SiO 2 is formed on the substrate 10 on which the source 12 and the drain 14 are formed.₂A first gate insulating film 46 (16) made of a film, a first polysilicon electrode 18 as a first gate electrode made of a remaining portion 48x of the first polysilicon film, a second SiO₂The second gate insulating film 20 made of the remaining portion 50x of the film, the second polysilicon electrode 22 as the second gate electrode made of the remaining portion 52x of the second polysilicon film, and the third SiO₂Film (Si_ThreeN_FourA gate laminated structure 24 in which a gate hard mask insulating film 26 composed of the remaining portion 54x of the film) is laminated in this order, and a third electrically connected to the first polysilicon electrode 18 on both side walls of the gate laminated structure 24. A structure including the third polysilicon electrode 28 as a side wall electrode made of the remaining portion of the polysilicon film is obtained.
[0118]
Next, in this embodiment, a resist is deposited on the entire upper surface of the substrate 10 so as to cover the gate stacked structure 24. Thereafter, the resist is patterned so that at least a region including the third polysilicon film 28 provided on the opposing sidewalls of the two adjacent gate stacked structures 24 is exposed (FIG. 13A).
[0119]
  Next, anisotropic dry etching is performed using the formed resist pattern 90 as a mask. As a result, the third polysilicon film 28 and the portion 18a of the first polysilicon film therebelow are removed. When the gate hard mask insulating film 26 is exposed from the resist pattern window 92, the gate hard mask insulating film is exposed.Membrane 26 is also partially etched.
[0120]
  Thereafter, after removing the resist pattern (FIG. 13B),Reference exampleIn the same manner as the above, a resist pattern in which the region on the element isolation region becomes a window is newly provided in the remaining third polysilicon film 28, and this resist pattern is used as a mask to expose the third polysilicon film exposed from the mask window. The portion 28 is removed by etching (similar to FIGS. 12A and 12B).
[0121]
Thereafter, a mask insulating film 32 is formed on the entire upper surface of the substrate 10 by thermal oxidation (FIG. 13C).
[0122]
  As a result, a device is obtained in which a side wall electrode electrically connected to the first gate electrode is provided on one side wall of the gate stacked structure. With the device of this structure,First embodimentThe same effect can be obtained.
[0123]
【The invention's effect】
As is apparent from the above description, according to the nonvolatile semiconductor memory device of the present invention, at least one memory cell is provided on the semiconductor substrate, and the memory cell is in the first conductivity type region of the semiconductor substrate. And a second conductivity type first diffusion layer and a second diffusion layer which are exposed on the upper surface of the semiconductor substrate and spaced apart from each other, and the first diffusion layer and the second diffusion layer on the semiconductor substrate. A gate stacked structure in which the first gate insulating film, the first gate electrode, the second gate insulating film, and the second gate electrode are stacked in this order across the diffusion layer, and on the side wall of the gate stacked structure, And a side wall electrode formed in electrical connection with the first gate electrode.
[0124]
Since the sidewall electrode is electrically connected to the first gate electrode, the electrode constituted by the first gate electrode and the sidewall electrode substantially functions as a floating gate (floating gate). This increases the area of the insulating film between the second gate electrode serving as the control gate and the floating gate, so that the capacitance between the control gate and the floating gate can be increased. Therefore, since the coupling ratio is improved, the writing characteristics of this device can be improved. Further, due to the sidewall electrode, the end portion of the floating gate is in a position that bites into the diffusion layer region formed in the semiconductor substrate as compared with the conventional case. Therefore, a sufficient overlap layer between the diffusion layer and the floating gate can be obtained. Thereby, it is possible to alleviate the electric field concentration generated at the end of the floating gate as compared with the prior art, and to reduce the possibility of gate oxide film destruction.
[0125]
In manufacturing the nonvolatile semiconductor memory device described above, the memory cell is preferably formed by including the following steps (1) to (8).
[0126]
(1) A step of separating an active region and an element isolation region by forming an element isolation region on a first conductivity type semiconductor substrate.
[0127]
(2) After sequentially forming the first insulating film and the first electrode film over the entire upper surface of the semiconductor substrate, the first electrode film provided on the active region adjacent to the element isolation region is formed on the element isolation region. Electrical cutting process.
[0128]
(3) A step of sequentially forming a second insulating film, a second electrode film, and a third insulating film over the entire upper surface of the semiconductor substrate so as to cover the first electrode film.
[0129]
  (4) By patterning the second insulating film, the second electrode film, and the third insulating film using a mask,Including a second gate electrode as a control gate formed as a remaining portion of the second electrode filmForming a preliminary gate stacked structure;
[0130]
(5) After forming an insulating film over the upper surface of the first electrode film exposed from the preliminary gate stacked structure, the side walls and the upper surface of the preliminary gate stacked structure, the insulating film is formed on the active regions on both sides of the preliminary gate stacked structure from above On the other hand, a step of implanting ions for forming the first and second diffusion layers.
[0131]
(6) A step of leaving an insulating film only on the side wall of the preliminary gate stacked structure and then forming a third electrode film on the surface of the remaining insulating film so as to be electrically connected to the first electrode film.
[0132]
  (7) removing the region of the first electrode film exposed from the third electrode filmAs a result, the first gate electrode is formed as the remaining portion of the first electrode film.Process.
[0133]
  (8)Formed on adjacent active regions across the isolation regionElectrically cut the third electrode film on the device isolation filmAs a result, a floating gate composed of the sidewall electrode formed as the remaining portion of the third electrode film and the first gate electrode is formed.Process.
[0134]
According to this manufacturing method, there is no need to perform heat treatment for obtaining an overlap layer of the first gate electrode and side wall electrode to be a floating gate and the diffusion layer. For this reason, the short channel effect which may arise by a high-temperature heat treatment process can be suppressed. Further, it is possible to avoid the possibility that the write characteristics are deteriorated.
[Brief description of the drawings]
[Figure 1]Reference example2 is a schematic configuration diagram of a memory cell of the nonvolatile semiconductor memory device shown in FIG.
FIG. 2 (A) to (D)Reference exampleFIG. 4 is a manufacturing process diagram of the nonvolatile semiconductor memory device of FIG.
FIG. 3 (A) and (B) are:Reference exampleFIG. 3 is a manufacturing process diagram subsequent to FIG. 2 for the non-volatile semiconductor memory device of FIG.
FIG. 4 is a plan view seen from above the structure at the time of FIG. 3 (B).
5A is a structural diagram of the structure at the time of FIG. 3B, and is shown by a cut surface having a cross section different from that in FIG. 3B; FIGS. FIG. 6 is a manufacturing process diagram following FIG.
6A to 6C are manufacturing process diagrams subsequent to FIG. 5;
7A is a plan view seen from above the structure at the time of FIG. 6C, and FIG. 7B is a manufacturing process diagram subsequent to FIG.
FIGS. 8A to 8C are manufacturing process diagrams continued from FIG. 6 and shown by a cross-section cut along the line III-III in FIG.
FIG. 9First embodiment2 is a schematic configuration diagram of a memory cell of the nonvolatile semiconductor memory device shown in FIG.
FIGS. 10A to 10C areFirst embodimentIt is a manufacturing process figure with which it uses for description.
11A and 11B are manufacturing process diagrams subsequent to FIG.
12A is a plan view seen from above the structure at the time of FIG. 11B, and FIG. 12B is a manufacturing process diagram subsequent to FIG.
FIG. 13 (A) to (C)Second embodimentIt is a manufacturing process figure with which it uses for description.
14A is a configuration diagram of a memory cell of a conventional nonvolatile semiconductor memory device, and is a plan view seen from above. FIG. (B) is a block diagram which shows the cut surface of the cross section cut along the xx line of (A).
15A to 15C are manufacturing process diagrams of a conventional nonvolatile semiconductor memory device.
16A and 16B are manufacturing process diagrams subsequent to FIG.
[Explanation of symbols]
  10, 100: Semiconductor substrate (p-type Si substrate)
  12, 102: first (impurity) diffusion layer (source)
  14, 104: second (impurity) diffusion layer (drain)
  16, 106: first gate insulating film (first SiO 2₂film)
  18, 108: first gate electrode (first polysilicon electrode, remaining portion of the first polysilicon film)
  18a: protruding area
  20, 110: second gate insulating film (second SiO₂film)
  22, 112: second gate electrode (second polysilicon electrode)
  24, 116: gate stacked structure
  26, 114: Gate hard mask insulating film
  28, 70: Side wall electrode (third polysilicon electrode)
  30: Insulating film
  32, 118: Mask insulating film
  40, 120: pad oxide film
  42: Nitride film
  42x, 122: Remaining portion of nitride film
  43a, 126a: active region
  43b, 126b: element isolation region
  44, 124: element isolation film
  46, 128: first insulating film (first SiO 2₂film)
  48: First electrode film (first polysilicon film)
  48x, 130: Cut first electrode film
  48xx: Remaining portion of the first polysilicon film
  50, 132: second insulating film (second SiO₂film)
  50x, 50y: remaining portion of the second insulating film
  52, 134: second electrode film (second polysilicon film)
  52x, 52y: Remaining portion of the second electrode film
  54, 136: third insulating film (third SiO₂Film (Si_ThreeN_Fourfilm))
  54x, 54y: remaining portions of the third insulating film
  56: Preliminary gate stack structure
  58: Insulating film (SiO₂film)
  60: Third electrode film (third polysilicon film)
  60x: Remaining portion of the third electrode film
  62, 84, 92: Window
  64, 86, 90: resist pattern
  72: Preliminary laminated structure
  74a: a region having a gate stacked structure
  74b: Adjacent gate stacked structure planned region
  76: Region to be the first diffusion layer
  78: Insulating film (SiO₂film)
  78x: remaining portion of insulating film (side wall SiO₂film)
  80: Third polysilicon film (in the shape of a side wall)
  80x: exposed third silicon film portion
  82: Slit formation region
  88: Slit

Claims (5)

In a nonvolatile semiconductor memory device in which a plurality of memory cells are provided on a semiconductor substrate,
Each of the memory cells
A second conductivity type first diffusion layer and a second diffusion layer formed in the region of the first conductivity type of the semiconductor substrate, which are exposed on the upper surface of the semiconductor substrate and spaced apart from each other;
A first gate insulating film, a first gate electrode, a second gate insulating film, and a second gate electrode as a control gate are formed on the semiconductor substrate and across the first diffusion layer and the second diffusion layer. A gate stack structure formed by sequentially stacking,
A sidewall electrode formed on the side wall of the gate stacked structure and electrically connected to the first gate electrode ;
A floating gate is constituted by the first gate electrode and the sidewall electrode,
Of the memory cells, two memory cells adjacent to each other along the gate length direction share the first diffusion layer,
The sidewall electrode is provided on one side wall on the second diffusion layer side in the gate length direction of the gate stacked structure, and is not provided on one side wall on the first diffusion layer side. > A non-volatile semiconductor memory device. The nonvolatile semiconductor memory device according to claim 1,
The first diffusion layer is a source;
The nonvolatile semiconductor memory device, wherein the second diffusion layer is a drain . The nonvolatile semiconductor memory device according to claim 1 or 2,
A nonvolatile semiconductor memory device, wherein an insulating film is interposed between the sidewall electrode, the second gate insulating film, and the second gate electrode. In manufacturing a nonvolatile semiconductor memory device in which a plurality of memory cells are provided on a semiconductor substrate,
The step of forming each of the memory cells includes
Forming an element isolation region in a first conductivity type semiconductor substrate to separate the active region and the element isolation region;
A first insulating film and a first electrode film are sequentially formed over the entire upper surface of the semiconductor substrate, and then a first electrode film provided on an active region adjacent to the element isolation region is disposed on the element isolation region. Electrically disconnecting with,
Sequentially forming a second insulating film, a second electrode film and a third insulating film over the entire upper surface of the semiconductor substrate so as to cover the cut first electrode film;
A spare gate including a second gate electrode as a control gate formed as a remaining portion of the second electrode film by patterning the second insulating film, the second electrode film, and the third insulating film using a mask Forming a laminated structure;
After forming an insulating film over the upper surface of the first electrode film exposed from the preliminary gate stacked structure, the sidewalls and the upper surface of the preliminary gate stacked structure, the active on both sides of the preliminary gate stacked structure from above the insulating film Implanting ions for forming the first and second diffusion layers into the region;
Forming the third electrode film on the surface of the remaining insulating film so as to be electrically connected to the first electrode film after the insulating film is left only on the side wall of the preliminary gate stacked structure; ,
Forming a first gate electrode as a remaining portion of the first electrode film by removing a region of the first electrode film exposed from the third electrode film;
The third electrode film formed on the active region adjacent to the element isolation region is electrically cut on the element isolation film to form a remaining portion of the third electrode film. Forming a side wall electrode and a floating gate comprising the first gate electrode ,
Between the step of removing the region of the first electrode film exposed from the third electrode film and the step of cutting the third electrode film,
Wherein one of said third electrode film formed on both sides of the preliminary gate stack, over there the containing and a step in which the first ion diffusion layer formation is removed third electrode film of the implanted active region side and A method for manufacturing a nonvolatile semiconductor memory device. In manufacturing a nonvolatile semiconductor memory device in which a plurality of memory cells are provided on a semiconductor substrate,
The step of forming each of the memory cells includes
Forming an element isolation region in a first conductivity type semiconductor substrate to separate the active region and the element isolation region;
A first insulating film and a first electrode film are sequentially formed over the entire upper surface of the semiconductor substrate, and then a first electrode film provided on an active region adjacent to the element isolation region is disposed on the element isolation region. Electrically disconnecting with,
Sequentially forming a second insulating film, a second electrode film and a third insulating film over the entire upper surface of the semiconductor substrate so as to cover the cut first electrode film;
Using the mask, the second insulating film, the second electrode film, and the third insulating film are patterned to form a laminated structure having a double pitch in the gate length direction of the desired gate laminated structure. Process,
After forming an insulating film over the upper surface of the first electrode film exposed from the laminated structure, the sidewalls and the upper surface of the laminated structure, the upper side of the insulating film is exposed to the active regions on both sides of the laminated structure . A step of implanting ions for forming a diffusion layer of 2 ;
Forming the third electrode film so as to be electrically connected to the first electrode film on the surface of the remaining insulating film after the insulating film is left only on the sidewall of the laminated structure;
Removing a region of the first electrode film exposed from the third electrode film;
A slit that divides the third insulating film, the second electrode film, the second insulating film, and the first electrode film is formed with respect to the stacked structure, and a first gate electrode as a remaining portion of the first electrode film, And forming a second gate electrode as a control gate as the remaining portion of the second electrode film ;
Implanting ions for forming a first diffusion layer from above the first insulating film exposed in the slit;
By electrically cutting the third electrode film formed on the active region adjacent to the element isolation region across the element isolation region , the second electrode film is used as a remaining portion of the third electrode film. And a step of forming a floating gate composed of a side wall electrode provided on one side wall on the side where ions for forming the diffusion layer are implanted and the first gate electrode. Device manufacturing method.

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