JP4401120B2 - Electrostatic discharge protection element - Google Patents

Description

  The present invention relates to an electrostatic discharge protection element that is formed in a semiconductor integrated circuit and protects a circuit element from destruction due to electrostatic discharge, and more particularly to an electrostatic discharge protection element that utilizes a parasitic bipolar.

  Conventionally, in order to protect a circuit element in a semiconductor integrated circuit from electrostatic discharge (hereinafter also referred to as ESD (Electro Static Discharge)), an electrostatic discharge protection element (hereinafter also referred to as ESD protection element) composed of a diode or a resistance element. Was used. Recently, an ESD protection element provided in a CMOS (Complementary Metal Oxide Semiconductor) integrated circuit has a low resistance and higher discharge capability than an ESD protection element composed of a diode or a resistance element. It has been replaced by a MOS type protection element using This MOS type protective element is a protective element that utilizes the snapback phenomenon of a MOSFET (MOS Field Effect Transistor).

  Even in a MOS type protection element made of a parasitic bipolar transistor, there is a limit to the ability to pass the current, and the protection performance often does not satisfy the required level unless the width of the protection element is increased to about 400 to 800 μm. However, in general, in an integrated circuit, the layout is limited by the arrangement of bonding pads and the like, and it is often necessary to keep the MOS type protection element within a specified area. For this reason, the MOS type protection element is not a single element, but a plurality of small MOSFETs called fingers having a width of about 10 to 50 μm are arranged in a direction perpendicular to the direction of current flow (hereinafter referred to as a lateral direction). Thus, a method is adopted in which the MOS type protection elements are connected in parallel to each other and the MOS type protection elements are efficiently arranged within a specified area. At this time, there is a method of connecting a plurality of fingers in parallel with each finger having a common source and drain, and a method of arranging small MOSFETs individually and connecting them in parallel (for example, non- (See Patent Document 1).

  FIG. 9 is a plan view showing an input protection element using a snapback phenomenon of an NMOSFET, which is a conventional MOS type protection element, and FIG. 10 is a diagram showing a cross section taken along line AA 'shown in FIG. FIG. 11 is a graph showing the operating characteristics of the MOS type protection element with the voltage applied to the protection element on the horizontal axis and the current flowing through the protection element on the vertical axis. As shown in FIGS. 9 and 10, in the MOS type protection element 101, a plurality of gate electrodes 103 extending in one direction are provided on the P type substrate 102 in parallel with each other, and the P type substrate 102. The region immediately below the gate electrode 3 on the surface of the gate electrode is a channel region 104. A region between the channel regions 104 on the surface of the P-type substrate 102 is a source region 105 or a drain region 106, and the source regions 105 and the drain regions 106 are alternately arranged.

Thereby, a plurality of MOSFETs 111 are formed, and the source region or the drain region is shared between the MOSFETs 111 adjacent to each other. On the surfaces of the source region 105 and the drain region 106, a plurality of contacts 107 are arranged in a line along the direction in which the gate electrode 103 extends. A guard ring 108 made of a P ⁺ diffusion region is provided on the surface of the P-type substrate 102 so as to surround the plurality of MOSFETs 111 and is connected to the ground wiring 109. The guard ring 108 is provided for the purpose of preventing latch-up. Further, an input pad 110 is connected to the contact 107 formed on the surface of the drain region 106.

  Next, the operation of the MOS protection element 101 will be described with reference to FIGS. When a current surge is input to the input pad 110, the current surge flows into the drain region 106 via the contact 107, and the drain voltage increases. When the drain voltage becomes equal to or higher than the voltage indicated by voltage Vt0 in FIG. 11, an avalanche breakdown starts at the PN junction between the drain region 106 and the channel region 104, and a substrate current flows. At this time, a parasitic bipolar is formed in which the source region 105 of each finger serves as an emitter, the P-type substrate 102 including the guard ring 108 serves as a base, and the drain region 106 serves as a collector. Due to the current flowing in the P-type substrate 102, a potential difference corresponding to the product of this current and the resistance of the P-type substrate 2 is generated in the P-type substrate 102, and the potential near the bottom surface of the source region 105 in the P-type substrate 102 is , Rising with respect to the guard ring 108. As shown in FIG. 11, when the voltage applied to the MOS protection element 101 becomes the voltage Vt1, the potential near the bottom surface of the source region 105 with respect to the guard ring 108 causes the PN junction between the source region 105 and the channel region 104 to be The forward bias is, for example, about 0.7 V, and the PN junction is forward biased to allow further current to flow, and the parasitic bipolar is turned on to enter a low resistance state. As a result, a larger current flows. This phenomenon is called snapback, and the voltage Vt1 is called snapback start voltage or trigger voltage.

  It should be noted that the IV measurement as shown in FIG. 11 is normally performed by a TLP (Transmission Line Pulser) because a normal current-voltage measurement apparatus has a long current duration and is destroyed before entering the snapback state. ) Is used. In this method, a rectangular current waveform having a duration of about 100 nsec is added to a DUT (device under test), and the current value and voltage value of the DUT are read from the change in voltage and current (for example, non-current). (See Patent Document 2). In general, the DUT breakdown current It2 [A] measured by TLP and the DUT breakdown voltage V [V] measured by the human body charging model test (HBM test) are empirically V = It2 × 1500. It is said that there is a relationship.

  In a MOS type protection element composed of a plurality of fingers (multi-finger), the operation differs for each finger. This difference in operation can be explained as being due to a difference in substrate resistance. That is, since the distance from each finger to the ground electrode (usually the guard ring) is different, the substrate resistance, that is, the base resistance of the parasitic bipolar transistor is different, and as a result, each charge accumulation after avalanche breakdown causes each A difference occurs in a local voltage formed in the junction region between the source region and the channel region of the MOSFET. Thereby, the timing at which each parasitic bipolar transistor reaches the snapback voltage is different, and the timing at which each parasitic bipolar transistor is turned on is different. Actually, as shown in FIG. 9 and FIG. 10, the substrate potential is coupled to the substrate current between the fingers, the substrate is driven by the three-dimensional current route in each finger, and the substrate resistance in the width direction inside the finger. There are complex factors that cause differences in substrate resistance between fingers, such as different resistances.

  When a current flows through the drain side PN junction of the finger, that is, the PN junction between the drain region and the channel region, the potential difference at the PN junction portion occupies most of the potential difference in the finger. Heat is generated in the joining area. There is a positive correlation between the current and the junction temperature, and the current increases as the temperature increases. In other words, current is concentrated on some fingers due to process variations and structures, etc., or there are variations in contact resistance and drain resistance, etc. within the fingers, and current is applied to specific fingers or specific areas within the fingers. When it concentrates, it triggers, and the PN junction of the finger or the region in the finger where the current is concentrated generates heat, the temperature rises, and a positive feedback occurs that the amount of current increases. Melts. For this reason, before the other fingers are turned on, the first turned-on finger is destroyed, and the multi-finger structure cannot be used.

  Conventionally, when the surface of the diffusion layer is not metal-silicided, the resistance value of this diffusion layer is about several hundred Ω, which is about the same as the resistance value of the transistor itself. The potential difference in the ballast resistance portion of the finger, that is, the portion other than the PN junction is increased, and the current flowing through the protection element is limited. For this reason, the above-mentioned destruction phenomenon has not become a significant problem. At this time, the current-voltage characteristic of the protection element is as indicated by a line 112 in FIG.

  However, recently, as the circuit scale increases and the required performance is improved, it is necessary to shorten the gate length of the transistor. At this time, in order to suppress the short channel effect of the MOSFET, it is necessary to reduce the junction depth of the source / drain diffusion layer. When the junction depth is reduced, the resistance of the source / drain diffusion layer is increased. As a countermeasure, a technique for forming a metal silicide on the surface of the diffusion layer has been developed (see, for example, Patent Documents 1 and 2). .) In particular, the process of forming metal silicide simultaneously on the gate electrode and the diffusion layer is called a salicide process. This is because, after the formation of the source / drain, the oxide film on the gate electrode and the source / drain region is removed, and a metal such as cobalt, nickel, or titanium is deposited on this region, and is reduced by rapid heating (RTA) or the like. This is a method of simultaneously reducing the parasitic resistance of the source region, the drain region, and the gate electrode by forming a metal silicide of resistance and then selectively removing unreacted metal and high resistance silicide.

  As shown by line 112 in FIG. 11, the layer resistance of the diffusion layer formed of a normal silicon layer is several tens to several hundreds Ω / □, but as shown by line 113 in FIG. By doing so, the layer resistance becomes about several to 20 Ω / □. That is, the resistance of the drain region, which has previously served as a protective resistance, becomes extremely small and can no longer play its role. As a result, in the case of the multi-finger structure, the voltage (breakdown voltage) Vt2 through which the breakdown current It2 that destroys the protection element flows becomes lower than the spanback start voltage Vt1, and when one finger snaps back, Before the finger became low resistance, it came to breakage as it was, and the protection performance against ESD was remarkably lowered.

  As a countermeasure, basically, a technique for increasing the resistance of the drain region only for the ESD protection element is used. As shown in FIG. 11, by adding a ballast resistor to each finger, the resistance of the drain region is adjusted so that the breakdown voltage is sufficiently higher than the snapback start voltage, that is, Vt1 <Vt2. ing. In FIG. 11, the difference between the inclination of the line 112 and the inclination of the line 113 is the ballast resistance, and most of the ballast resistance is, for example, the resistance of the drain region.

  In the MOS-type protective element having a multi-finger structure, by adjusting the ballast resistance of the protective element so that the minimum value of the breakdown voltage Vt2 is larger than the maximum value of the snapback voltage Vt1 for all fingers, Can be snapped back. Thereby, high protection performance can be secured. That is, if the ballast resistance value is increased, all fingers can be surely snapped back.

  Even when all fingers snap back, the higher the ballast resistance, the more current variations within the fingers can be absorbed. For this reason, generally, when considering the criterion of whether or not the ESD protection element itself is destroyed, the breakdown current tends to increase as the ballast resistance increases.

  However, when a MOS protection element is actually used as an input / output protection element, it is often impossible to apply excessive voltage stress to the protected element. For example, in a product that requires an operating frequency of about 1 GHz, the value of the protective resistance immediately before the input inverter needs to be extremely small. That is, if an excessive voltage is applied to the protective element disposed at this position, the secondary protective element, the inverter to be protected, and the like are destroyed. In order to avoid such a phenomenon, the dynamic resistance value from when the current starts to flow to the protection element until the snapback is started, that is, the resistance value corresponding to the slope between the voltages Vt0 to Vt1 shown in FIG. The clamp voltage (that is, the voltage of the protective element itself, that is, the voltage applied to the protected element when the protective element is discharging an ESD surge) is sufficiently small so that the protected element is not destroyed. It must be designed to be. Thus, when evaluating the performance of the ESD protection element, the dynamic resistance value must be considered as an index together with the breakdown current of the ESD protection element itself.

  The ballast resistor added to the drain region includes (1) a method of increasing the N-well resistance or LDD resistance, (2) a method of forming a silicide blocking region where no silicide is formed on the drain region, and (3) a silicide is formed. A method of lengthening the diffusion layer, (4) a method of dividing the diffusion layer on which the silicide is formed, and (5) a method of adding resistance by wiring, contacts, vias, etc. are conceivable. Hereinafter, it demonstrates in order.

  (1) As a method of increasing the N-well resistance or LDD resistance, there is a method of reducing the impurity concentration of the N-well or LDD to increase the resistance value of these portions to obtain a ballast resistance (for example, Patent Document 3). reference.).

  (2) As a method of forming a silicide blocking region on the drain region, the drain region of the protection element transistor is masked to form a silicide blocking region, only the source region is silicided, and the gate electrode is made to have a polycide structure. There are ways to increase ESD performance. In addition, a method has been proposed in which a large number of silicide blocking regions are provided on the drain region, the length of the silicided diffusion layer (current path) is increased, and the drain resistance value is substantially increased (for example, (See Patent Documents 4 to 7.)

  Since the resistance value of the silicide blocking region is normally 150 to 200Ω / □, an appropriate resistance value can be obtained by setting the width of the silicide blocking to about 2 μm. That is, normally, the breakdown current It2 of a fully silicided NMOS transistor is about 3 to 5 mA / μm. Therefore, if the resistance value of the silicide blocking region is 300 Ω / μm, the potential difference between both ends of this region is (current Value × resistance value) of about 0.9 to 1.5V. When this potential difference is added to the snapback voltage Vsb, the value exceeds Vt1. In a device with added silicide blocking resistance, this silicide blocking resistor plays the role of ballast resistance, that is, prevents current concentration in a single finger, and the breakdown current is higher than that of a fully silicided device. It becomes.

  However, in practice, when a low-resistance silicide layer remains between the ballast resistor and the gate electrode, current often flows in the lateral direction, that is, in the direction in which the transistors are arranged. . When the current flows in the lateral direction, the current tends to concentrate on the finger that snapped back first, and the above-described problem is likely to occur. Thus, a technique is disclosed in which the width of the silicide layer formed in a portion of the drain region in contact with the channel region is set to the minimum width allowed by the design rule (see, for example, Patent Document 8).

  FIG. 12 is a plan view showing the ESD protection element described in Patent Document 8. FIG. As shown in FIG. 12, a silicide layer 117 is formed on the surface of the drain region 116 in the MOSFET 115. An opening 118 is formed in the silicide layer 117, and a band-shaped portion 120 is formed at the end of the silicide layer 117 on the gate electrode 119 side. The width of the strip 120 is the minimum width allowed by the design rule. Thereby, it is suppressed by a thin wire | line effect that an electric current flows through the strip | belt-shaped part 120 to a horizontal direction, and it prevents that an electric current concentrates on a specific finger.

  (3) The method of lengthening the diffusion layer formed with silicide does not want to reduce the dynamic resistance when the protective element is turned on, such as when a very low clamp voltage is required, such as when protecting the power supply. Applies to In this case, since it is not desired to add a ballast resistor that becomes an extra resistor, as a suboptimal measure, the position where the contact is disposed is separated from the end of the drain and protected by the resistance of the silicide region.

  (4) Various methods for dividing the diffusion layer on which the silicide is formed have been studied. In the above description, it is assumed that a multi-finger MOS type protection element is used for input / output protection. However, there are applications in which the clamp voltage is desired to be extremely low, such as a power supply protection element. In that case, it is necessary not to use the drain ballast resistor. As an example, for example, a structure has been proposed in which a diffusion layer between contacts is separated so that current does not concentrate excessively on one finger (see, for example, Patent Document 9). This allows only one drain contact to pass current through the gate region near the diffusion layer connected to that drain contact. For this reason, it is difficult for current to flow from the adjacent drain contact, and current concentration is prevented. Also disclosed is a technique of providing a current separation slit (current divider) in the drain region to limit the current flowing in the lateral direction until just before the channel region (see, for example, Patent Document 10). There are also proposed a technique for connecting the source portion instead of dividing the source portion and a technique for arranging the N-well resistance element in a direction perpendicular to the gate electrode (see, for example, Patent Document 11).

  (5) The method of adding resistance by wiring, contacts, vias, etc. is to divide the metal wiring or polysilicon wiring finely and form a ballast resistor by forming a resistance element including the contacts and vias, and the current This is a method of restricting the route, and is called “back-end ballast”. According to this method, since it is not necessary to provide a silicide blocking step, there is an advantage that the process is simplified (for example, see Non-Patent Document 3 and Patent Document 12).

Li, T., Tsai, CH Rosenbaum, E. Kang, SM, etc., “Substrate resistance modeling and circuit-level simulation of parasitic device coupling effects for CMOS I / O circuits under ESD stress” Electrical Overstress / Electrostatic Discharge Symposium Proceedings, 1998 , 6-8 Oct. 1998 pp. 281-289 Barth, J. et al. “TLP calibration, correlation, standards, and new techniques [ESD test]” Electrical Overstress / Electrostatic Discharge Symposium Proceedings 2000, 2000 pp. 85-96 JP-A-5-75045 JP-A-5-259115 JP 9-507723 A JP 63-07553 A JP-A-5-3173 Japanese Patent No. 2773221 US Pat. No. 6,476,449 Japanese Patent No. 3319445 Japanese Patent No. 2996722 US Patent Application Publication No. 2002/0074602 US Pat. No. 5,742,083 Verhaege, K.G., Russ, C.C., "Wafer cost reduction through design of high performance fully silicided ESD devices" Electrical Overstress / Electrostatic Discharge Symposium Proceedings 2000, 2000 pp. 18-28 US Patent Application Publication No. 2002/0033507

  However, the conventional techniques described above have the following problems. As a method of adding a ballast resistor to the drain region, (1) the method of increasing the N-well resistance or LDD resistance has a problem that it is difficult to calculate the resistance value. In this case, the maximum resistance value is about 2 kΩ per 1 μm of the element. Even if the distance between the impurity layers is minimized within the limit in which the resistance value can be controlled, the resistance value is reduced only to about 500Ω, and the resistance value becomes larger than necessary. For this reason, there is a problem that the dynamic resistance becomes too high. Also, this method cannot suppress current concentration on a specific finger or a part thereof.

  (2) In the method of forming a silicide blocking region in which no silicide is formed on the drain region, as described above, in order to obtain a fine line effect by narrowing the width of the silicide layer in order to avoid current concentration, the resistance value is increased. There is a problem of large variation. When the resistance value varies, the protection performance against ESD becomes unstable. In order to stabilize the resistance value, the width of the silicide layer needs to be sufficiently thick so that the fine line effect does not appear. However, if the silicide layer is thickened, current concentration cannot be prevented, and the resistance value per unit length increases, resulting in an increase in layout area.

  (3) In the method of lengthening the diffusion layer on which the silicide is formed, in order to obtain a necessary ballast resistance value, there is a problem that the diffusion layer has to be made extremely long and the layout area increases.

  (4) Regarding the method of dividing the diffusion layer on which the silicide is formed, for example, in the method described in Patent Document 9, the length of the resistance layer is set to 2 μm as in the above-described example of silicide blocking. If the width of the diffused diffusion layer is 0.5 μm and the arrangement pitch of the diffusion layers is 1 μm, the resistance of the silicided diffusion layer is about 10Ω / □, so the resistance value is only about 40Ω / μm. Don't be. For this reason, there is a problem that the layout area increases. Further, if the division width is further narrowed, there is a problem that the variation in resistance value increases due to the fine line effect. Furthermore, when the pitch is increased and the arrangement density of the diffusion layers is made rough, current distribution occurs, and the breakdown current becomes a much lower value than when the resistance is set to the same level by silicide blocking. Furthermore, if the number of contacts is too small, the current is excessively concentrated per contact, resulting in a low breakdown current. For this reason, there is a limit to increasing the arrangement pitch.

  Further, even in the technique of providing a current separation slit in the drain region described in Patent Document 10, since this current separation slit is not provided for the formation of the ballast resistor, when trying to obtain a necessary ballast resistor, contact is made. There is a problem that the distance between the gate electrode and the gate electrode becomes long, and the layout area increases.

  (5) The method of adding a resistance by wiring, contact, via or the like has a problem that the variation in resistance value is large. Recently, as the design rules of products have become finer, contacts and vias have become finer. However, in the case of fine contacts, there is a problem that variation in individual contact resistance becomes extremely large due to manufacturing variations. is there. For this reason, in an electrostatic protection element that does not particularly use a ballast resistor by a method such as silicide blocking and a small transistor of an internal circuit, there are contacts having a lower resistance value than other contacts among a large number of contacts. The current concentrates there, and the contact itself is destroyed by the overcurrent, or the overcurrent flows to the PN junction near the gate electrode of the MOS transistor arranged in the vicinity of the contact and is destroyed.

  Even when a back-end ballast as described in Patent Document 11 is provided, the resistance value in the lateral direction of the transistor and the value of the ballast resistance value cannot be too far apart. There is a problem that the degree of freedom of value setting is small. In addition, since the resistance value of polysilicon wiring, contacts, vias, etc. used in the resistance element is much smaller than the resistance value obtained by the silicide blocking region, a resistance value comparable to the resistance value obtained by the silicide blocking method is obtained. For this purpose, it is necessary to devise such as increasing the distance of the wiring. This complicates the wiring structure and makes it extremely difficult to design. Furthermore, with regard to contact resistance and via resistance, the miniaturization of the LSI process has progressed, and the contact diameter has also become finer, which makes it possible to use the back-end ballast technique. On the other hand, since the variation of the resistance value is large, it is necessary to take a sufficient margin in the element design.

  For example, in Patent Document 11, this back-end ballast is effectively used because the circuit configuration is such that a potential is applied to the gate of the next finger using the source resistance of the first triggering finger. . According to this circuit configuration, the snapback voltage (trigger voltage) Vt1 ′ of the finger snapping back after the second can be made extremely small compared to the snapback voltage Vt1 of the finger snapping back to the first. It becomes. Therefore, since the required resistance value may be small, the back end ballast can be used effectively. The disadvantage of this method is that Vt1 is extremely high, and it is difficult to avoid damage to the oxide film on the finger that first enters the snapback in the MOS transistor using an extremely thin gate oxide film. There are many things that must be done and the design margin is narrow.

  As described above, there are various methods for forming the ballast resistor, but each has a problem. To summarize the above-mentioned problems, when a ballast resistance value of a required size is formed, the layout area becomes large, the current flows in the width direction, and the current concentrates on a specific finger or a part thereof. In addition, the finger is destroyed, and the resistance value varies and the protection performance becomes unstable.

  The present invention has been made in view of such problems, and an object of the present invention is to provide an electrostatic discharge protection element that has a small layout area, can suppress current concentration, and has little variation in resistance value.

An electrostatic discharge protection element according to the present invention includes a substrate having a first conductivity type region formed on at least a part of a surface thereof, and a first second conductivity type formed in the first conductivity type region and receiving a surge current. A region, and a second second conductivity type region that is formed at a position spaced apart from the first second conductivity type region in the first direction in the first conductivity type region and to which a reference potential is applied. The first second conductivity type region is opposed to the second second conductivity type region, and has one end region in which silicide is formed on the surface or no silicide is formed on the surface; A plurality of conductive regions that are arranged along a second direction orthogonal to the direction of the electrodes and that receive the surge current and that are each connected to the end region and have no silicide layer formed on the surface, and between the conductive regions and arranged insulated region, the plurality of conductive regions Across fine said insulating region opposite to the first end region, and the other end region silicide layer formed on the surface, and having a.

  In the present invention, a parasitic bipolar ESD protection element is formed by the first second conductivity type region, the first conductivity type region, and the second second conductivity type region. Then, by providing an insulating region between the plurality of conductive regions, current can be prevented from being concentrated on a specific portion. Further, by not forming a silicide layer on the surface of the conductive region, the resistance value of the conductive region can be increased, and the layout area can be reduced accordingly.

Further, the and second second conductivity type region is provided with a plurality, one of the first second-conductivity-type region is disposed between two of said second second conductivity type region, The one end region may be formed at both ends of the one first second conductivity type region in the first direction. Thus, in the two parasitic bipolar, can share a single first second conductivity type region, it is possible to reduce the overall layout area.

Alternatively, the provided second second conductivity type region is provided with a plurality of, two of the first second-conductivity-type region is disposed between two of said second second conductivity type region, the conductive regions of the two first second-conductivity-type region may be arranged alternately along the second direction. Thereby, the entire layout area can be reduced.

  Further, the resistor may be connected to the first second conductivity type region and input with the surge current, and the resistor may be formed of polysilicon. Thereby, the ballast resistance value can be further increased and the layout area can be reduced.

Another electrostatic discharge protection element according to the present invention includes a substrate having a first conductivity type region formed on at least a part of a surface thereof, and a first second element formed in the first conductivity type region and receiving a surge current. A conductive type region and a second second conductive type region formed in a position spaced apart from the first second conductive type region in the first direction in the first conductive type region and to which a reference potential is applied; The first second conductivity type region has a first end region facing the second second conductivity type region and a second direction orthogonal to the first direction. And a plurality of first conductive regions connected to the end region, and a first insulating region disposed between the conductive regions, and the second second conductivity type region of the silicide layer is formed on the surface, to face the first second conductivity type region A second end region, the silicide layer is formed on the surface, a second conductive which each of the plurality is connected to the end region with the second of said reference potential are arranged along the direction is applied A region and an STI region disposed between the conductive regions, and the first conductive region and the second conductive region are shifted by a half pitch in the second direction. It is characterized by that.

Still another electrostatic discharge protection element according to the present invention includes a substrate having a first conductivity type region formed on at least a part of a surface thereof, and a first first electrode formed in the first conductivity type region and receiving a surge current. has a second conductivity type region, and two second second conductivity type region in which the reference potential is formed at a position sandwiching the first second conductive type region in the first conductivity type region is applied, the The first second conductivity type region includes a region having a silicide layer formed on a surface thereof, and a first heading from one second second conductivity type region to the other second second conductivity type region. A plurality of contacts that are arranged along a second direction orthogonal to the direction of the input and to which the surge current is input, and both ends of the contacts in the first direction that are arranged between the contacts are thicker than the center portion. A plurality of conductive regions on which no silicide layer is formed. And wherein the Rukoto.

  As described above in detail, according to the present invention, by providing an insulating region between a plurality of conductive regions, it is possible to prevent current from being concentrated on a specific portion, and silicide is formed on the surface of the conductive region. By not forming the layer, the resistance value of the conductive region can be increased, and the layout area of the electrostatic discharge protection element can be reduced.

Hereinafter, embodiments of the present invention will be specifically described with reference to the accompanying drawings. First, a first embodiment of the present invention will be described. FIG. 1 is a plan view showing an ESD protection element according to this embodiment. As shown in FIG. 1, in the ESD protection element 1 according to the present embodiment, a P-type substrate 2 made of P-type silicon is provided. A P well (not shown) is formed on the surface of the P type substrate 2. On the P-type substrate 2, a plurality of gate electrodes 3 extending in one direction (hereinafter referred to as a lateral direction) are provided in parallel to each other. In FIG. 1, only two gate electrodes 3 are shown, but the number of gate electrodes 3 is not limited to two. A region immediately below the gate electrode 3 on the surface of the P-type substrate 2 is a channel region (not shown), and a source region 5 and a drain region 6 are formed so as to sandwich the channel region. Source region 5 and drain region 6 are N ⁺ diffusion regions. A MOSFET is formed by the gate electrode 3, the channel region, the source region 5 and the drain region 6. The source region 5 and the drain region 6 are common to other MOSFETs adjacent to this MOSFET in a direction orthogonal to the horizontal direction (hereinafter referred to as the vertical direction). Accordingly, only one of the source region 5 and the drain region 6 is formed between the gate electrodes 3.

  On the surface of the source region 5, a plurality of contacts 7 are formed in a row in the lateral direction. The surface of the drain region 6 is divided into a plurality of regions described below. That is, both end portions in the vertical direction in the drain region 6 are channel proximity regions 11 as two end regions in contact with the channel region. The width of the channel proximity region 11, that is, the length in the vertical direction is, for example, 0.5 μm. The central portion in the vertical direction of the drain region 6 is a contact formation region 12 in which a plurality of contacts 7 are formed. The contacts 7 are arranged in a row in the horizontal direction, and the contact formation region 12 has a rectangular shape that is long in the horizontal direction. Further, a ballast resistor region 13 is formed between the channel proximity region 11 and the contact formation region 12. Thereby, on the surface of the drain region 6, the channel proximity region 11, the ballast resistance region 13, the contact formation region 12, the ballast resistance region 13, and the channel proximity region 11 are arranged in this order along the vertical direction.

  The ballast resistor region 13 is further divided into a conductive region 14 and an STI (Shallow Trench Isolation) region 15, and the conductive regions 14 and the STI regions 15 are alternately arranged in the lateral direction. ing. That is, in the drain region 6, no diffusion layer is provided in the STI region 15, and a region other than the STI region 15 forms a lattice-like diffusion layer. Each conductive region 14 corresponds to each finger.

  Further, in the conductive region 14, a silicide blocking region 17 is set except for both ends in the vertical direction. A silicide layer (not shown) is formed in a region other than the STI region 15 and the silicide blocking region 17 on the surface of the drain region 6. Further, a silicide layer (not shown) is formed on the entire surface of the source region 5. A region other than the source region 5, the channel region, and the drain region 6 on the surface of the P-type substrate 2 is an STI region 18.

Furthermore, the contact 7 formed in the drain region 6 is connected to an input pad (not shown). The contact 7 formed in the source region 5 is connected to a ground electrode (not shown). Further, a guard ring (not shown) made of a P ⁺ diffusion region and connected to the ground electrode is formed on the surface of the P-type substrate 2 so as to surround the ESD protection element 1.

  Next, the operation of the ESD protection element 1 according to this embodiment configured as described above will be described. When a surge current due to electrostatic discharge is input to the input pad, the surge current flows into the drain region 6 via the contact 7 and the drain voltage increases. When the drain voltage becomes equal to or higher than the voltage Vt 0 shown in FIG. 11, avalanche breakdown starts at the PN junction between the drain region 6 and the channel region, and a substrate current flows through the P-type substrate 2. At this time, a parasitic bipolar is formed in which the source region 5 of each finger serves as an emitter, the P-type substrate 2 serves as a base, and the drain region 6 serves as a collector. Due to the substrate current flowing in the P-type substrate 2, a potential difference is generated in the P-type substrate 2, and the potential near the bottom surface of the source region 5 in the P-type substrate 2 rises with respect to the guard ring. When the voltage applied to the input pad reaches the snapback start voltage (voltage Vt1 shown in FIG. 11), the PN junction between the source region 5 and the channel region 4 is forward-biased, and the aforementioned parasitic bipolar transistor is turned on. It becomes a low resistance state. As a result, a larger current flows. Thereby, the surge current applied to the input pad is released to the ground electrode.

  Next, the effect of this embodiment will be described. In the present embodiment, since the STI region 15 is provided in the ballast resistor region 13 of the drain region 6, it is possible to suppress the substrate current from flowing in the lateral direction, and to prevent the current from being concentrated on one finger, Ballast resistance can be imparted. Further, in the drain region 6, since the silicide blocking region 17 is provided in the conductive region 14 between the contact formation region 13 and the channel proximity region 11, no silicide layer is formed in this region, and a ballast resistance is further given. can do. That is, a ballast resistor having a sufficiently large and small variation can be formed by the synergistic effect of the STI region 15 and the silicide blocking region 17. As a result, the length of the drain region 6 in the vertical direction can be shortened, and the layout area can be reduced.

Hereinafter, the effects of the present embodiment will be specifically described in comparison with conventional ESD protection. Normally, the silicide blocking region is set as wide as the layout allows, but in reality, the length in the vertical direction is often about 2 μm. Therefore, as an object of comparison, a description will be given of a layout in which the drain resistance value of the NMOS transistor having a silicide blocking region width of 2 μm is substantially the same. In the present embodiment, a silicide blocking region (N ⁺ diffusion layer) is used for the ballast resistor because an appropriate resistance value can be obtained and the resistance value hardly varies. However, the layer is not limited to the silicide blocking region, and may be a layer having a similar resistance value and having a small variation.

  In this embodiment, the ballast resistor region 13 is divided in the horizontal direction at intervals of 1 μm, and the conductive regions 14 and the STI regions 15 are arranged at intervals of 1 μm. That is, the width of the silicide blocking region 17 is 1 μm. Thereby, the resistance value viewed from the channel region becomes the same value as that of the conventional ESD protection element in which the length of the drain region is twice that of the present embodiment. In other words, the length of the resistor region can be reduced by dividing the shape of the resistor region and the lateral width thereof is reduced, so that the transistor pitch can be reduced and the layout area can be saved. Although the length in the vertical direction of the drain region can be reduced to 50% of the conventional one, the other areas of the source region and the like are equivalent, and as a result, the layout area is about 70% of the conventional one.

In the present embodiment, the width of the channel proximity region 11 is made the shortest within the range of the design rule so as to minimize the current flow in the lateral direction. As described above, this value is about 0.5 μm, for example. This value is sufficiently longer than the width at which the thin line effect appears as described in Patent Document 8 described above. The resistance value of the region where the current spreads in the lateral direction (that is, the resistance value of the silicided N ⁺ diffusion layer) is usually about 10 to 20Ω / □. The resistance value of one striped ballast resistor is about 100 to 200Ω, and the dynamic resistance value after snapback of the silicided MOS transistor is usually about 50 to 200Ω depending on the gate length. As can be seen from the comparison, the current spreads almost uniformly in the width direction of the gate and flows. In other words, a sufficiently high resistance value can be realized by one ballast resistor, and as described in the section of the prior art, when the shape of the silicided polysilicon wiring and the silicided diffusion layer is devised. It can be seen that there is no problem of uneven current.

  Comparing the present embodiment with the conventional example, the current density of the ESD protection element in the present embodiment is about twice that of the conventional example, but the overall heat generation is the same. There is no difference compared to. Although the current density is twice that of the conventional example, this resistance element is formed on a silicon substrate and has a very good thermal conductivity, so that the temperature rises locally and melts. There is nothing. Further, since a sufficient number of contacts can be arranged, there is no fear that the breakdown current due to the shortage of contacts is reduced.

  Also, from the viewpoint of heat conduction, the length of the resistance is shortened, so the heat generated at the drain end and the striped ballast resistor portion is more heat capacity via the drain contact than in the conventional example. It is easy to diffuse into a large wiring area. For this reason, it becomes difficult to be destroyed as compared with the conventional protection element, and the destruction current becomes high.

Further, since the area of the N ⁺ diffusion layer in the drain region is reduced, there is an advantage that parasitic capacitance can be reduced. Since the substrate resistance value depends on the arrangement of the guard ring and the protective element, it cannot be generally stated. However, when the substrate resistance is compared with the conventional one, the STI region 15 is formed in the drain region 6, and the STI region Since the resistance value of the P well in the region immediately below 15 is higher than the resistance value of the P well in the region immediately below the N ⁺ diffusion layer forming the drain region, the substrate resistance can be effectively increased, and the voltage Vt1 Can be lowered. Therefore, there is a possibility that the resistance value required for snapping back all the fingers can be lowered. When the same resistance value is set, there is an advantage that the snapback operation is more stable.

  In the above description, the width of the conductive region 14 and the STI region 15 is 1 μm and the arrangement period is 2 μm. However, the present embodiment is not limited to this, and depending on the required ballast resistance value, these shapes and periods Can be optimized. In other words, when it is desired to set the resistance value high, the resistance layer width may be narrowed and the pitch may be widened.

  In addition, since current tends to concentrate at the lateral end of the drain region 6, the silicide blocking layer is also provided at the lateral end in the normal silicide blocking structure. Similarly, in this embodiment, the same effect can be achieved by separating the conductive region 14 from the lateral end.

Further, in this embodiment, the silicide-blocked drain N ⁺ diffusion layer is used as the ballast resistor. However, the present invention is not limited to this, and in the case where the dynamic resistance is large, there is little problem. A well resistor or an LDD resistor may be used, and a similar layout area reduction effect is obtained.

  Furthermore, in this embodiment, the STI region 15 is used to partition the conductive region 14, but the present invention is not limited to this, and ion implantation of high-concentration impurities for forming a diffusion layer is not performed. Alternatively, a low concentration impurity layer may be used. In this structure, since the absorption source that absorbs heat can be installed close to the resistance layer, the breakdown current may be higher. For example, in the SOI process, as described in other embodiments to be described later, an element isolation region is formed, that is, the body is removed by etching to form a striped ballast resistor. Method is desirable.

  Next, a second embodiment of the present invention will be described. FIG. 2 is a plan view showing the ESD protection element according to this embodiment. As shown in FIG. 2, in the present embodiment, the silicide blocking region 17 extends not only to the conductive region 14 but also to the channel proximity region 11 and the gate electrode 3. It should be noted that the gate electrode 3 may be sandwiched to extend to a part of the source region 5. Thereby, the ballast resistance value can be further increased. Other configurations, operations, and effects of the present embodiment are the same as those of the first embodiment.

  Next, a third embodiment of the present invention will be described. FIG. 3 is a plan view showing the ESD protection element according to this embodiment. As shown in FIG. 3, in this embodiment, the drain regions 21 of the MOSFETs adjacent to each other are not made common but are separated from each other. The drain region 21 has a comb shape, and the drain regions 21 of adjacent MOSFETs are nested in each other. That is, the comb portions 21a of the drain regions 21 of adjacent MOSFETs are alternately arranged in the horizontal direction. An STI region 22 is formed between the drain regions 21. Other configurations and operations in the present embodiment are the same as those in the first embodiment.

  In the present embodiment, the layout area can be further reduced compared to the first embodiment described above. In this embodiment, the number of contacts is reduced to about half compared to the first embodiment. However, in a normal MOS type protection element, the number of contacts is not so small that the breakdown current is determined. There is no problem because there is no. However, if it is necessary to increase the number of contacts, for example, when the pitch must be increased in order to increase the resistance value, two or more contacts may be arranged in each comb portion of the drain region 21. The ESD protection element according to the present embodiment can be reduced in length in the vertical direction by about 3 μm compared to the conventional example and by about 0.5 μm compared with the first embodiment. For this reason, the layout area can be reduced to about 60% of the conventional example. The effects of the present embodiment other than those described above are the same as those of the first embodiment described above.

  Next, a fourth embodiment of the present invention will be described. FIG. 4 is a plan view showing the ESD protection element according to this embodiment. As shown in FIG. 4, the present embodiment is an example in which the second embodiment and the third embodiment described above are combined. That is, in this embodiment, in the ESD protection element according to the third embodiment, the silicide blocking region is set so as to cover the gate electrode. Configurations and operations other than those described above in the present embodiment are the same as those in the third embodiment described above.

  In the present embodiment, as is apparent from the calculation of the resistance value of each resistance element, the current flows uniformly in the transistor. Further, since the silicide blocking region reaches the gate electrode, it is possible to further suppress the current from flowing laterally in the channel proximity region of the drain region. Thereby, the breakdown current can be further improved. The effects of the present embodiment other than those described above are the same as those of the third embodiment described above.

  Next, a fifth embodiment of the present invention will be described. FIG. 5 is a plan view showing the ESD protection element according to this embodiment. As shown in FIG. 5, in this embodiment, in the ESD protection element according to the third embodiment described above, a resistor 24 made of polysilicon is connected to each end of the comb portion 21 a of the drain region 21. Yes. That is, a wiring 23 is connected to the contact 7 formed at each end of the comb portion 21 a of the drain region 21, and one end of a resistor 24 made of polysilicon formed on the P-type substrate 2 is connected to the wiring 23. Is connected. A contact 25 is formed at the other end of the resistor 24, and this contact 25 is connected to an input pad (not shown). The resistance value of the resistor 24 is about a fraction of the resistance value of the silicide blocking region. For example, the resistance value of the silicide blocking region is 150Ω, and the resistance value of the resistor 24 is 60Ω. The total width of the resistors 24 is set such that the resistance value increases at a current value close to the breakdown current of the ESD protection element. Other configurations in the present embodiment are the same as those in the third embodiment described above.

  FIG. 6 is a graph showing the operating characteristics of the ESD protection element of this embodiment, with the voltage applied to the ESD protection element on the horizontal axis and the current flowing through the ESD protection element on the vertical axis. As shown in FIG. 6, unlike the resistance in the silicide block region, the resistor 24 made of polysilicon does not diffuse most of the generated heat into the P-type substrate 2 and the like, and the temperature of the resistor 24 increases. used. For this reason, when a current flows through the ESD protection element, the temperature of the resistor 24 rises, and the resistance value increases by about three times at a current value close to the breakdown current. For this reason, in the high current region in FIG. 6, the voltage value varies depending on the presence or absence of the resistor 24, and the voltage value when the same current flows is higher when the resistor 24 is present than when the resistor 24 is not present. Become. As a result, the current limiting effect is increased and the breakdown current is improved. The effects of the present embodiment other than those described above are the same as those of the third embodiment described above.

  Next, a sixth embodiment of the present invention will be described. FIG. 7 is a plan view showing the ESD protection element according to this embodiment. As shown in FIG. 7, in the present embodiment, the source region 26 has a comb shape, and the comb portion 21a of the drain region 21 and the comb portion 26a of the source region 26 are compared with the third embodiment described above. They differ from each other in that they are arranged so as to be shifted by a half pitch in the lateral direction, and that a silicide blocking region is not provided in the drain region 21 and a silicide layer (not shown) is formed on the entire surface of the drain region 21. Yes. Other configurations in the present embodiment are the same as those in the third embodiment described above. That is, the drain regions of the MOSFETs adjacent to each other have a gear structure, and the source regions of the MOSFETs adjacent to each other also have a gear structure.

  In the present embodiment, the source region 26 has a comb shape, and the comb portion 21a of the drain region 21 and the comb portion 26a of the source region 26 are arranged so as to be shifted by a half pitch in the lateral direction. The effective path of the current flowing from the divided diffusion layer, that is, the comb portion 21 a to the comb portion 26 a of the source region 26 through the channel region that is immediately below the gate electrode 3 becomes long. Thereby, ballast resistance can be improved and a layout area can be reduced. In addition, since the current flowing through the drain region and the channel region is divided into the comb portions 26a of the two source regions, current concentration can be more effectively prevented. Furthermore, since the silicide blocking region is not provided, the process for manufacturing the ESD protection element can be simplified. The effects of the present embodiment other than those described above are the same as those of the third embodiment described above. In each comb portion 21a of the drain region 21 and / or each comb portion 26a of the source region 26, a plurality of contacts may be formed instead of one.

  Next, a seventh embodiment of the present invention will be described. FIG. 8 is a plan view showing the ESD protection element according to this embodiment. As shown in FIG. 8, the configuration of the drain region 31 in this embodiment is different from that in the first embodiment described above. In other words, in the present embodiment, a plurality of contacts 7 are arranged in a line along the horizontal direction at the central portion in the vertical direction of the drain region 31. A silicide blocking region 32 is set between the contacts 7. In other words, in the drain region 31, the contacts 7 and the silicide blocking regions 32 are alternately arranged along the horizontal direction. No silicide layer is formed in the silicide blocking region 32, and a silicide layer (not shown) is formed on the entire surface of the drain region 31 other than the silicide blocking region 32 and the surface of the source region 5. . In the present embodiment, the STI region is not formed.

  The silicide blocking region 32 extends in the vertical direction, and both end edges in the vertical direction do not reach the channel region. Further, both end portions in the vertical direction of the silicide blocking region 32 are thicker than the central portion. Thus, the silicide blocking region 32 is disposed so as to partially surround the contact 7. Other configurations and operations in the present embodiment are the same as those in the first embodiment.

  In the present embodiment, the drain region is separated not by the STI region but by a silicide-blocked diffusion layer. In particular, in a semiconductor integrated circuit using an SOI substrate, since there is no substrate on which generated heat is dissipated, the problem of being easily destroyed thermally is particularly significant. For this reason, in order to alleviate this, the ESD protection characteristics can be improved by leaving a diffusion layer capable of absorbing heat in the adjacent region.

  The configuration of the present embodiment is similar to the configuration of the protection element shown in FIG. 13 of Patent Document 7 described above, but the feature of the present embodiment is that a silicide block region is arranged so as to surround the contact. It is that you are. That is, since the contact resistance is about 10Ω per one and the resistance of the silicided diffusion layer is about 10Ω, the resistance of the contact itself can also be used as the ballast resistance. Accordingly, the contacts are arranged at intervals so that the breakdown current of the contacts is reduced to a level that does not fall below the breakdown current of the protective element. In the technique described in Patent Document 7, since the lateral direction of the region where the contact is installed is connected by a silicided diffusion layer, current flows laterally in this region, and the resistance of the contact itself is reduced. It cannot be used as a ballast resistor.

It is a top view which shows the ESD protection element which concerns on the 1st Embodiment of this invention. It is a top view which shows the ESD protection element which concerns on the 2nd Embodiment of this invention. It is a top view which shows the ESD protection element which concerns on the 3rd Embodiment of this invention. It is a top view which shows the ESD protection element which concerns on the 4th Embodiment of this invention. It is a top view which shows the ESD protection element which concerns on the 5th Embodiment of this invention. It is a graph which shows the operating characteristic of the ESD protection element of this embodiment, taking the voltage applied to an ESD protection element on a horizontal axis, and taking the electric current which flows into this ESD protection element on a vertical axis | shaft. It is a top view which shows the ESD protection element which concerns on the 6th Embodiment of this invention. It is a top view which shows the ESD protection element which concerns on the 7th Embodiment of this invention. It is a top view which shows the input protection element using the snapback phenomenon of NMOSFET which is the conventional MOS type protection element. It is a figure which shows the cross section by the A-A 'line shown in FIG. 9, and its equivalent circuit. It is a graph showing the operating characteristics of this MOS type protection element, with the voltage applied to the protection element on the horizontal axis and the current flowing through the protection element on the vertical axis. It is a top view which shows the ESD protection element described in patent document 8

Explanation of symbols

DESCRIPTION OF SYMBOLS 1; ESD protection element 2; P-type substrate 3; Gate electrode 5; Source region 6; Drain region 7; Contact 11; Channel proximity region 12; Contact formation region 13: Ballast resistance region 14; Conductive region 15; Silicide blocking region 18; STI region 21; Drain region 21a; Comb 22; STI region 23; Wiring 24; Resistor 25; Contact 26; Source region 26a; Comb 31; Drain region 32; Silicide blocking region 101; 102; P-type substrate 103; Gate electrode 104; Channel region 105; Source region 106; Drain region 107; Contact 108; Guard ring 109; Ground wiring 110; Input pad 111;
112, 113; line 115; MOSFET
116; drain region 117; silicide layer 118; opening 119; gate electrode 120;

Claims (16)

A substrate in which a first conductivity type region is formed at least on a part of the surface; a first second conductivity type region formed in the first conductivity type region to which a surge current is input; and And a second second conductivity type region to which a reference potential is applied at a position separated from the first second conductivity type region in the first direction, and the first second conductivity type region Is opposed to the second second conductivity type region and has one end region in which silicide is formed on the surface or no silicide is formed on the surface, and in a second direction orthogonal to the first direction. A plurality of conductive regions that are arranged along with the surge current and that are each connected to the end region and not formed with a silicide layer on the surface; an insulating region disposed between the conductive regions; The one end across the conductive region and the insulating region And regions facing, electrostatic discharge protection device and having the other end regions silicide layer is formed on the surface. The first second conductivity type region includes a contact formation region connected to the other end portion of the conductive region and having a contact formed on a surface thereof to which the surge current is input. The electrostatic discharge protection element according to 1. The second second-conductivity-type region is provided with a plurality, two said and second one of said first second-conductivity-type region between the second conductive type region is disposed, the 1 one of the electrostatic discharge protection device according to claim 1 or 2, characterized in that the said one end region to the opposite end portions in the first direction of the first second conductivity type region is formed. The electrostatic discharge protection element according to claim 3, wherein the plurality of conductive regions are commonly connected to the contact formation region. Wherein and second second conductivity type region is provided with a plurality of, two of the first second conductive type region in between two of said second second-conductivity-type region is disposed, the 2 one of the conductive region of the first second conductivity type region, the electrostatic discharge protection device according to claim 1 or 2, characterized in that are arranged alternately along the second direction. 6. The electrostatic discharge protection element according to claim 5, wherein a plurality of the contact formation regions are provided, and the plurality of conductive regions are connected to one of the contact formation regions. The electrostatic discharge protection element according to claim 1, wherein a silicide layer is not formed on a surface of the one end region. 8. The electrostatic discharge protection element according to claim 7, wherein a silicide layer is not formed at an end of the second second conductivity type region facing the first second conductivity type region. The electrostatic discharge protection element according to claim 1, further comprising a resistor connected to the first second conductivity type region and to which the surge current is input. The electrostatic discharge protection element according to claim 9, wherein the resistor is made of polysilicon. The electrostatic discharge protection element according to claim 1, wherein the insulating region is an STI region. A substrate in which a first conductivity type region is formed at least on a part of the surface; a first second conductivity type region formed in the first conductivity type region to which a surge current is input; and And a second second conductivity type region to which a reference potential is applied at a position separated from the first second conductivity type region in the first direction, and the first second conductivity type region Are arranged along a first end region facing the second second conductivity type region and a second direction orthogonal to the first direction, and the surge current is input and each is A plurality of first conductive regions connected to the end region, and a first insulating region disposed between the conductive regions, wherein the second second conductivity type region has a silicide layer on a surface thereof And a second end region facing the first second conductivity type region, and a silicide layer on the surface A plurality of second conductive regions formed and arranged along the second direction, to which the reference potential is applied and each connected to the end region, and an STI region disposed between the conductive regions An electrostatic discharge protection element, wherein the first conductive region and the second conductive region are shifted by a half pitch in the second direction. Said first and second second-conductivity-type region is provided with a plurality s respectively, in the first direction, a set of two of said first second conductivity type region, the two said second and sets of second conductivity type regions are alternately arranged in said two first conductive region of the second conductivity type region are alternately arranged in the second direction, the two conductive region of the second conductivity type region, the electrostatic discharge protection device according to claim 12, characterized in that are arranged alternately along the second direction. 13. The silicide layer according to claim 12, wherein a silicide layer is formed on a surface of the first end region and a surface of the plurality of first conductive regions in the first second conductivity type region. 14. The electrostatic discharge protection element according to 13. The electrostatic discharge protection element according to claim 14, wherein the first insulating region is an STI region. A substrate in which a first conductivity type region is formed at least on a part of the surface; a first second conductivity type region formed in the first conductivity type region to which a surge current is input; and wherein two second of the second conductive type region in which the first reference potential are formed at positions sandwiching the second conductivity type region is applied, having a first second conductivity type region, the surface And a region in which a silicide layer is formed on the first and second second conductivity type regions and a second direction orthogonal to the first direction from the second second conductivity type region to the other second second conductivity type region. A plurality of contacts to which the surge current is input, and a plurality of conductive regions disposed between the contacts and having both end portions in the first direction thicker than the central portion and no silicide layer formed on the surface. An electrostatic discharge protection element comprising:

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