JP4429638B2 - Image forming apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an image forming apparatus that includes a plurality of devices that perform image processing on input data and forms an image based on the data subjected to image processing.
[0002]
[Prior art]
In recent years, with the spread of personal computers and the progress of networking, there are increasing demands for higher speed and higher image quality of image forming apparatuses that form images on recording media. In recent years, with the spread of digital cameras and the like, colorization has been promoted, and the demands on the quality of the color images formed have become increasingly severe.
[0003]
Even in an image forming apparatus using an electrophotographic method such as a printer or a copying machine, it is necessary for control when image processing such as color conversion and gamma correction is applied to image data, and for toner image formation based on image processed image data. The load of the control system in the image forming apparatus is increasing more and more, such as control for adjusting image forming conditions such as charging voltage, exposure light quantity, and developing bias voltage. For this reason, there is an urgent need to improve the processing capability of a semiconductor device used for a control system such as a processor including a CPU, RAM, ROM, and various ASICs (Application Specific Integrated Circuits).
[0004]
In recent years, the number of functions that can be incorporated into one device is increasing due to the progress of process technology for manufacturing semiconductor devices. However, since the number of functions required for the control system of the image forming apparatus has increased, the number of devices used in the entire image forming apparatus has not decreased.
[0005]
Devices used in the control system of the image forming apparatus generally operate by being connected to a CPU control bus. (1) Necessity of reducing the load on the CPU control bus, (2) Different timing systems (3) There is a case where a device is connected to a dedicated bus (local bus) separated from the CPU control bus via the ASIC because of the necessity of matching (3) necessity of avoiding the influence when mounted on a separate board. It is increasing.
[0006]
For example, a CPU of a main control unit that performs various controls of the image forming apparatus, a ROM that stores a control program, a user information, a usage history, and the like, which are connected via a CPU bus under the control of the CPU, are stored as information. Of the non-volatile memory, etc., the non-volatile memory is connected via an ASIC with a built-in data memory to reduce the load on the CPU associated with the information update processing in the non-volatile memory and to suppress performance degradation (See Patent Document 1).
[0007]
Also, in an image forming apparatus that uses a bus such as Peripheral Component Interconnect (PCI) or Accelerated Graphic Port (AGP), PCI via a chipset has a low performance, so the NB and ASIC of the chipset are connected with a dedicated port for graphic display. There is one that uses a certain AGP to switch and control the image data exchanged between the CPU and the engine unit (see Patent Document 2).
[0008]
FIG. 1 is a diagram showing an example of a processor system that does not use a conventional local bus.
[0009]
As shown in FIG. 1, the CPU 1a-1 is directly connected to the ROM 1a-2, RAM 1a-3, CPU peripheral ASIC 1a-5, device A1a-7, and device B1a-8 via the CPU control bus 1a-4. Each of these input / output devices is configured to be directly controlled by the CPU 1a-1. Therefore, since the CPC 1a-1 operates in accordance with the processing operation of each input / output device, the processing efficiency decreases.
[0010]
FIG. 2 is a diagram illustrating an example of a processor system using a local bus.
[0011]
As shown in FIG. 2, a local bus 1b-6 to which the device A1b-7 and the device B1b-8 are connected is provided, and a peripheral ASIC 1b-5 is disposed between the local bus 1b-6 and the CPU 1b-1. .
[0012]
The device A1b-7 and the device B1b-8 are separated from the CPU control bus 1b-4 by the local bus 1b-6 generated by the peripheral ASIC 1b-5, and the load on the CPU 1b-1 is reduced.
[0013]
FIG. 3 is a diagram illustrating an example of the local bus generation circuit.
[0014]
The local bus generation circuit shown in FIG. 3 includes an address bus (ADDR10: 0) 101, a data bus (DATA7: 0) 113, a read signal input (RD-N) 102, and a system clock connected to the CPU 1b-1. XIN) 100 and a write signal input (WR-N) 114, an input / output cell (IOcell) 40, an internal circuit 50, an input / output cell (IOcell) 60, and a plurality of devices , Local bus address bus (LBA6: 0) 108, local bus data bus (LBDATA7: 0) 110, local bus read signal output (LBRD-N) 109, and local bus write signal output ( LBWR-N).
[0015]
The internal circuit 50 includes a decoder 51 that decodes a signal on the address bus (ADDR10: 0) 101, a chip select signal (cs-lbus, cs-xx, cs-nn) and a local bus that are decoded and output. Data that has three AND circuits to which signals from the data bus 110 are inputted and an OR circuit connected to the three AND circuits, and is selected to the data bus (DATA 7: 0) via the input / output cell 10 Output of the two-stage D-type FF circuit and the two-stage D-type FF circuit operated by the selector 52 that outputs the signal, the inverted read signal input (RD-N) 102 and the system clock (XIN) 100 The data input from the local bus data bus is output to the data bus (DATA 7: 0) 113. Output of the first delay circuit 53 for outputting the enable signal for the output, the D-type FF circuit operated by the inverted write signal input (WR-N) 114 and the system clock (XIN) 100, and the output of the D-type FF circuit A second delay circuit 54 having an OR circuit for outputting either the effective period or the inverted effective period of the write signal input (WR-N) 114, and the signal and decode on the address bus (ADDR10: 0) 101 The AND circuit 57 that operates in response to both the chip select signal (cs-lbus) output and outputs an address to the local bus address bus 108 via the input / output cell (IOcell) 60, and the chip select signal (Cs-lbus) 107 and the output signal of the second delay circuit 54, and the data bus (DAT 7: 0) 113 and an NAND circuit 56a that outputs an enable signal for data output from the local bus data bus (LBDATA 7: 0) 110, a chip select signal (cs-lbus) 107, and an inverted read signal input ( RD-N) 102 and both the NAND circuit 56b for outputting the local bus read signal 109, the chip select signal (cs-lbus) 107 and the inverted write signal input (WR-N) 114. And a NAND circuit 56c for outputting a write signal for the local bus.
[0016]
Here, the reason why the OR circuit is used for the second delay circuit 54 is to extend the effective period of the local bus enable signal (ldb-en) 118 to the effective period of the write signal (wr) 116.
[0017]
FIG. 4 is a timing chart showing the operation timing of the local bus generation circuit.
[0018]
In FIG. 4, the top stage is the system clock (XIN) 100, the second stage is the address bus (ADDR10: 0) 101, the third stage is the read signal input (RD-N) 102, The internal read signal (rd) 103 in the delay circuit 53, the system clock falling edge synchronization internal read signal (drd-n) 104, the system clock rising edge synchronization read signal (drd-p) 105, and the first delay circuit 53 CPU data bus enable signal (d-enl) 106 output from, internal chip select signal (cs-lbus) 107 input to selector 52, local bus address bus (LBA6: 0) 108, local bus Read signal output (LBRD-N) 109, data bus for local bus (LBDATA7: 0) 110, data (od-lbus 7: 0) 111 input to the selector 52, data (d-o 7: 0) 112 output from the selector 52, CPU data bus (DATA 7: 0) 113, write signal input (WR- N) 114, input data (d-i7: 0) 115 from the CPU data bus, internal write signal (wr) 116 in the second delay circuit 54, system clock rising edge synchronous internal write signal (dwr-p) 117 , A signal (lbd-en) 118 output from the second delay circuit 54 and an enable signal (lbd-enl) 119 for the local bus data bus (LBDATA7: 0).
[0019]
When the CPU 1b-1 shown in FIG. 2 performs a read operation on the devices 1b-7 and 1b-8 connected to the local bus 1b-6, the address is designated by the address bus (ADDR10: 0) 101. The read signal (RD-N) 102 is asserted. Then, the address bus for local bus (LBA6: 0) 108 and the read signal for local bus (LBRD-N) are asserted 120 according to the designation of the target address, and the devices 1b-7, 1b- connected to the local bus are asserted 120. 8 outputs data to the local bus data bus (LBDATA 7: 0) 110. This data is input 121 to the selector 52 as output data (od-lbus7: 0) 111 via an input / output cell (IOcell) 60, and the selector 52 receives input data (d-o7: 0) to the CPU data bus. ) 112, and the output data (d-o7: 0) 112 is taken in as data (DATA7: 0) 113 via the input / output cell (IOcell) 40, and the CPU 1b-1 Get.
[0020]
Next, when the CPU performs a write operation on a device connected to the local bus, an address is designated by the address bus (ADDR10: 0) 101, and then a write signal (WR-N) 114 is asserted. Then, the local bus address bus (LBA6: 0) 108 and the local bus write signal output (LBWR-N) are asserted according to the designation of the target address. The device connected to the local bus has output data (DATA 7: 0) 113 of the CPU data bus, that is, output data (d-i 7: 0) 115 is an enable signal (lbd) of the data bus for local bus (LBDATA 7: 0). -Enl) When activated by 119, data is taken in via an input / output cell (IOcell) 60.
[0021]
On the other hand, a variable delay circuit that includes a plurality of delay circuits capable of delaying a data input signal and makes a data delay time variable by selecting one of the plurality of delay circuits with a selector is widely used. Although it is known, in that case there is a drawback that the delay time cannot be set with a resolution less than the delay time of the gate, so the disadvantage can be reduced by switching multiple paths having a delay time relative to the period of the clock signal. There is a technique that can obtain a variable delay time having a desired arbitrary resolution and high accuracy of delay time and resolution (see Patent Document 3).
[0022]
However, this technique does not consider a technique for avoiding a hazard that occurs due to a delay in data output from a device connected to a local bus, for example.
[0023]
FIG. 5 is a timing chart showing the operation timing of the local bus generation circuit when the CPU performs a read operation on a high-speed device on the local bus.
[0024]
The symbols shown in each stage of FIG. 5 are the same as those described in FIG. 4, and description thereof is omitted here.
[0025]
When an address is specified by the address bus (ADDR10: 0) 101 and the local bus read signal output (LBRD-N) 109 is asserted, the device A connected to the local bus is connected to the local bus data bus (LBDATA7). : 0), the data is output 124. At this time, since device A is a high-speed device, the delay time (tdd) until valid data is output to the local bus data bus (LBDATA 7: 0) 110 is small 125.
[0026]
For this reason, the CPU peripheral ASIC 1b-5 shown in FIG. 2 receives the local bus data bus (LBDATA7: LBDATA7 :) until the enable signal (d-enl) for outputting data to the CPU control bus 1b-4 is asserted 126. 0) 110 valid data can be output to the CPU control bus 1b-4.
[0027]
FIG. 6 is a timing chart showing the operation timing of the local bus generation circuit when the CPU performs a read operation on a low-speed device on the local bus.
[0028]
The symbols shown in each stage shown in FIG. 6 are the same as those described with reference to FIG. 4, and description thereof is omitted here.
[0029]
When an address is specified by the address bus (ADDR10: 0) 101 and the local bus read signal output (LBRD-N) 109 is asserted, the device A connected to the local bus is connected to the local bus data bus (LBDATA7). : 0) Output data to 110. At this time, since the device B is a low-speed device, the valid data is output to the local bus data bus (LBDATA7: 0) 110 after the local bus read signal output (LBRD-N) 109 is asserted. The delay time (tdd) is 127.
[0030]
Therefore, the CPU peripheral ASIC 1b-5 shown in FIG. 2 has the local bus data bus (LBDATA7 :) until the enable signal (d-enl) 106 for outputting data to the CPU control bus 1b-4 is asserted 128. 0) The valid data of 110 cannot be output to the CPU control bus 1b-4. Therefore, after outputting 129, which is internal data, for a moment, valid data of the local bus data bus (LBDATA7: 0) 110 is output to the CPU control bus 1b-4.
[0031]
As described above, when a low-speed device is connected to the local bus, the local bus data bus (LBDATA7) until the enable signal (d-enl) for outputting data to the CPU control bus 1b-4 is asserted 128. : 0) Since valid data cannot be output to 110, the output data of the CPU control bus 1b-4 changes in a short cycle.
[0032]
Depending on the delay time from when the local bus read signal output (LBRD-N) 109 of the device connected to the local bus 1b-6 is asserted until valid data is output to the local bus 1b-6, there is a hazard. The pulse of several nanoseconds, which is called, is generated, which may increase radiation noise, increase ground bounce, and cause malfunction of the device.
[0033]
[Patent Document 1]
JP 2002-337402 (paragraph number 0016 to paragraph number 0018, FIGS. 1 and 2)
[0034]
[Patent Document 2]
JP 2003-87443 (paragraph number 0010 to paragraph number 0037, FIGS. 1 and 2)
[0035]
[Patent Document 3]
JP-A-9-46197 (paragraph number 0002 to paragraph number 0036, FIGS. 1 to 7)
[0036]
[Problem to be Solved by the Invention]
In view of the above circumstances, the present invention avoids hazards that are likely to occur when a read operation is performed on a device connected to a local bus from a CPU provided in an image processing unit, and the CPU performs a stable control operation. An object of the present invention is to provide an image forming apparatus capable of forming a high-quality image.
[0037]
[Means for Solving the Problems]
An image forming apparatus of the present invention that achieves the above object has a plurality of devices that perform image processing on input data, and an image forming apparatus that forms an image based on the data subjected to the image processing.
The central processing unit that controls the plurality of devices, and the access request from the central processing unit to each of the plurality of devices is relayed to each device that has made the access request, and the read request of the access request And an integrated circuit including a timing adjustment unit that adjusts the timing for transferring data output from the device to which the read request is made to the central processing unit.
[0038]
As described above, since the timing adjustment unit that adjusts the timing of transferring the data to the central processing unit after the data is output from the device for which the read request is made, the data is output before the data is output to the device. Hazard caused by can be avoided.
[0039]
Here, it is preferable that the timing adjustment unit adjusts the timing based on a selection signal for selecting a device for which the access request has been made.
[0040]
As described above, since the processing speed of the selected device can be known from the selection signal for selecting the device, for example, the address, it is easy to adjust the timing.
[0041]
The timing adjustment unit preferably gives a predetermined delay to data according to the read request based on the selection signal.
[0042]
As described above, the timing adjustment is ensured by shifting the input data according to a selection signal for selecting a device, for example, an address, or selecting any one of a plurality of circuits whose delay times are known in advance.
[0043]
The timing adjustment unit may adjust the timing by issuing an enable signal in accordance with a timing at which data corresponding to the read request is output from the device that has made the read request.
[0044]
As described above, if the enable signal is output in accordance with the timing at which data corresponding to the read request is output, occurrence of a hazard can be reliably avoided.
[0045]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the image forming apparatus of the present invention will be described.
[0046]
FIG. 7 is a schematic configuration diagram of a copying machine showing an embodiment of the image forming apparatus of the present invention.
[0047]
The copying machine 1 shown in FIG. 7 reads an original and outputs an image signal, and A / D converts the image signal read by the image reading unit 3, performs image processing, and outputs image data. An image control unit 7, an image forming unit 4 that forms a fixed toner image on a recording medium based on image data that has been subjected to image processing by the image control unit 7, and automatic document transmission that sends a document to the image reading unit 3 And a mechanism 5.
[0048]
The image reading unit 3 includes a platen glass 6 on which a document is placed, a first traveling mirror 8 that faces the document surface across the platen glass 6 and bends an optical path of reflected light from the document, and a first traveling mirror 8. The second traveling mirror 9 that turns back the optical path from the first traveling mirror 9 and the CCD sensor 10 that receives and photoelectrically converts the original image formed by the imaging lens disposed on the optical path of the second traveling mirror 9 are provided.
[0049]
The image control unit 7 relays a plurality of devices, a central processing unit that controls the plurality of devices, and an access request from the central processing unit to each of the plurality of devices to each of the devices for which the access request has been made. For the read request of the access request, the peripheral device includes a peripheral ASIC that includes a timing adjustment unit that adjusts the timing at which the data output from the device for which the read request is made is transferred to the central processing unit. Under the control of the central processing unit, color separation processing, gamma correction, and the like are performed on the image data obtained by digitally converting the image signal photoelectrically converted by the CCD sensor 10, and the image signal is output by performing pulse width modulation.
[0050]
The image forming unit 4 is an optical writing device including a laser output device that emits laser light based on an image signal output from the image control unit 7 and a polygon mirror that converts the laser light into light that scans a predetermined range. Unit 14, photoconductor drum 11, charger 13 for charging photoconductor drum 11, and laser beam from optical writing unit 14 is applied to charged photoconductor drum 11. The electrostatic latent image formed in this way is developed with toner to form a toner image on the photosensitive drum 11, the transfer device 16 for transferring the toner image formed on the photosensitive drum 11 to the paper, and the paper The toner cleaner 12 that cleans the toner remaining on the photosensitive drum 11 after the transfer to the transfer unit 16 and the sheet that is sent to the transfer unit 16 via the sheet transport mechanism 23 is stored. A cassette 19 and a small-capacity paper cassette 17 of different sizes, a paper transport path 20 for transporting the paper on which the toner image has been transferred by the transfer device 16, and heating and pressurizing the paper on which the toner image has been transferred onto the paper A fixing device 21 for fixing the toner image and a paper discharge tray 18 for discharging the paper on which the toner image is fixed and the image is formed are provided.
[0051]
Here, the present embodiment has been described based on a copying machine. However, the present embodiment is not limited to the copying machine, and may be a printer or a facsimile. The image forming unit of the copying machine of the present embodiment adopts a direct transfer method, but it is not necessary to be limited to the direct transfer method, and even an indirect transfer method using an intermediate transfer member is further photosensitive. Even a tandem type having a plurality of body drums is applicable. The image forming apparatus according to the present embodiment is not limited to an electrophotographic image forming apparatus using toner, and may be applied to an image forming apparatus using ink.
[0052]
Next, the relationship between a central processing unit that is used in the image control unit 7 of this embodiment and controls image processing performed by the image processing unit, and a plurality of devices that perform image processing will be described.
[0053]
The connection form of the central processing unit, the control bus, the plurality of devices, the peripheral ASIC corresponding to the integrated circuit of the present invention, and the local bus, which are components of the image control unit 7 of the present embodiment, is as described in FIG. Since they are the same, description thereof will be omitted, and different peripheral ASIC 1b-5 and local bus 1b-6 will be described.
[0054]
FIG. 8 is a diagram illustrating a local bus generation circuit including a peripheral ASIC and a local bus according to the present embodiment.
[0055]
The local bus generation circuit shown in FIG. 8 includes an address bus (ADDR10: 0) 101, a data bus (DATA7: 0) 113, a read signal input (RD-N) 102, and a system clock (connected to the CPU 1b-1. XIN) 100 and a write signal input (WR-N) 114, an input / output cell (IOcell) 40, an internal circuit 50, an input / output cell (IOcell) 60, and a plurality of devices , Local bus address bus (LBA6: 0) 108, local bus data bus (LBDATA7: 0) 110, local bus read signal output (LBRD-N) 109, and local bus write signal output ( LBWR-N).
[0056]
The internal circuit 50 includes a decoder 51 that decodes a signal on the address bus (ADDR10: 0) 101, a chip select signal (cs-lbus, cs-xx, cs-nn) and a local bus that are decoded and output. Data that has three AND circuits to which signals from the data bus 110 are input and an OR circuit connected to the three AND circuits, and is selected to the data bus (DATA 7: 0) via the input / output cell 10 Output of the two-stage D-type FF circuit and the two-stage D-type FF circuit operated by the selector 52 that outputs the signal, the inverted read signal (RD-N) 102 and the system clock (XIN) 100. It has a NOT circuit and outputs data input from the local bus data bus to the data bus (DATA 7: 0) 113. Output and inversion of the first delay circuit 53 for outputting the enable signal, the D-type FF circuit operated by the inverted write signal input (WR-N) 114 and the system clock (XIN) 100, and the D-type FF circuit Second delay circuit 54 having an OR circuit for outputting any one of the write signal inputs (WR-N) 114, a signal on the address bus (ADDR10: 0) 101, and a chip select that is decoded and output An AND circuit 57 that operates by both signals (cs-lbus) and outputs an address to the local bus address bus 108 via an input / output cell (IOcell) 60, a chip select signal (cs-lbus), and a second signal It operates with both output signals of the delay circuit 54 of the data bus (DATA 7: 0) 113 for the local bus. It operates by both a NAND circuit 56a that outputs an enable signal for data output to the data bus (LBDATA7: 0) 110, a chip select signal (cs-lbus) and an inverted read signal input (RD-N) 102. The NAND circuit 56b that outputs the bus read signal 109 and the NAND circuit 56c that operates by both the chip select signal (cs-lbus) and the inverted write signal input (WR-N) 114 and outputs the local bus write signal. And.
[0057]
In this embodiment, the signal (d-enl-in) 130 and the chip select signal (cs-lbus, cs-xx, cs-nn) output from the first delay circuit 53 are input and delayed. The timing adjustment unit 55 outputs the enable signal (d-enl) 106. The timing adjustment unit 55 uses the delay time of the signal (denl-in) 130 output from the first delay circuit 53 as a chip. It can be changed arbitrarily according to the select signal (cs-lbus, cs-xx, cs-nn). The enable signal (d-enl) 106 whose delay time is adjusted by the timing adjustment unit 55 is input to the input / output cell (IOcell) 40 and output from the local bus data bus (LBDATA7: 0) 110. The timing at which data is output to the data bus (DATA 7: 0) 113 is adjusted.
[0058]
Here, even if the timing adjustment unit 55 is a shift register that shifts the signal output from the first delay circuit 53 in accordance with the chip select signal, the timing adjustment unit 55 includes a plurality of delay circuits having different delay times. May be a variable delay circuit that selects the signal according to the chip select signal.
[0059]
FIG. 9 is a timing chart showing the operation timing of the local bus generation circuit.
[0060]
In FIG. 9, the top stage is the system clock (XIN) 100, the second stage is the address bus (ADDR10: 0) 101, the third stage is the read signal input (RD-N) 102, Internal read signal (rd) 103 in delay circuit 53, system clock falling edge synchronous internal read signal (drd-n) 104, system clock rising edge synchronous internal read signal (drd-p) 105, and first delay circuit 53, an enable signal (d-enl-in) 130 output from 53, an enable signal (d-enl) 106 output by the timing adjustment unit 55 after being delayed by a predetermined delay time 131, and an internal chip select input to the selector 52 Signal (cs-lbus) 107, address bus for local bus (LBA6: 0) 108, local Bus read signal (LBRD-N) 109, local bus data bus (LBDATA7: 0) 110 output after a large delay time (tdd) 132 has passed from a low speed device, local bus data input to selector 52 Output data (od-lbus7: 0) 111 from the bus, input data (d-o7: 0) 112 to the CPU data bus output from the selector 52, and output data (DATA7: 0) 113 to the CPU data bus Show.
[0061]
When the CPU 1b-1 shown in FIG. 2 performs a read operation on the devices 1b-7 and 1b-8 connected to the local bus 16-6, after specifying an address by the address bus (ADDR10: 0) 101, The read signal (RD-N) 102 is asserted. Then, the local bus address bus (LBA6: 0) 108 and the local bus read signal (LBRD-N) 109 are asserted 133 by the designation of the target address, and the devices 1b-7 and 1b connected to the local bus -8 outputs data to the local bus data bus (LBDATA 7: 0) 110 after a large delay time (tdd) 132 has elapsed. This data is input to the selector 52 as output data (od-lbus7: 0) 111 via the input / output cell (IOcell) 60, and the input data (d-o7: 0) 112 to the CPU data bus is output. . The output data (d-o7: 0) 112 is sent to the input / output cell (IOcell) 40, and the enable signal (d-enl) output by the timing adjustment unit 55 after being delayed by a predetermined delay time 131. 106 is activated 134 and is taken in as data (DATA 7: 0) 113 of the CPU data bus.
[0062]
Therefore, the CPU 1b-1 can reliably acquire valid data.
[0063]
【The invention's effect】
According to the image forming apparatus of the present invention, the data output from the local bus in response to the read request of the central processing unit by the peripheral ASIC provided in the image control unit that performs predetermined image processing on the data is stored in the data. Since it is configured so that it can be relayed to the central processing unit in accordance with the output timing, hazards that tend to occur when the central processing unit performs a read operation are avoided, and the image control unit performs stable control operations. This makes it possible to form a high-quality image.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating an example of a processor system that does not use a local bus that has been conventionally used.
FIG. 2 is a diagram illustrating an example of a processor system using a local bus.
FIG. 3 is a diagram illustrating an example of a local bus generation circuit.
FIG. 4 is a timing chart showing the operation timing of the local bus generation circuit.
FIG. 5 is a timing chart showing the operation timing of the local bus generation circuit when the CPU performs a read operation on a high-speed device on the local bus.
FIG. 6 is a timing chart showing the operation timing of the local bus generation circuit when the CPU performs a read operation on a low-speed device on the local bus.
FIG. 7 is a schematic configuration diagram of a copying machine showing an embodiment of the image forming apparatus of the present invention.
FIG. 8 is a diagram showing a local bus generation circuit of the present embodiment.
FIG. 9 is a timing chart showing the operation timing of the local bus generation circuit.
[Explanation of symbols]
1a-1, 1b-1 CPU
1a-2, 1b-2 ROM
1a-3, 1b-3 RAM
1a-4, 1b-4 CPU control bus
1a-5, 1b-5 CPU peripheral ASIC
1a-6, 1b-6 Local bus
1a-7, 1b-7 Device A
1a-8, 1b-8 Device B
3 Image reader
4 Image forming unit
5 Automatic document sending mechanism
6 Platen glass
7 Image controller
8 First traveling mirror
9 Second traveling mirror
10 CCD sensor
11 Photosensitive drum
12 Toner cleaner
13 Charger
14 Optical writing part
15 Developer
16 Transfer device
17 Small capacity paper cassette
18 Output tray
19 Large capacity paper cassette
20 Paper transport path
21 Fixing device
23 Paper transport mechanism
40,60 I / O cells
50 Internal circuit
51 decoder
52 selector
53 First delay circuit
54 Second delay circuit
55 Timing adjuster
56a, 56b, 56c NAND circuit
57 AND circuit
100 system clock
101 Address bus
102 Read signal input
104 System clock falling edge synchronous read signal
105 System clock rising edge synchronous read signal
106 CPU data bus data enable signal
107 Chip select signal
108 Address bus for local bus
109 Read signal output for local bus
110 Data bus for local bus
111 Data input to the selector
112 Output data from selector
113 CPU data bus
114 Write signal input
115 Input data from CPU data bus
116 Internal write signal in second delay circuit
117 System clock rising edge synchronous internal write signal
118 Signal output from second delay circuit
119 Local bus data enable signal
120 Local bus read signal is asserted
121 Selector input
122 Activated by local bus data bus enable signal
124 Data output to local bus data bus
125 Delay time until valid data is output
126 Enable signal asserted
127 Delay time until valid data is output is large
128 Enable signal asserted
129 Delay time until enable signal is asserted is large
130 Signal output from the first delay circuit
131 Predetermined delay time
132 Large delay time
133 Read signal for local bus is asserted
134 Activated by enable signal

Claims (2)

In an image forming apparatus having a plurality of devices that perform image processing on input data and forming an image based on the data subjected to the image processing,
The central processing unit that controls the plurality of devices, and the access request from the central processing unit to each of the plurality of devices is relayed to each device that has made the access request, and the read request of the access request And an integrated circuit including a timing adjustment unit that adjusts a timing for transferring data output from the device requested to be read to the central processing unit,
The timing adjustment unit sends a timing for issuing an enable signal to the device for which the read request is made in response to a selection signal for selecting the device for which the read request is made, from the device for which the read request is made to the central processing unit. An image forming apparatus characterized by delaying data output timing . In an image forming method in an image forming apparatus having a plurality of devices and an integrated circuit for performing image processing on input data and forming an image based on the data subjected to the image processing,
A central processing unit included in the integrated circuit controls the plurality of devices;
The timing adjustment unit included in the integrated circuit relays an access request from the central processing unit to each of the plurality of devices to each device for which the access request is made, and in response to a read request of the access request. Adjusting the timing for transferring the data output from the device to which the read request is made to the central processing unit;
Have
The timing adjustment unit sends a timing for issuing an enable signal to the device for which the read request is made in response to a selection signal for selecting the device for which the read request is made, from the device for which the read request is made to the central processing unit. An image forming method characterized by delaying data output timing .

Images