JP4454532B2 - Image processing device, mobile phone - Google Patents

Description

  The present invention relates to an image processing apparatus, and more particularly to an image processing apparatus that takes a captured image signal into a RAM (Random Access Memory) and performs processing. The present invention also relates to a mobile phone provided with such an image processing apparatus.

  FIG. 6 shows a block diagram of a conventional image processing apparatus. The image processing apparatus 900 includes a sensor unit 901 that captures an image, a RAM (Random Access Memory) 902 that temporarily stores data provided by the sensor unit 901, and data that is read from the RAM 902 and visually confirmed by the user. And a display unit 903 for displaying in a possible format. The display unit 903 is usually configured by a liquid crystal display or the like.

  Image data captured by the image processing apparatus 900 is provided from the sensor unit 901 to the RAM 902 for each frame. The sensor unit 901 includes a plurality of pixels arranged in a matrix, and includes a line memory (not shown) that temporarily stores pixel data for each line. Then, the pixel data held for each line from the line memory is sequentially given to the RAM 902.

  On the other hand, the display unit 903 reads the data stored in the RAM 902 and displays it at a predetermined timing. At this time, by sequentially outputting the imaging data given from the line memory to the RAM 902 to the display unit 903, the time until the video is displayed on the display unit 903 after imaging can be shortened.

  However, in the case where the display unit 903 performs rotation processing or reversal processing of the imaging data, the video is displayed until the display unit 903 reads out all the imaging data for one frame imaged by the sensor unit 901. I can't. FIG. 7 is a conceptual diagram for explaining the flow of data transfer when performing reversal processing in the display unit 903. 7A shows the sensor unit 901, and FIG. 7B shows the display unit 903.

  As shown in FIG. 7A, the imaging data captured by the sensor unit 901 is sequentially given to the RAM 902 from the first row to the n-th row for each line (n is a natural number of 2 or more). At this time, as described above, in the case where the display unit 903 displays the data obtained by performing the reversal processing on the captured image data captured by the sensor unit 901, as shown in FIG. It is necessary to read data up to one line.

  In this case, in order to transfer the n-th row data to the display unit 903, the n-th row imaging data needs to be stored in the RAM 902. For this reason, the n-th row from the sensor unit 901 to the RAM 902 is required. The display unit 903 cannot perform the display process until the imaging data is provided. That is, the time required to transfer data from the sensor unit 901 to the display unit 903 increases.

  As described above, when the data transfer time for the display unit 903 is increased, and this transfer time becomes longer than the output time interval (data output time interval for each frame) of the imaging data output from the sensor unit 901, the sensor unit Since the display unit 903 is still accessing the RAM 902 and reading out the data at the time when the imaging data relating to the next frame from 901 is output to the RAM 902, there is a problem that the sensor unit 901 cannot write to the RAM 902. To do. This state will be described with reference to FIG.

  FIG. 8 is a time chart until the imaging data given from the sensor unit 901 in FIG. 6 is output to the display unit 903 via the RAM 902. In FIG. 8, data D-91 to D-94 each represent imaging data for one frame, and each data may include a data amount corresponding to the number of pixels included in the sensor unit 901. Note that the time chart shown in FIG. 8 shows a state diagram when the imaging data output time interval for each frame is longer than the data transfer time to the display unit 903 as described above.

  The camera enable signal EN is a binary signal indicating a high state while imaging data is input from the sensor unit 901 to the RAM 902 and indicating a low state when input is completed.

  When data D-91, which is a signal relating to the first frame, is input from the sensor unit 901 to the RAM 902, the RAM 902 indicates a writing state during this input time (W-91). When the input of the data D-91 ends, the RAM 902 shifts to a reading state in which the data D-91 is transferred to the display unit 903 (R-91). Then, the data D-91 read out in the display unit 903 is displayed.

  At this time, if the data read time is longer than the data output time interval for each frame as described above, the display unit 903 reads the data D-91 from the RAM 902 before the read period of the data D-91 ends. During the process (R-91), data D-92, which is image data of the next frame, is output from the sensor unit 901 to the RAM 902. However, since the RAM 902 is accessed for reading by the display unit 903, the data D-92 cannot be written to the RAM 902, and the data D-92 is lost. To do.

  Similarly, after the data D-93, which is image data of the next frame, is input to the RAM 902 and written, the data D-93 is being read by the display unit 903, and then the next frame is read. Since the data D-94, which is imaging data, is given to the RAM 902, the data D-94 cannot be written to the RAM 902 and is lost.

As one method for solving such a problem, when a plurality of RAMs capable of storing data are provided and data is input within a period in which data is read from one RAM, the other RAM A method of preventing data loss by writing data is used (see, for example, Patent Document 1).
JP-A-6-208614

  However, in the configuration including a plurality of RAMs as described in Patent Document 1, there is a problem that the circuit scale is increased as compared with an imaging apparatus including a single RAM. Further, it is necessary to select a RAM to be written according to input data, and there is a problem that the control for selecting the RAM becomes complicated.

  In view of the above problems, the present invention provides an image processing apparatus that can transfer input data without loss, and includes an independent RAM that temporarily stores data. The purpose is to do. Another object of the present invention is to provide a mobile phone provided with such an image processing apparatus.

  In order to achieve the above object, an image processing apparatus of the present invention displays a sensor unit that captures an image and generates imaging data, and performs a reduction process that reduces the amount of data on the imaging data output from the sensor unit. A reduction processing unit that generates data and outputs the data to a subsequent stage, a buffer that temporarily stores first display data that is display data output from the reduction processing unit within a first period, and a second period The second display data that is the display data output from the reduction processing unit and the first display data that is output from the buffer are temporarily stored therein, and the first display data and A RAM that restores the display data of the frame imaged from the second display data, and a display unit that reads the display data from the RAM and performs display output. , A period in which display data is read and accessed for the previous frame stored in the RAM by the display unit, and the second period is applied to the frame from the end of the first period. This is a period until generation of all display data by the reduction processing unit, and since the RAM is in the second period and the reduction processing is performed in the reduction processing unit, the reduction processing is performed. The first display data output from the buffer is stored in a period in which the second display data write access is not performed from the unit to the RAM.

  By being configured in this way, the display unit includes a buffer that temporarily holds only the first display data among the display data output from the reduction processing unit while reading the data stored in the RAM, After the read access from the display unit is completed, the second display data output from the sensor unit is written to the RAM, and at the same time, the second display data held in the buffer is used at a timing when the RAM is not written during the reduction process. By transferring one display data to the RAM, it is possible to realize an image processing apparatus constituted by a single RAM without data loss.

  Further, since the buffer is used only for the purpose of holding the data output from the sensor unit while the display unit reads out the data stored in the RAM, the capacity of the buffer can be greatly reduced compared to the RAM. it can. That is, the circuit scale can be reduced as compared with an image processing apparatus including a plurality of RAMs.

  Furthermore, in the configuration of the present invention, since the read-out RAM from which the display unit reads display data is single, the read-out source from which data is read out by the display unit is selected as compared with an image processing apparatus having a plurality of RAMs. There is no need to perform control. That is, the read control when the display unit reads data is simplified.

  In addition, the reduction processing unit includes an access memory that temporarily holds imaging data supplied from the sensor unit, and is supplied from the sensor unit until a predetermined number of data necessary for the reduction processing is provided. The captured image data is held in the access memory, and when the predetermined number of pieces of captured data is held in the access memory, a reduction process may be performed to output the data to the subsequent stage.

  At this time, when imaging data is given for each line from the sensor unit and data of a predetermined number of lines is held in the access memory, when imaging data relating to the next line is input, the input imaging A configuration may be adopted in which reduction processing is performed using the data and the imaging data held in the access memory and output to the subsequent stage.

  Further, the RAM may secure an area for storing the first display data output from the buffer in advance when storing the second display data within the second period. .

  At this time, a first counter configured to count up each time a predetermined unit amount of data subjected to reduction processing by the reduction processing unit is output, and the first counter output from the reduction processing unit. The second counter is configured to count up each time a predetermined unit amount of display data is output to the buffer, and the second display data output from the buffer is predetermined to the RAM. A third counter that is configured to count up each time a unit amount is output, and the first to third counters have a count value corresponding to an image picked up by the sensor unit. The RAM is configured to be reset, and the RAM stores the second display data given from the reduction processing unit in an address area corresponding to a count value of the first counter. Recognizing that the first display data amount corresponding to the count value indicated by the second counter is held in the buffer, reading the data amount corresponding to the count value from the buffer, The read first display data may be stored in an address area corresponding to the count value of the third counter.

  At this time, the predetermined unit amount may be a data amount for one line. In other words, the reduction processing unit may output data to the buffer or RAM for each line, and the first counter may be incremented every time data for one line is output. Furthermore, the second counter may be incremented each time a data amount for one line is written from the reduction processing unit to the buffer. Further, the third counter may be incremented each time the data amount for one line is transferred from the buffer to the RAM and written.

  With this configuration, the first display data output from the reduction processing unit while the display unit reads the RAM cannot be written to the RAM, but is temporarily held in the buffer, and the first display data is stored in the buffer. Since an address for storing one display data on the RAM is secured in advance, writing to this address area allows the display data for one frame output from the reduction processing unit to be restored on the RAM. .

  According to the configuration of the present invention, only the imaging data (strictly speaking, the display data obtained by reducing the imaging data) output from the sensor unit while the display unit reads out the data stored in the RAM is temporarily stored. After the read access from the display unit is completed, the imaging data output from the sensor unit is written to the RAM, and the buffer is held using the timing at which the RAM is not written during the reduction process. By transferring the processed data to the RAM, it is possible to realize an image processing apparatus constituted by a single RAM without data loss.

  Further, since the buffer is used only for the purpose of holding the data output from the sensor unit while the display unit reads out the data stored in the RAM, the capacity of the buffer can be greatly reduced compared to the RAM. it can. That is, the circuit scale can be reduced as compared with an image processing apparatus including a plurality of RAMs.

  Furthermore, in the configuration of the present invention, since the reading source RAM from which the display unit reads display data is independent, the reading source from which data is read by the display unit is selected as compared with an image processing apparatus having a plurality of RAMs. There is no need for control. That is, the read control when the display unit reads data is simplified.

  Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of an image processing apparatus according to an embodiment of the present invention.

  An image processing apparatus 1 shown in FIG. 1 includes a sensor unit 2 that captures an image, a data input unit 3 to which imaging data is input from the sensor unit 2, and data visually transferred from the data input unit 3. And a display unit 4 for displaying in a form that can be confirmed. The display unit 4 is usually configured by a liquid crystal display or the like.

  Image data captured by the image processing apparatus 1 is given from the sensor unit 2 to the data input unit 3 for each frame. The sensor unit 2 includes a plurality of pixels arranged in a matrix and includes a line memory (not shown) that temporarily stores pixel data for each line. Then, the pixel data held for each line from the line memory is sequentially supplied to the data input unit 3.

  The data input unit 3 includes a buffer 6 for temporarily storing data, and a RAM 7. Of these, the buffer 6 may be configured to have a significantly smaller storage capacity than the RAM 7.

  Further, the data input unit 3 includes a reduction processing unit 5 that performs a reduction process on the data input from the sensor unit 2. Usually, the number of pixels included in the sensor unit 2 (hereinafter referred to as “number of imaging pixels”) is larger than the number of pixels included in the display unit 4 (hereinafter referred to as “number of display pixels”). The reduction data obtained by reducing the imaging data constituted by the amount to the data amount corresponding to the number of display pixels is generated, and the display unit 4 reads out the reduced data, so that the display unit 4 has display data corresponding to the imaging data. This is the configuration displayed. The reduction processing unit 5 is a block that performs reduction processing for reducing the number of pixels in order to convert the imaging data provided from the sensor unit 2 into display data, and is configured by hardware or software including a reduction algorithm. The reduction processing unit 5 includes an access memory (not shown) for temporarily storing data. Hereinafter, the imaging data after the reduction processing by the reduction processing unit 5 is referred to as “display data”.

  The image processing apparatus 1 also includes an input control unit 8 that controls each component of the data input unit 3. As will be described later, when the imaging data input for each line from the sensor unit 2 is input to the reduction processing unit 5, it is stored in the access memory until the imaging data of the number of lines necessary for performing the reduction processing is input. Stored temporarily. When necessary data is stored in the access memory, the data is read from the access memory, subjected to reduction processing, and then output to the RAM 7 or the buffer 6. At this time, whether to output to either the RAM 7 or the buffer 6 is controlled by the input control unit 8.

  Further, the input control unit 8 includes a counter for designating a write destination address when data is written to the RAM 7. The operation description regarding this counter will be described later.

  As will be described later, the reduction processing unit 5 compresses the data amount by performing reduction processing on the imaging data from a given sensor for each predetermined number of rows. At this time, for example, when the reduction processing is performed every three rows and the data amount is compressed to 1/3, the data for the first two rows is held in the access memory, and the data of the third row is input. Then, it is possible to adopt a configuration in which reading is performed from the access memory and compression processing is performed using the input value and the value read from the memory.

  Further, the input control unit 8 performs timing control for transferring the data stored in the buffer 6 to the RAM 7. As described above, a part of the data subjected to the reduction processing by the reduction processing unit 5 is written in the buffer 6, so that the data written in the buffer 6 is transferred to the RAM 7 at a predetermined timing. Accordingly, the display unit 4 is configured to be able to acquire all necessary data by accessing only the RAM 7.

  Next, reduction processing performed in the reduction processing unit 5 will be described with reference to the drawings. FIG. 2 is a conceptual diagram showing a process in which image data supplied from the sensor unit 2 is subjected to reduction processing and then output to the RAM 6 or the buffer 7.

  As described above, the sensor unit 2 includes a plurality of pixels arranged in a matrix, and pixel data is stored in the line memory for each line. The pixel data held for each line is sequentially supplied from the line memory to the reduction processing unit 5.

  The reduction processing unit 5 temporarily stores the data given to the access memory, reads the data from the access memory when a predetermined amount of data necessary for the reduction processing calculation is given, performs the reduction processing, and outputs the data To do. FIG. 2 shows an example in which an operation for reducing the data amount to 1/3 is performed by performing a reduction operation every three lines.

  According to the example shown in FIG. 2, the imaging data is sequentially input from the first row from the sensor unit 2, and the data is held in the access memory until the second row of data is input. Then, the data of the third row is inputted, the data concerning the first row and the second row are read from the access memory, and the reduction processing is performed together with the data concerning the inputted third row. Then, the data for three lines subjected to the reduction process is written to the RAM 7 or the buffer 6 (L-1d). The same procedure is performed for the fourth and subsequent rows.

  As will be described later, the calculation result subjected to the reduction processing is selected so as to be output to either the RAM 7 or the buffer 6 by the input control unit 8, but in FIG. 2 and FIG. Will be described on the assumption that all are to be output to the RAM 7.

  FIG. 3 is a time chart until data relating to a certain frame subjected to the reduction processing from the sensor unit 2 via the reduction processing unit 5 is written to the RAM 7. The sensor output shown in FIG. 3 shows a state in which imaging data for each line relating to a certain frame is sequentially output, and L-1 to L-7 represent imaging data relating to the first to seventh rows, respectively. ing. In FIG. 3, the reduction process is performed every three lines. However, the reduction process is not limited to every three lines, and may be performed every predetermined number of lines.

  As described above, after the data L-1 and L-2 are written in the access memory and then the data L-3 for the third row is input from the sensor unit 2, the reduction processing unit 5 The data L-1 and L-2 stored in the data are read out, and the reduction operation is performed using the input data L-3. At this time, for example, when performing an arithmetic operation for taking an average value for each column, it is not necessary to wait until the data L-3 is completely input, and the data of each column constituting the third row is sequentially input. Each time, it is possible to perform an operation using data relating to the first row and the second row located in the same column as the data. In this case, the time from the end of the input of the data L-3 to the completion of the reduction process for the three rows of the data L-1 to L-3 by the reduction processing unit 5 is very short.

  The reduction processing unit 5 outputs the calculation result to the RAM 7 each time the calculation related to the reduction processing is performed. At this time, as in the above-described example, in the case of performing an operation that takes an average value for each column, when the operation for each column is completed, the operation result is output each time, and the operation proceeds to the operation for the next column. can do. That is, the time from the end of the input of the data L-3 in the third row to the output of the reduction processing results for the three rows of data L-1 to L-3 by the reduction processing unit 5 to the RAM 7 is as follows. It will be very little time.

  When the reading of the data L-3 is completed, the data L-4 related to the fourth row is continuously input. The fourth to sixth rows are performed in the same procedure as the reduction processing from the first to third rows. That is, the data L-4 in the fourth row and the data L-5 in the fifth row are once stored in the access memory, and when the data L-6 in the sixth row is input, L-4 and L from the access memory. In addition to reading −5, reduction processing is performed using the input data L-6, and the calculation result is output to the RAM 7.

  That is, as shown in the time chart of FIG. 3, when imaging data relating to a certain frame is given to the data input unit 3 for each line and written to the RAM 7, data is sequentially input from the sensor unit 2. On the other hand, access to the RAM 7 for writing data is not continuous, and a time during which access is not performed occurs. As will be described later, the data stored in the buffer 6 is stored in the RAM 7 by the input control unit 8 by using this time during which the RAM 7 is not accessed while the imaging data is input from the sensor 2 to the data input unit 3. Control writing.

  FIG. 4 is a time chart until the imaging data given from the sensor unit 2 is output to the display unit 4 via the data input unit 3 in the image processing apparatus 1 according to the present embodiment. In FIG. 4, data D-1 to D-4 each represent imaging data for one frame, and each data may include a data amount corresponding to the number of pixels included in the sensor unit 2. Note that the time chart shown in FIG. 4 shows a state diagram when the imaging data output time interval for each frame is longer than the data transfer time to the display unit 4 as in FIG. 8 in order to emphasize the effect of the present invention. ing.

  The camera enable signal EN is a binary signal indicating a high state while imaging data is being input from the sensor unit 2 to the data input unit 3 and indicating a low state when input is completed.

  When data D-1 which is a signal relating to the first frame is input from the sensor unit 2 to the data input unit 3, after the reduction processing is performed by the reduction processing unit 5 as described above, Data d-1 is written to the RAM 7 (W-1). When the data d-1 is written to the RAM 7, the display unit 4 accesses the RAM 7 and reads the data d-1 (R-1).

  Then, while the display unit 4 is reading the data d-1 from the RAM 7, the data D-2 as the next frame is input from the sensor unit 2 to the data input unit 3. The data D-2 is subjected to reduction processing by the reduction processing unit 5 in the same manner as D-1. Of the data d-2 after this processing, the data d output from the reduction processing unit 5 during the period (R-1) in which the display unit 4 performs read access for reading the data d-1 into the RAM 7. -21 is output to the buffer 6 (W-21), and the data d-22 output from the reduction processing unit 5 after the read access from the display unit 4 is completed is output to the RAM 7 (W-22). ).

  As described above with reference to FIG. 3, after the reduction processing is performed on the imaging data supplied from the sensor unit 2, the RAM 7 is actually accessed in order to write the output from the reduction processing unit 5 in a series of processes written to the RAM 7. The time that is spent is the time to fly, not continuous. That is, there is a time during which the data d-22 is being output to the RAM 7 (W-22) and the RAM 7 is not accessed for writing.

  Using this non-accessed time, the input control unit 8 controls to write the data d-21 stored in the buffer 6 to the RAM 7. It is assumed that the input control unit 8 is configured to be able to grasp in advance the timing for performing the calculation related to the reduction process by accessing the reduction processing unit 5. That is, since the reduction processing unit 5 does not access to write to the RAM 7 during the period in which the data necessary for the operation is stored in the access memory, the input control unit 8 receives the data from the reduction processing unit 5. In this configuration, the timing at which the calculation result is written to the RAM 7 and the timing at which no write access to the RAM 7 is performed can be grasped.

  Therefore, the input control unit 8 performs control to write the data d-21 held in the buffer 6 to the RAM 7 when the reduction processing unit 5 does not perform write access to the RAM 7. Thus, the data d-21 that has not been written in the RAM 7 among the data d-2 is also held in the RAM 7.

  In order to correctly restore the data d-2 from the data d-21 written directly from the reduction processing unit 5 to the RAM 7 and from the data d-22 written from the buffer 6 to the RAM 7, the data d-21 or the data d is restored. It is necessary to specify an address at which −22 is written to the RAM 7. This address designation method will be described later.

  Hereinafter, similarly, the reduction processing unit 5 performs reduction processing on the imaging data D-3 for the next frame, and the display unit 4 stores the data d-2 in the RAM 7 among the data d-3 after this processing. The data d-31 output from the reduction processing unit 5 during the period of read access for reading (R-2) is output to the buffer 6 (W-31), and the read access from the display unit 4 is performed. The data d-32 output from the reduction processing unit 5 after the end is output to the RAM 7 (W-32). Then, the input control unit 8 performs control to write the data d-31 held in the buffer 6 to the RAM 7 when the reduction processing unit 5 does not perform write access to the RAM 7. Thereafter, the same control is performed for each frame.

  By performing such control, even in the image processing apparatus 1 including the single RAM 7, the imaging data input while the display unit 4 is reading and accessing the RAM 7 is temporarily stored in the buffer 6. Since the free time that can be written to the RAM 7 can be found and the data can be written from the buffer 6 to the RAM 7, the display image data for each frame is held in the RAM 7 in a state where there is no data loss. Thereby, the imaging data concerning all the frames can be output to the display unit 4 as display data.

  Hereinafter, a method for restoring display data from data directly written in the RAM 7 from the reduction processing unit and data written in the RAM 7 from the buffer 6 once stored in the buffer 6 will be described with reference to the drawings. FIG. 5 is a time chart and conceptual diagram for explaining the process of writing data d-2 from the reduction processing unit 5 to the RAM 7 and the buffer 6 in FIG. FIG. 5A is a time chart, and FIG. 5B is a conceptual diagram. In the following, the data d-2 will be described, but the same applies to other data.

  In FIG. 5, data d-2 is composed of M rows of data (M is a natural number of 4 or more, and so on). Further, the lines output from the reduction processing unit 5 during the reading of the data d-1 related to the first frame written in the RAM 7 (R-1) are three lines from the first row to the third row (d- 21) It is assumed that there is no read access from the display unit 4 to the RAM 7 while the display data from the fourth line to the Mth line is being output (d-22).

  As shown in FIG. 5A, when the display data relating to the first to third lines is output from the reduction processing unit 5, the input control unit 8 controls to be written into the buffer 6. The display control data from the fourth line to the Mth line is controlled by the input control unit 8 to be written in the RAM 7.

  FIG. 5B shows a conceptual diagram when the display data d-2 is written in the RAM 7. As described above, the display data from the fourth row to the Mth row given from the reduction processing unit 5 is written into the RAM 7. At this time, the display from the first row to the third row given from the buffer 6 is performed. After securing an area for writing data for display, display data for the fourth and subsequent rows is written. Then, the display data for the first to third rows is read from the buffer 6 using the time during which the above-described write access to the RAM 7 is not performed, and is written in a predetermined area reserved in advance.

  As described above, when data is written to the RAM 7, the write destination address of the data is controlled by the input control unit 8. In order to designate this address, the input control unit 8 is provided with an address designation counter. At this time, a counter (hereinafter referred to as a “first counter”) for designating a write destination address when the display data output from the reduction processing unit 5 is written in the RAM 7 and the display data written in the buffer 6 are displayed. A counter (hereinafter referred to as a “second counter”) for designating a write destination address when data is read and written to the RAM 7 and a counter for counting the number of display data written in the buffer 6 ( Hereinafter, it will be referred to as a “third counter”.

  These first to third counters are reset when data relating to the next frame is input, that is, in response to the rise of the camera enable signal EN.

  The first to third counters do not need to be configured by individual counter circuits, but operate in the same counter circuit individually for each digit, so that the operation is equivalent to that of the individual three counters. You may make it the structure which performs.

  The first counter is configured to be counted up every time data reduced by the reduction processing unit 5 is output. In the example shown in FIG. 2, when data for one line after the reduction processing for three lines is output, the data is counted up by one. At this time, regardless of whether the output destination is the RAM 7 or the buffer 6, the first counter is incremented by one each time data is output.

  The second counter is configured to count up each time display data output from the reduction processing unit 5 is output to the buffer 6. In the example shown in FIG. 5, since the data for the first three lines of the data d-2 is written to the buffer 6, when the data is completely written to the buffer 6, that is, from the display unit 4 to the RAM 7 When the read access to is completed and the write access to the RAM 7 is enabled from the reduction processing unit 5, the count value of the second counter is “3”. Since the data on and after the fourth row is directly written into the RAM 7 from the reduction processing unit 5, the count value of the second counter holds “3” until the data on the Mth row is written into the RAM 7.

  When the display data is supplied from the reduction processing unit 5, the buffer 6 holds the data at an address position corresponding to the count value of the second counter. For example, in the example shown in FIG. 5, when the data for the first row is given from the reduction processing unit 5, the count value of the second counter at that time indicates “1”. The data is held at the address position corresponding to “”. Similarly, data relating to the second row is held at an address position corresponding to the count value “2”, and data relating to the third row is held at an address position corresponding to the count value “3”. Hereinafter, description will be given using the example shown in FIG.

  After the data up to the third line is output to the buffer 6, the input control unit 8 performs control so that the data after the fourth line is written to the RAM 7. At this time, when the reduction processing unit 5 outputs the data of the fourth row, the input control unit 8 confirms the count value of the first counter and gives an instruction to output to the address position of the RAM 7 according to the count value. . As described above, since the first counter is configured to count up each time data is output from the reduction processing unit 5, at the time when the data in the fourth row is output, the count value of the counter is “ 4 ".

  When the input control unit 8 confirms the count value “4” of the first counter, the input control unit 8 gives an instruction to write the data in the fourth row at the address position corresponding to the count value “4” of the RAM 7. Similarly, after the fifth line, when the reduction processing is completed in the reduction processing unit 5, the input control unit 8 confirms the count value of the first counter and stores the data at the address position of the RAM 7 corresponding to the count value. Give instructions to export.

  In such a configuration, when the data on the Mth row is written to the RAM 7, the data is written to the address positions corresponding to the count values “1”, “2”, and “3” of the RAM 7. Not done. That is, an area in which the data relating to the first to third rows already held in the buffer 6 is to be written to the RAM 7 is secured.

  As described above, there is a timing during which write access to the RAM 7 is not performed within the period W-22 in FIG. 5, and this timing can be grasped by the input control unit 8. When the timing at which write access to the RAM 7 is not made comes, the input control unit 8 instructs the buffer 6 to write the data held in the buffer 6 (data relating to the first to third rows) to the RAM 7. .

  At this time, since the second counter indicates the count value “3”, the input control unit 8 can grasp the number of data held in the buffer 6 by checking the count value of the second counter. it can. Then, the data is read from the buffer 6 and written to the address of the RAM 7 corresponding to the address where the data is held. At this time, the third counter is counted up.

  For example, when the input control unit 8 reads data relating to the first row from the buffer 6, the data relating to the first row is stored at a predetermined address position in the RAM. At this time, the input control unit 8 may designate the address position of the RAM 7 to be written in accordance with the address position stored in the buffer, confirm the count value of the third counter, and respond to the count value. The address position of the RAM 7 may be designated. In the latter case, since the count value of the third counter is “0” when the data for the first row is read from the buffer 6, the data given from the buffer 6 at the time of the count value “0” in advance is the first value. When the input control unit 8 grasps the content indicating that the data is for one line, an instruction to write the data for the first line in a predetermined address area of the RAM 7 can be given.

  The third counter may be configured to set the count value to “1” at the time of resetting in advance.

  When the data relating to the first row is written from the buffer 6 to the RAM 7, the third counter is counted up. Next, when the input control unit 8 recognizes the timing at which the RAM 7 can be accessed for writing, it reads the data relating to the next second row and similarly writes to the predetermined area of the RAM 7 to count up the third counter. To do. By performing this operation for the number of times indicated by the count value of the second counter, all the data held in the buffer 6 can be correctly transferred to the RAM 7.

  With this configuration, the data that is temporarily stored in the buffer 6 cannot be written to the RAM 7 because the data is output from the reduction processing unit 5 while the display unit 4 reads the RAM 7. Since the address where the data is to be stored on the RAM 7 is secured in advance, the display data for one frame output from the reduction processing unit 5 can be restored on the RAM 7 by writing to this address area. It becomes possible.

  Therefore, after the writing to the RAM 7 is completed, the display unit 4 performs read access to the RAM 7 so that the display data relating to this frame is transferred to the display unit 4, and the display screen relating to the frame is correctly output on the display unit 4. .

  According to the configuration of the present invention, only the imaging data (strictly speaking, the display data obtained by reducing the imaging data) output from the sensor unit while the display unit reads out the data stored in the RAM is temporarily stored. After the read access from the display unit is completed, the imaging data output from the sensor unit is written to the RAM, and the buffer is held using the timing at which the RAM is not written during the reduction process. By transferring the processed data to the RAM, it is possible to realize an image processing apparatus constituted by a single RAM without data loss.

  Further, since the buffer is used only for the purpose of holding the data output from the sensor unit while the display unit reads out the data stored in the RAM, the capacity of the buffer can be greatly reduced compared to the RAM. it can. That is, the circuit scale can be reduced as compared with an image processing apparatus including a plurality of RAMs.

  Furthermore, in the configuration of the present invention, since the display unit from which the display unit reads the display data is a single RAM, the reading unit from which data is read by the display unit is selected as compared with an image processing apparatus having a plurality of RAMs. There is no need for control. That is, the read control when the display unit reads data is simplified.

  The image processing apparatus of the present invention can be suitably used for a digital camera having a display for display or a mobile phone equipped with a digital camera function.

These are block diagrams which show the structure of the image processing apparatus which is one Embodiment of this invention. FIG. 3 is a conceptual diagram showing a process of performing reduction processing on imaging data given from a sensor unit in FIG. 1 and then outputting it to a RAM or a buffer. These are time charts until data relating to a certain frame subjected to reduction processing from the sensor unit in FIG. 1 is written to the RAM. These are time charts until imaging data given from the sensor unit in FIG. 1 is output to the display unit via the data input unit. FIG. 4 is a time chart and conceptual diagram for explaining a process of writing data d-2 from the reduction processing unit to the RAM and the buffer in FIG. FIG. 2 is a block diagram of an image processing apparatus having a conventional configuration. These are the conceptual diagrams for demonstrating the flow of data transfer when performing inversion processing in the display part in FIG. These are time charts until imaging data given from the sensor unit in FIG. 6 is output to the display unit via the RAM.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Image processing apparatus 2 Sensor part 3 Data input part 4 Display part 5 Reduction process part 6 Buffer 7 RAM
900 Image processing device 901 Sensor unit 902 RAM
903 display

Claims (5)

A sensor unit that captures an image and generates imaging data;
A reduction processing unit for generating display data by performing a reduction process for reducing the amount of data to the imaging data output from the sensor unit;
A buffer that temporarily stores first display data that is display data output from the reduction processing unit within a first period;
Temporarily storing second display data that is display data output from the reduction processing unit and the first display data output from the buffer within a second period, and the first display data A RAM for restoring display data relating to the frame imaged from the display data and the second display data;
A display unit that reads the display data from the RAM and performs display output;
The first period is a period in which display data is read and accessed for the previous frame stored in the RAM by the display unit,
The second period is a period from when the first period ends to when the reduction processing unit finishes generating all display data related to the frame,
The RAM is in the second period, and the reduction processing is being performed in the reduction processing unit, so the second display data is not written to the RAM from the reduction processing unit. An image processing apparatus for storing the first display data output from the buffer within a period. The reduction processing unit
An access memory for temporarily holding imaging data provided by the sensor unit;
Until the predetermined number of data required for the reduction processing is given, the imaging data given from the sensor unit is held in the access memory, and the imaging data having the predetermined number of data is held in the access memory. The image processing apparatus according to claim 1, wherein the image processing apparatus performs reduction processing and outputs data to a subsequent stage.   The RAM reserves an area for storing the first display data output from the buffer in advance when storing the second display data within the second period. The image processing apparatus according to claim 1 or 2. A first counter configured to count up each time a predetermined unit amount of data subjected to reduction processing by the reduction processing unit is output;
A second counter configured to count up each time the first display data output from the reduction processing unit is output to the buffer by a predetermined unit amount;
A third counter configured to count up each time the second display data output from the buffer is output to the RAM by a predetermined unit amount,
The first to third counters are configured such that the count value is reset-controlled in response to an image being captured by the sensor unit,
The RAM is
Storing the second display data provided by the reduction processing unit in an address area corresponding to a count value of the first counter;
Recognizing that the first display data amount corresponding to the count value indicated by the second counter is held in the buffer, reading the data amount corresponding to the count value from the buffer, 4. The image processing apparatus according to claim 3, wherein the read first display data is stored in an address area corresponding to a count value of the third counter.   A mobile phone having a camera function, comprising the image processing device according to claim 1.

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