JP4454982B2 - Photometric circuit - Google Patents

Description

  The present invention relates to a photometric circuit that uses a photodiode as a light receiving element and converts the received light signal into a current-voltage, for example, an integration type photometric circuit used for a camera or the like.

  FIG. 9 shows a configuration example of an integrating photometry circuit conventionally used in cameras. In the photometric circuit shown in FIG. 9, a photodiode 102 is connected between the non-inverting terminal and the inverting terminal of the operational amplifier circuit 101, the inverting terminal of the operational amplifier circuit 101 and the output terminal of the operational amplifier circuit 101 are connected, One end of an integration capacitor 103 whose non-inverting terminal and the other end of the operational amplifier circuit 101 are grounded and one terminal of a switch 104 are connected, and the other terminal and one end of the switch 104 are grounded. The other end is connected and configured.

  Next, the operation of the photometric circuit according to this conventional example will be described. First, before the start of integration, the switch 104 is turned on. At this time, the voltage VREF of the reference voltage source 105 is output to the output terminal of the operational amplifier circuit 101.

  Next, the switch 104 is switched from ON to OFF in accordance with an instruction to start photometry. Thus, the integration is started, and the voltage VOUT output to the output terminal of the operational amplifier circuit 101 is expressed by the following equation (1).

VOUT = VREF + (Ipd1 × t) / C1 (1)
Here, Ipd1 is the photocurrent of the photodiode 102, t is the integration time, and C1 is the capacitance value of the integration capacitor 103.

  Further, FIG. 10 shows a configuration example of another integration type photometry circuit. In the configuration example shown in FIG. 10, a photodiode 102 is connected between the non-inverting terminal and the inverting terminal of the operational amplifier circuit 101, and between the inverting terminal of the operational amplifier circuit 101 and the output terminal of the operational amplifier circuit 101, The integrating capacitor 103 and the switch 104 are connected in parallel, and the non-inverting terminal of the operational amplifier circuit 101 and the reference voltage source 104 are connected.

  Next, the operation of this configuration example will be described. First, before the start of integration, the switch 104 is turned on. At this time, the voltage VREF of the reference voltage source 105 is output to the output terminal of the operational amplifier circuit 101.

  Next, the switch 104 is switched from ON to OFF in accordance with an instruction to start photometry. Thus, the integration is started, and the voltage VOUT output to the output terminal of the operational amplifier circuit 101 is expressed by the following equation (2).

VOUT = VREF− (Ipd1 × t) / C1 (2)
Here, Ipd1 is the photocurrent of the photodiode 102, t is the integration time, and C1 is the capacitance value of the integration capacitor 103.

An integrating photometry circuit used in cameras is often used for flash light control. Incidentally, this kind of integral-type photometric circuit is disclosed in Japanese Patent Laid-Open No. 5-288604.
JP-A-5-288604

  By the way, in the photometry circuit of the integration method, when the photodiode and the integration circuit are configured on the same semiconductor substrate in order to reduce the mounting area and the cost, the cathode (or the anode) of the photodiode is arranged due to the process configuration. Generally, it is connected to a common region (usually the highest potential) of the semiconductor substrate. In the divided photodiode used in the camera, the cathodes (or anodes) of the plurality of photodiodes are connected to the common region of the semiconductor substrate. However, in the integrating photometry circuit having the configuration shown in the conventional example, it is difficult to realize the connection mode of the photodiode because of the circuit configuration.

  The present invention has been made by paying attention to the above viewpoint, and the photodiode and the integration circuit can be configured on the same semiconductor substrate. Further, when the photocurrent of the photodiode changes abruptly, the substrate An object of the present invention is to provide an integration-type photometry circuit in which the integration error due to the influence of the bias current is reduced as much as possible so as not to deteriorate the photometry characteristics.

In order to solve the above problems, the invention according to claim 1 is directed to a photodiode having one terminal connected to one power source and the first and second in order to set the bias of the photodiode substantially constant . And a first semiconductor element having a control terminal for controlling a current from the first terminal to the second terminal, the first terminal being connected to the other terminal of the photodiode; An operational amplifier circuit in which an inverting input terminal is connected to the other terminal of the photodiode, a non-inverting input terminal is connected to the power supply or another power supply, and an output terminal is connected to the control terminal of the first semiconductor element. a bias setting portion comprises, connected to said inverting input terminal of the operational amplifier circuit of the bias setting portion, when the photocurrent flowing through the photodiode is reduced, the current the bias setting from current source Comprising a current applying unit for applying to the part, integrates the output current from the generally set to a constant bias the photodiode, and a integral output portion in which the photodiode and outputs a signal corresponding to the amount of light received This constitutes a photometric circuit.

  The invention according to claim 2 is the photometric circuit according to claim 1, wherein the current application unit applies the current from the current source between photometry and the next photometry. is there.

The invention according to claim 3, in photometric circuit according to claim 2, wherein the photodiode is one of the terminals of the anode or the cathode terminal of that is connected the one of the power supply, the current applying section, the first and a second terminal, and a control terminal for controlling the current of the to the second terminal from the first terminal, is connected to the control terminal to a control terminal of the first semiconductor, said second terminal the second semiconductor element and a current source connected to a first terminal of the second semiconductor element and the other end to said one end of the power at one end, one terminal the current but connected to the other power supply A switch connected to the other end of the source and the first terminal of the second semiconductor element, and the other terminal connected to the inverting input terminal of the operational amplifier circuit, A first integral capacitor connected to a second terminal of one semiconductor element; The voltage integrated by the integrating capacitor of the first, the photodiode is characterized in that it comprises a, and an output circuit for outputting a signal corresponding to the amount of light received.

According to a fourth aspect of the present invention, in the photometric circuit according to the third aspect , the bias setting unit further includes a switch for connecting the inverting input terminal of the operational amplifier and the other terminal of the photodiode. It is characterized by.

The invention according to claim 5 is the photometric circuit according to any one of claims 1 to 4 , wherein each component is formed on the same semiconductor substrate.

According to the photometric circuit configured as in the invention according to the claims 1-4, the configuration of the process, one electrode of the full Otodaio de, or cathode (or anode) is a common region (usually the highest potential of the semiconductor substrate even when it is connected to) it can be configured off Otodaio de and an integrating circuit in the same semiconductor substrate. Furthermore, even if the full Otodaio de photocurrent rapidly changes, the voltage at the inverting input terminal of the operational amplifier after the metering operation is completed, the voltage close to when a peripheral has received the full Otodaio de during darkness, quickly converged Therefore, it is possible to reduce an integration error caused by circuit factors at the next photometry, and to realize an integration-type photometry circuit that does not deteriorate the photometry characteristics. In the photometric circuit configured as in the invention according to the fifth aspect , it is possible to contribute to cost reduction of the IC by configuring all the circuits on the same semiconductor substrate. Further, in the circuit configuration of the light measuring circuit according to claims 1 to 4, it can cope with a plurality of full Otodaio de anode or cathode is connected in common to the semiconductor substrate. Therefore, the Oh Ru full Otodaio de such constraint multiple photometric circuit can be realized on the same semiconductor substrate be used.

  Next, the best mode for carrying out the invention will be described.

  FIG. 1 is a circuit configuration diagram showing Embodiment 1 of a photometric circuit according to the present invention. This embodiment corresponds to the invention according to claim 1. Here, a case where a MOS transistor is used as a semiconductor element having first and second terminals and a control terminal for controlling a current from the first terminal to the second terminal will be described. The same applies to other embodiments. As shown in FIG. 1, in the photometric circuit of this embodiment, the photodiode 1 is set to a substantially zero bias or the reverse bias between the photodiode 1 whose cathode is connected to the power supply VCC1 and the integral output unit 2. And a current application unit 4 for applying a current to the bias setting unit 3.

  The bias setting unit 3 connects the anode of the photodiode 1 to the inverting terminal of the operational amplifier circuit 5 and the source terminal of the Pch-MOS transistor Q1, connects the non-inverting terminal of the operational amplifier circuit 5 to the power supply 6, and the transistor The gate terminal of Q1 and the output terminal of the operational amplifier circuit 1 are connected, and the drain terminal of the transistor Q1 is connected to the input of the integration output unit 2.

  Next, the operation of the photometry circuit configured as described above will be described. FIG. 2 shows an example of the photometry timing of the photometry circuit. For example, when the photocurrent Ipd1 from the photodiode 1 suddenly decreases at the end of the first integral photometry 1, ideally the voltage at the inverting terminal of the operational amplifier circuit 5 is shown. Is always the same as the voltage at the non-inverting terminal of the operational amplifier circuit 5 due to the virtual ground, and as a result, the drain current IGOUT of the transistor also changes in the same manner as Ipd1 as shown in the following equation (3).

IGOUT = Ipd1 (3)
However, in practice, the open loop gain of the operational amplifier circuit 5 is finite, and when the photocurrent Ipd1 varies, the voltage between the source and gate of the transistor Q1 varies. The voltage also fluctuates. In the photodiode 1, a parasitic capacitance Cpd exists in parallel between the cathode and the anode, and a phase compensation capacitor Cop for stably operating the operational amplifier circuit 5 exists in the photodiode 1 in parallel. Therefore, when the voltage at the inverting terminal of the operational amplifier circuit 5 fluctuates, the parasitic capacitance Cpd and the phase compensation capacitance Cop are charged and discharged, and the current from these capacitances is added to IGOUT with a time constant, and the integration output unit It flows to 2.

  This time constant becomes longer as the current flowing to the source current of the transistor Q1 is smaller. As shown by hatching in FIG. 2, if IGOUT remains until the next photometry 2 is operated, Cause an integration error during photometry. In order to prevent this, the time constant between the current application unit 4 and the photometry is sufficiently small between the end of the first integral photometry 1 and the timing of the next integral photometry 2, and a current as small as possible is amplified. Applied to the inverting terminal of the circuit 5. That is, a dark bias is set for the photodiode 1. Thereby, even if the charging / discharging current of the parasitic capacitance Cpd and the phase compensation capacitance Cop flows, the influence on the next integral photometry can be eliminated.

  Next, Example 2 will be described. FIG. 3 is a circuit configuration diagram showing Embodiment 2 of the photometry circuit according to the present invention. This embodiment corresponds to the invention according to claim 2. As shown in FIG. 3, in this embodiment, the cathode of the photodiode 1 is connected to the power supply VCC1, the anode is connected to the inverting terminal of the operational amplifier circuit 1 and the source terminal of the Pch-MOS transistor Q1, and the operational amplification is performed. The non-inverting terminal of the circuit 1 is connected to the power source 6, and the gate terminal of the Pch-MOS transistor Q1 and the output terminal of the operational amplifier circuit 1 are connected to form the bias setting unit 3 in the same manner. The drain terminal of the transistor Q1 is connected to one terminal of the integration capacitor 7 and the switch 8, the other terminal of the switch 8 is connected to the reference voltage source 9, and the connection point between the transistor Q1 and the integration capacitor 7 is connected. A buffer circuit 10 that extracts a voltage obtained by integrating the output current IGOUT by the integration capacitor 7 as an output voltage is connected to constitute an integration output unit 2. Also, the current source 11 and the source terminal of the Pch-MOS transistor Q2 are connected to the inverting terminal of the operational amplifier circuit 5 via the switch 12, the gate terminal of the transistor Q2 and the gate terminal of the transistor Q1 are connected, The drain terminal of the transistor Q2 is grounded to form a current application unit 4.

  Next, the operation of the photometry circuit according to the second embodiment configured as described above will be described with reference to a timing example of the photometry circuit shown in FIG. First, before the start of photometry, the switch 8 and the switch 12 are turned on. At this time, the voltage VREF of the reference voltage source 9 is output to the output VOUT of the buffer circuit 10.

  Then, the switch 8 and the switch 12 are switched from ON to OFF according to the instruction to start the first photometry 1. As a result, integration is started. If there is no change in the photocurrent Ipd1 by this time, the voltage VOUT output to the output terminal of the buffer circuit 10 is expressed by the following equation (4).

VOUT = VREF + (Ipd1 × t) / C1 (4)
Here, Ipd1 is the photocurrent of the photodiode 1, t is the integration time, and C1 is the capacitance value of the integration capacitor 7.

  Next, the switch 8 and the switch 12 are switched from OFF to ON according to an instruction to end the first integral photometry 1. Simultaneously with this timing, when the photocurrent Ipd1 from the photodiode 1 sharply decreases, the voltage at the inverting terminal of the operational amplifier circuit 5 fluctuates, charging / discharging occurs in the parasitic capacitance Cpd and the phase compensation capacitance Cop. Is added to the output current IGOUT with a time constant. This time constant becomes longer as the current flowing to the source current of the transistor Q1 becomes smaller. If the output current IGOUT remains until the next integral photometry 2 operation, this current component becomes an integration error factor at the next photometry. However, in the present embodiment, the time constant is sufficiently settled from the current source 11 through the switch 12 until the start of the next integral photometry 2, and a current as small as possible is applied to the inverting terminal of the operational amplifier circuit 5. Apply. As a result, the influence of the charging / discharging current of the parasitic capacitance Cpd and the phase compensation capacitance Cop has already disappeared when the switches 8 and 12 are switched from ON to OFF in response to the second metering start instruction, and the integration does not deteriorate the metering characteristics. Can be realized.

  Next, Example 3 will be described. FIG. 4 is a circuit configuration diagram showing Embodiment 3 of the photometry circuit according to the present invention. This embodiment corresponds to the invention according to claim 3. The basic configuration of the third embodiment shown in FIG. 4 is the same as that of the second embodiment shown in FIG. The difference from the second embodiment shown in FIG. 3 is that a switch 13 is connected between the connection portion between the anode of the photodiode 1 and the source terminal of the Pch-MOS transistor Q1 and the inverting terminal of the operational amplifier circuit 5. When the switch 12 is ON, the switches 13 are operated alternately such that the switch 13 is OFF. The operational effect of the photometric circuit configured in this way is the same as that of the second embodiment shown in FIG.

  Next, Example 4 will be described. FIG. 5 is a circuit configuration diagram showing Embodiment 4 of the photometry circuit according to the present invention. This embodiment corresponds to the invention according to claim 4.

  The back gate of the Pch-MOS transistor Q1 in the bias setting unit 3 of the photometry circuit is connected to the power supply VCC1 so that a minute substrate bias current (leakage current) Ibgq1 flows. The substrate bias current Ipgq1 becomes a current value at a level that cannot be ignored by the current handled by the photometry circuit when the temperature rises. Therefore, in the photometric circuit according to the second embodiment shown in FIG. 3, the substrate bias current Ibgq1 of the transistor Q1 is added to the output current IGOUT and flows to the integrating capacitor 7 when the temperature rises, and the photometric characteristics are deteriorated. In order to reduce the deterioration of the photometric characteristic, in this embodiment, as shown in FIG. 5, the Pch-MOS in which the source terminal and the gate terminal are connected to the power supply VCC1 in the circuit configuration of the embodiment 2 shown in FIG. A substrate bias current cancel circuit 15 including a transistor Q3 and a current mirror circuit 14 having an input terminal connected to the drain terminal of the transistor Q3 and an output terminal connected to the drain terminal of the transistor Q1 is added.

  Next, the operation of the photometry circuit configured as described above will be described. Considering the substrate bias currents Ibgq1 and Ibgq3 of the transistors Q1 and Q3, the voltage VOUT output to the output terminal of the buffer circuit 10 of the integration output unit 2 is expressed by the following equation (5).

VOUT = VREF + [(Ipd1 + Ibgq1−Ibgq3) × t] / C1 (5)
Here, assuming that the transistors Q1 and Q3 have the same size and the input / output current ratio of the current mirror circuit 14 is 1: 1, the substrate bias currents Ibgq1 and Ibgq3 of the transistors Q1 and Q3 are substantially equal. Therefore, equation (5) becomes
VOUT = VREF + (Ipd1 × t) / C1 (6)
Thus, an integral-type photometric circuit that is not affected by the substrate bias current of the transistor Q1 constituting the bias setting unit 3 and that does not deteriorate the photometric characteristics can be realized.

  Next, Example 5 will be described. FIG. 6 is a circuit configuration diagram showing Embodiment 5 of the photometry circuit according to the present invention. This embodiment corresponds to the invention according to claim 5. In this embodiment, as shown in FIG. 6, the source and gate terminals of a Pch-MOS transistor Q3 are connected to a power supply VCC1 in the circuit configuration of the photometry circuit of the embodiment 2 shown in FIG. The drain terminal is connected to the integration capacitor 16 and one terminal of the switch 17, the other terminal of the switch 17 is connected to the reference voltage source 9, and the substrate of the transistor Q3 is connected to the connection point between the transistor Q3 and the integration capacitor 16. A buffer circuit 18 is connected to take out a voltage obtained by integrating the bias current Ibgq3 by the integration capacitor 16 as an output voltage. The output of the buffer circuit 18 and the output of the buffer circuit 10 of the integration output unit 2 are input, and the buffer A substrate bias current capacitor comprising an arithmetic circuit 19 for outputting a signal obtained by canceling the substrate bias current of the transistor Q1 from the output of the circuit 10. It is obtained by adding a cell circuit 20.

  Next, the operation of the photometry circuit configured as described above will be described. The photometry circuit of this embodiment also reduces the degradation of photometry characteristics due to the substrate bias current Ibgq1 of the transistor Q1 of the bias setting unit 3, and considering the substrate bias currents Ibgq1 and Ibgq3 of the respective transistors Q1 and Q3, The voltage VOUT output to the output terminal of the buffer circuit 10 of the integration output unit 2 is expressed by the following equation (7).

VOUT = VREF + [(Ipd1 + Ibgq1) × t] / C1 (7)
Next, the voltage VOUT2 output to the output terminal of the buffer circuit 18 of the substrate bias current cancel circuit 20 is expressed by the following equation (8). However, C2 is the capacitance value of the integration capacitor 16.

VOUT2 = VREF + (Ibgq3 × t) / C2 (8)
If the transistors Q1 and Q3 have the same size, the substrate bias currents Ibgq1 and Ibgq3 of the transistors Q1 and Q3 are substantially equal. When the sizes of the integrating capacitors 7 and 16 are the same and the outputs of the respective buffer circuits 10 and 18 are calculated by the calculation circuit 19, the following equation (9) is obtained.

VOUT−VOUT2 = (Ipd1 × t) / C1 (9)
Thereby, it is possible to realize an integral-type photometric circuit that is not affected by the substrate bias current of the transistor Q1 constituting the bias setting unit 3 and does not deteriorate the photometric characteristics.

  Next, Example 6 will be described. FIG. 7 is a circuit configuration diagram showing Embodiment 6 of the photometric circuit according to the present invention. This embodiment corresponds to the invention according to claim 6. As shown in FIG. 7, in this embodiment, a photodiode 1 whose cathode is connected to a power supply VCC1, an anode of the photodiode 1 is connected to an inverting terminal of an operational amplifier circuit 5, and a source terminal of a Pch-MOS transistor Q1, The non-inverting terminal of the operational amplifier circuit 5 is connected to the power source 6, the bias setting unit 3 is connected to the gate terminal of the Pch-MOS transistor Q1 and the output terminal of the operational amplifier circuit 5, and the drain terminal of the transistor Q1 is integrated. The capacitor 7 is connected to one terminal of the switch 8, the other terminal of the switch 8 is connected to the reference voltage source 9, and the output current IGOUT of the bias setting unit 3 is connected to the connection point between the transistor Q1 and the integrating capacitor 7. An integration output unit 2 to which a buffer circuit 10 for extracting the voltage integrated by the integration capacitor 7 as an output voltage is connected; and a Pch-MOS transistor A current mirror circuit 14 having a source terminal and a gate terminal of the transistor Q3 connected to the power supply VCC1, an input terminal connected to the drain terminal of the transistor Q3, and an output terminal connected to the drain terminal of the transistor Q1 of the bias setting unit 3; The substrate bias current cancel circuit 15 provided constitutes a photometric circuit.

  Next, the operation of the photometry circuit configured as described above will be described. Considering the substrate bias currents Ibgq1 and Ibgq3 of the transistors Q1 and Q3, the voltage VOUT output to the output terminal of the buffer circuit 10 is expressed by the following equation (10).

VOUT = VREF + ((Ipd1 + Ibgq1-Ibgq3) × t) / C1 (10)
Here, assuming that the transistors Q1 and Q3 have the same size and the input / output current ratio of the current mirror circuit 14 is 1: 1, the substrate bias currents Ibgq1 and Ibgq3 of the transistors Q1 and Q3 are substantially equal. Therefore, equation (10) becomes
VOUT = VREF + (Ipd1 × t) / C1 (11)
Thus, an integral-type photometric circuit that is not affected by the substrate bias current of the transistor Q1 constituting the bias setting unit 3 and that does not deteriorate the photometric characteristics can be realized.

  Next, Example 7 will be described. FIG. 8 is a circuit configuration diagram showing Embodiment 7 of the photometric circuit according to the present invention. This embodiment corresponds to the invention according to claim 7. As shown in FIG. 8, in this embodiment, a photodiode 1 whose cathode is connected to a power supply VCC1, an anode of the photodiode 1 is connected to an inverting terminal of an operational amplifier circuit 5, and a source terminal of a Pch-MOS transistor Q1. The non-inverting terminal of the operational amplifier circuit 5 is connected to the power source 6, the bias setting unit 3 is connected to the gate terminal of the Pch-MOS transistor Q1 and the output terminal of the operational amplifier circuit 5, and the drain terminal of the transistor Q1 is integrated. The capacitor 7 is connected to one terminal of the switch 8, the other terminal of the switch 8 is connected to the reference voltage source 9, and the output current IGOUT of the bias setting unit 3 is connected to the connection point between the transistor Q1 and the integrating capacitor 7. An integration output unit 2 to which a buffer circuit 10 for extracting the voltage integrated by the integration capacitor 7 as an output voltage is connected; and a Pch-MOS The source terminal and gate terminal of the transistor Q3 are connected to the power supply VCC1, the drain terminal of the transistor Q3 is connected to one terminal of the integrating capacitor 16 and the switch 17, and the other terminal of the switch 17 is connected to the reference voltage source 9. A buffer circuit 18 is connected to a connection point between the transistor Q3 and the integration capacitor 16 to take out a voltage obtained by integrating the substrate bias current Ibgq3 of the transistor Q3 by the integration capacitor 16 as an output voltage. And an output of the buffer circuit 10 of the integral output unit 2 and an arithmetic circuit 19 that outputs a signal obtained by canceling the substrate bias current of the transistor Q1 from the output of the buffer circuit 10. And constitutes a photometric circuit.

  Next, the operation of the photometry circuit configured as described above will be described. The photometry circuit of this embodiment also reduces the degradation of photometry characteristics due to the substrate bias current Ibgq1 of the transistor Q1 constituting the bias setting unit 3, and considers the substrate bias currents Ibgq1 and Ibgq3 of the respective transistors Q1 and Q3. Then, the voltage VOUT output to the output terminal of the buffer circuit 10 of the integral output unit 2 is expressed by the following equation (12).

VOUT = VREF + [(Ipd1 + Ibgq1) × t] / C1 (12)
Next, the voltage VOUT2 output to the output terminal of the buffer circuit 18 constituting the substrate bias current cancel circuit 20 is expressed by the following equation (13).

VOUT2 = VREF + (Ibgq3 × t) / C2 (13)
If the transistors Q1 and Q3 have the same size, the substrate bias currents Ibgq1 and Ibgq3 of the transistors Q1 and Q3 are substantially equal. Further, assuming that the sizes of the integration capacitors 7 and 16 are the same and the outputs of the respective buffer circuits 10 and 18 are calculated by the calculation circuit 19,
VOUT−VOUT2 = VREF + (Ipd1 × t) / C1 (14)
Thus, an integral-type photometric circuit that is not affected by the substrate bias current of the transistor Q1 constituting the bias setting unit 3 and that does not deteriorate the photometric characteristics can be realized.

  Next, Example 8 will be described. In this embodiment, each of the photometry circuits is arranged on the same semiconductor substrate in the first to seventh embodiments shown in FIGS. 1 and 3 to 8. This corresponds to the invention according to claim 8.

  In the photometric circuits shown in the first to seventh embodiments, even when the anode or cathode of the photodiode is directly connected to the highest potential on the semiconductor substrate, the current from the photodiode is integrated with the integration capacitance of the integration output unit. It is possible to integrate. Therefore, the photodiode and the integration circuit can be arranged on the same semiconductor substrate. Further, it can cope with a plurality of photodiodes whose anodes or cathodes are commonly connected to a semiconductor substrate, such as a divided sensor used in a camera or the like. Therefore, a plurality of photometric circuits can be realized on the same semiconductor substrate even when such a restricted photodiode is used.

  Thus, by forming all the circuits constituting the photometric circuit on the same semiconductor substrate, it is possible to contribute to the cost reduction of the IC. In Examples 1 to 7, an example in which the photocurrent is obtained from the anode of the photodiode has been described. However, the same effect can be obtained when the photocurrent is obtained from the cathode.

  In the above embodiment, the power supply 6 is connected to the non-inverting terminal of the operational amplifier circuit 5 constituting the bias setting unit 3. However, the non-inverting terminal may be connected to the power supply VCC1. .

It is a circuit block diagram which shows Example 1 of the photometry circuit based on this invention. FIG. 3 is a photometric timing diagram for explaining the operation of the first embodiment shown in FIG. 1. It is a circuit block diagram which shows Example 2 of this invention. It is a circuit block diagram which shows Example 3 of this invention. It is a circuit block diagram which shows Example 4 of this invention. It is a circuit block diagram which shows Example 5 of this invention. It is a circuit block diagram which shows Example 6 of this invention. It is a circuit block diagram which shows Example 7 of this invention. It is a circuit block diagram which shows the structural example of the conventional photometry circuit. It is a circuit block diagram which shows the other structural example of the conventional photometry circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Photodiode 2 Integration output part 3 Bias setting part 4 Current application part 5 Operational amplifier circuit 6 Power supply 7 Integration capacity 8 Switch 9 Reference voltage source
10 Buffer circuit
11 Current source
12 switch
13 switch
14 Current mirror circuit
15 Substrate bias current cancel circuit
16 integral capacity
17 switch
18 Buffer circuit
19 Arithmetic circuit
20 Substrate bias current cancel circuit

Claims (5)

A photodiode with one terminal connected to one power source;
In order to set the bias of the photodiode substantially constant , the first and second terminals, and a control terminal for controlling a current from the first terminal to the second terminal, the first terminal A first semiconductor element having a terminal connected to the other terminal of the photodiode, an inverting input terminal to the other terminal of the photodiode, a non-inverting input terminal to the power supply or another power supply, and an output terminal to the power supply A bias setting unit including operational amplifier circuits respectively connected to control terminals of the first semiconductor element ;
Is connected to the inverting input terminal of the operational amplifier circuit of the bias setting portion, when the photocurrent flowing through the photodiode is reduced, a current applying unit for applying a current from current source to the bias setting portion,
An integrating output unit that integrates an output current from the photodiode set to the substantially constant bias and outputs a signal corresponding to the amount of light received by the photodiode; .   The photometry circuit according to claim 1, wherein the current application unit applies the current from the current source between photometry and the next photometry. The photodiode, the one terminal of the anode or the cathode terminal of that is connected to one of the power supply, the current applying section, first and second terminals, and said second terminal from said first terminal has a control terminal for controlling the current to, is connected to the control terminal to a control terminal of the first semiconductor, the second semiconductor device to which the second terminal is connected to the other power supply, one end a current source connected to the first terminal of the other end said one of the power source and the second semiconductor element, the one terminal first terminal of the other end and the second semiconductor element of the current source And a switch having the other terminal connected to the inverting input terminal of the operational amplifier circuit, wherein the integration output unit is connected to a second terminal of the first semiconductor element. A capacitance and a voltage integrated by the first integration capacitor, Photometric circuit according to claim 2 in which diode is characterized in that it and an output circuit for outputting a signal corresponding to the amount of light received. The photometric circuit according to claim 3 , wherein the bias setting unit further includes a switch for connecting the inverting input terminal of the operational amplifier to the other terminal of the photodiode. In photometric circuit according to any one of claims 1 to 4, the photometric circuit each component is characterized in that it is formed on the same semiconductor substrate.

Images