JP4459006B2 - Liquid crystal display device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a liquid crystal display device used in a display unit of a television receiver or an electronic device and a method for manufacturing the same, and in particular, a liquid crystal display device that gives a pretilt angle to liquid crystal by polymerizing a polymerizable component (material) mixed in the liquid crystal. And a manufacturing method thereof.

  The liquid crystal display device has two substrates and a liquid crystal sealed between the two substrates. In a liquid crystal display device, optical switching is performed by electrical stimulation using the electro-optical anisotropy of liquid crystal. A predetermined voltage is applied to the liquid crystal layer to control the tilt angle of the liquid crystal molecules, thereby changing the direction of the axis of refractive index anisotropy of the liquid crystal molecules. By utilizing the optical rotation and birefringence generated thereby, the light transmittance is changed, and the brightness of each pixel of the liquid crystal display panel is controlled.

  In a liquid crystal display device, it is very important to control the arrangement of liquid crystal molecules when no voltage is applied. If the initial alignment of the liquid crystal molecules is not stable, the tilt direction of the liquid crystal molecules becomes unstable when a voltage is applied to the liquid crystal, and as a result, the direction of the axis of refractive index anisotropy cannot be controlled. . Examples of a method for controlling the alignment of liquid crystal molecules include a method for controlling the initial formation angle (pretilt angle) between the alignment film and the liquid crystal, and a method for controlling a lateral electric field formed between the bus line and the pixel electrode. It is done. Here, the pretilt angle is an inclination angle of the liquid crystal molecules from the substrate surface when no voltage is applied to the liquid crystal layer. That is, “the pretilt angle is decreased” means that the tilt angle from the complete vertical alignment is increased, that is, closer to the horizontal alignment.

  Even in a liquid crystal display device using a liquid crystal material containing a polymerizable component such as a monomer or an oligomer (hereinafter abbreviated as a monomer), it is important to control the arrangement of liquid crystal molecules in the state where no voltage is applied. In particular, when the initial alignment state of the liquid crystal molecules is controlled by polymerizing the monomer in a state where a voltage is applied to the liquid crystal, the voltage application method at the time of polymerization is important. If the voltage at the time of polymerization is different, a difference occurs in the pretilt angle of the liquid crystal molecules formed in the initial stage, so that the transmittance characteristics of the liquid crystal display device are different.

  As the liquid crystal display device, a simple matrix type and an active matrix type are known. In recent years, active matrix liquid crystal display devices using thin film transistors (TFTs) have become mainstream due to demands for higher definition of display screens.

  FIG. 8 schematically shows a configuration example of an active matrix type liquid crystal display device. As shown in FIG. 8, in the liquid crystal display device 101, a plurality (four in FIG. 8) of gate bus lines 107a, 107b, 107c, 107d extending in the left-right direction in the drawing are formed on the TFT substrate in parallel with each other. ing. One ends of the gate bus lines 107a to 107d are connected to a gate bus line driving circuit 127 that drives the gate bus lines 107a to 107d. A plurality of (four in FIG. 8) drain bus lines 109a, 109b, 109c, and 109d extending in the vertical direction in the figure are formed in parallel with each other so as to intersect the gate bus lines 107a to 107d via an insulating film. . One ends of the drain bus lines 109a to 109d are connected to a drain bus line drive circuit 129 that drives the drain bus lines 109a to 109d.

  TFTs 111 are respectively formed in the vicinity of the intersection positions of the gate bus lines 107a to 107d and the drain bus lines 109a to 109d. The gate electrode of each TFT 111 is connected to the gate bus lines 107a to 107d, and the drain electrode is connected to the drain bus lines 109a to 109d. The source electrode is connected to the pixel electrode 113 formed for each pixel.

  A plurality (four in FIG. 8) of storage capacitor bus lines 115a, 115b, 115c, and 115d extending in parallel with the gate bus lines 107a to 107d are formed so as to intersect the drain bus lines 109a to 109d via an insulating film. ing. The storage capacitor bus lines 115a to 115d form a storage capacitor for each pixel with the pixel electrode 113. The storage capacitor bus lines 115a to 115d serve as one electrode of the storage capacitor, and the pixel electrode 113 serves as the other electrode. One end of each storage capacitor bus line 115a to 115d is electrically connected to one common storage capacitor line 117. A common storage capacitor terminal 119 is disposed at one end of the common storage capacitor wiring 117. A predetermined voltage Vcs can be applied to the common storage capacitor line 117 and the storage capacitor bus lines 115 a to 115 d via the common storage capacitor terminal 119.

  A common electrode 121 is formed on almost the entire surface of the counter substrate. The common electrode 121 and the pixel electrode 113 form a liquid crystal capacitance for each pixel. The common electrode 121 serves as one electrode of the liquid crystal capacitor, and the pixel electrode 113 serves as the other electrode. A common electrode terminal 123 is connected to one end of the common electrode 121. A predetermined voltage Vc can be applied to the common electrode 121 via the common electrode terminal 123. The other end of the common electrode 121 is electrically connected to the other end of the common storage capacitor wiring 117 via a connection wiring 125.

  In the manufacturing stage of the liquid crystal display device 101, a voltage Vc is applied to the common electrode 121, a voltage that always turns on the TFT 111 is applied to the gate bus lines 107a to 107d, and a desired voltage is applied to the drain bus lines 109a to 109d. Then, while applying a voltage to the liquid crystal in the relationship between the pixel electrode 113 and the common electrode 121, the monomer mixed in the liquid crystal is polymerized by irradiating light.

  However, as indicated by a cross in FIG. 9, for example, when the drain bus line 109 a is disconnected and a line defect occurs, in FIG. 9, a voltage is applied to the drain bus line 109 a ′ located below the disconnected portion. Is no longer applied.

  Therefore, a desired voltage is not applied to the liquid crystal of the pixel related to the drain bus line 109a ', and the monomer is polymerized in a state where the liquid crystal cannot be driven sufficiently. Accordingly, the pretilt angle of the liquid crystal in the pixel region connected to the drain bus line 109a ′ is different from that in the other pixel regions. Therefore, when the liquid crystal display device 101 is used as a display unit, the brightness of only the portion is different. have. Further, when the drain bus lines 109a to 109d are short-circuited to the gate bus lines 107a to 107d and the like, it is difficult to apply a desired voltage to the short-circuited drain bus lines 109a to 109d. There is a problem that the brightness differs only in the pixel area.

  Patent Document 1 discloses an active matrix liquid crystal display device that can solve this problem. In the liquid crystal display device, a voltage applied to the liquid crystal when the monomer is polymerized is generated based on an alternating voltage applied between the common electrode and the storage capacitor bus line. For this reason, unlike the liquid crystal display device 101, the liquid crystal display device disclosed in Patent Document 1 uses a common storage capacitor wiring from a common storage capacitor wiring in a process of polymerizing monomers to form a polymer (polymer formation process). It is necessary to open it electrically. However, except for this, the liquid crystal display device disclosed in Patent Document 1 may have the same configuration as the liquid crystal display device 101. For example, since the liquid crystal display device 101 can electrically disconnect the common electrode 121 from the common storage capacitor wiring 117 by cutting the connection wiring 125, the above-described problem can be solved in the same manner as the liquid crystal display device of Patent Document 1. it can.

  FIG. 10 shows an equivalent circuit of the liquid crystal display device 101 in which the connection wiring 125 is cut and the common electrode 121 is electrically disconnected from the common storage capacitor wiring 117. FIG. 10 shows an equivalent circuit of four pixels in two rows and two columns among a plurality of formed pixels. As shown in FIG. 10, the TFT 111a is formed at the intersection of the gate bus line 107a and the drain bus line 109a. The gate electrode (G) of the TFT 111a is connected to the gate bus line 107a, and the drain electrode (D) is connected to the drain bus line 109a. The source electrode (S) is connected to the pixel electrode 113a.

  The pixel electrode 113a is one electrode of the liquid crystal capacitor Clc101 and one electrode of the storage capacitor Cs101. The other electrode of the liquid crystal capacitor Clc 101 is a common electrode 121. The other electrode of the storage capacitor Cs101 is a storage capacitor bus line 115a.

  The TFT 111b is formed at the intersection of the gate bus line 107a and the drain bus line 109b. The gate electrode (G) of the TFT 111b is connected to the gate bus line 107a, and the drain electrode (D) is connected to the drain bus line 109b. The source electrode (S) is connected to the pixel electrode 113b. The pixel electrode 113b is one electrode of the liquid crystal capacitor Clc102 and one electrode of the storage capacitor Cs102. The other electrode of the liquid crystal capacitor Clc 102 is a common electrode 121. The other electrode of the storage capacitor Cs102 is a storage capacitor bus line 115a.

  The TFT 111c is formed at the intersection of the gate bus line 107b and the drain bus line 109a. The gate electrode (G) of the TFT 111c is connected to the gate bus line 107b, and the drain electrode (D) is connected to the drain bus line 109a. The source electrode (S) is connected to the pixel electrode 113c. The pixel electrode 113c is one electrode of the liquid crystal capacitor Clc103 and one electrode of the storage capacitor Cs103. The other electrode of the liquid crystal capacitor Clc 103 is a common electrode 121. The other electrode of the storage capacitor Cs103 is the storage capacitor bus line 115b.

  The TFT 111d is formed at the intersection of the gate bus line 107b and the drain bus line 109b. The gate electrode (G) of the TFT 111d is connected to the gate bus line 107b, and the drain electrode (D) is connected to the drain bus line 109b. The source electrode (S) is connected to the pixel electrode 113d. The pixel electrode 113d serves as one electrode of the liquid crystal capacitor Clc104 and also serves as one electrode of the storage capacitor Cs104. The other electrode of the liquid crystal capacitor Clc 104 is a common electrode 121. The other electrode of the storage capacitor Cs104 is the storage capacitor bus line 115b.

Each pixel is formed with a circuit in which a liquid crystal capacitor Clc and a storage capacitor Cs are coupled in series, each having a common electrode terminal 123 and a common storage capacitor terminal 119 at both ends. When an AC voltage Va having a voltage value of Va is applied between the common electrode 121 and the storage capacitor bus lines 115a and 115b via the common electrode terminal 123 and the common storage capacitor terminal 119, the liquid crystal capacitors Clc101 to Clc104 have the following: A voltage Vlc represented by the following formula is applied.
Vlc = {Cs / (Clc + Cs)} × Va (1)
In Expression (1), Clc represents each capacitance value of the liquid crystal capacitors Clc101 to Clc104, and Cs represents each capacitance value of the storage capacitors Cs101 to Cs104. Note that the voltage applied between the common electrode terminal 123 and the common storage capacitor terminal 119 may be a DC voltage.

  As shown in Equation (1), the voltage Vlc applied to the liquid crystal depends on the capacitance values Clc and Cs of the liquid crystal capacitors Clc101 to Clc104 and the storage capacitors Cs101 to Cs104, and is applied to the drain bus lines 109a and 109b. It does not depend on voltage. Therefore, almost the same voltage Vlc can be applied to the liquid crystal in each pixel region regardless of whether the drain bus lines 109a and 109b are disconnected or short-circuited.

FIG. 11 shows a part of an equivalent circuit of the liquid crystal display device 201 having repair wirings 135a and 135b for repairing the disconnection defect of the drain bus lines 109a and 109b. FIG. 11 shows an equivalent circuit of four pixels in 2 rows and 2 columns, as in FIG. As shown in FIG. 11, the repair wirings 135a and 135b extend substantially in parallel to the gate bus lines 107a and 107b, and are formed on the TFT substrate with the gate bus lines 107a and 107b interposed therebetween. The repair wirings 135a and 135b are electrically connected by another repair wiring formed, for example, in the gate bus line drive circuit 127 (not shown in FIG. 11) during actual drive display. The liquid crystal display device 201 has a pixel configuration similar to that of the liquid crystal display device 101. Therefore, the liquid crystal display device 201 can also apply substantially the same voltage Vlc to the liquid crystal in each pixel region when the monomers are polymerized, regardless of whether the drain bus lines 109a and 109b are disconnected or short-circuited.
Japanese Patent Laid-Open No. 2003-177408

  The liquid crystal display devices 101 and 201 can generate the voltage Vlc applied to the liquid crystal by the alternating voltage Va applied between the common electrode terminal 123 and the common storage capacitor terminal 119. Therefore, the liquid crystal display devices 101 and 201 can generate the voltage Vlc even in a floating state where a predetermined voltage is not applied to both bus lines 107a, 107b, 109a, and 109b. However, if both bus lines 107a, 107b, 109a, and 109b are in a floating state, there is a problem that the following problems (1) to (5) cannot be addressed.

(1) Problem due to short circuit defect between pixel electrode and storage capacitor bus line (2) Problem due to short circuit defect between pixel electrode and common electrode (3) Problem due to short circuit defect between gate bus line and drain bus line (4) Repair Caused by repairing the disconnection defect of the drain bus line using the wiring for wiring (5) Problem caused by the short-circuit defect between the drain bus line and the common electrode

  As indicated by A in FIG. 10, when the pixel electrode 113c and the storage capacitor bus line 115b are short-circuited (problem (1)), the potential of the pixel electrode 113c becomes substantially equal to the potential of the storage capacitor bus line 115b. . For this reason, the AC voltage Va applied between the common electrode terminal 123 and the common storage capacitor terminal 119 is applied to the liquid crystal capacitor Clc 103. Therefore, the desired voltage Vlc determined by the ratio of the capacitance values Clc and Cs as shown in the equation (1) is not applied to the liquid crystal capacitor Clc 103, and the pretilt angle of the liquid crystal molecules is changed to other pixel regions when the monomer is polymerized. It will be different. For this reason, when the liquid crystal display devices 101 and 201 are used as a display unit, only the relevant part is visually recognized as a display defect having a line defect shape with different brightness.

  In addition, since the AC voltage Va is applied to the storage capacitor bus line 115b, the potential of the pixel electrode 113c may be lower than the potential of the pixel electrodes 113a, 113b, and 113d that are not short-circuited. In this case, since the voltage (gate-source voltage) between the gate electrode (G) and the source electrode (S) of the TFT 111c increases, a weak leakage current flows from the pixel electrode 113c toward the drain bus line 109a. Will flow.

  The potential of the drain bus line 109a in the floating state is a capacitance ratio between the coupling capacitor Cps101 generated between the storage capacitor bus lines 115a and 115b intersecting the drain bus line 109a and the coupling capacitor Cpc101 generated between the common electrode 121. Is maintained at a predetermined potential. Since the capacitance values of the coupling capacitance Cps101 and the coupling capacitance Cpc101 are relatively small, the potential of the drain bus line 109a may fluctuate when a leak current flows through the TFT 111c. For this reason, the potential difference between the drain bus line 109a and the gate bus line 107a varies. As a result, the voltage (gate-drain voltage) between the gate electrode (G) and the drain electrode (D) of the TFT 111a fluctuates, and a leak current may flow through the TFT 111a. When the leak current flows, the potential of the pixel electrode 113a fluctuates, and the voltage Vlc applied to the liquid crystal capacitor Clc101 when polymerizing the monomer is different from the desired voltage Vlc.

  Thus, when a short-circuit defect occurs between one pixel electrode and the storage capacitor bus line, the potential of the other pixel electrode connected via the TFT to the drain bus line to which the pixel electrode is connected fluctuates. End up. Accordingly, in all the pixel regions connected to the drain bus line, the pretilt angle of the liquid crystal molecules is different from the other pixel regions. For this reason, when the liquid crystal display devices 101 and 201 are used as a display unit, only the portion has different brightness and is visually recognized as a display defect having a line defect.

  As indicated by B in FIG. 10, when the pixel electrode 113c and the common electrode 121 are short-circuited (problem (2)), a leak current flows through the TFT 111c for the same reason as the problem (1) above. . For this reason, the potential of the drain bus line 109a varies, and a leak current flows through the TFT 111a. As a result, the potential of the pixel electrode 113a varies. Therefore, in all the pixel regions connected to the drain bus line 109a, the pretilt angle of the liquid crystal molecules is different from that of the other pixel regions, and only the portion has a different brightness, which is visually recognized as a line defect-like display defect.

  As indicated by C in FIG. 10, when the gate bus line 107b and the drain bus line 109a are short-circuited (problem (3)), the potentials of both the bus lines 107b and 109a become substantially equal. For this reason, the potential of the drain bus line 109a varies from the potential before the short circuit. When the potential difference between the gate bus line 107a and the drain bus line 109a varies due to the potential variation of the drain bus line 109a, the gate-drain voltage of the TFT 111a varies, and thus a leakage current may flow through the TFT 111a. As a result, the potential of the pixel electrode 113a varies, and the desired voltage Vlc is not applied to the liquid crystal capacitor Clc101. Therefore, as in the case of the above problems (1) and (2), the pretilt angle of the liquid crystal molecules is different from the other pixel regions in all the pixel regions connected to the drain bus line 109a when the monomer is polymerized. End up. As a result, during actual drive display, only the relevant portions have different brightness and are visually recognized as line-defect-like display unevenness.

  As shown in FIG. 11, when a disconnection defect (x mark) occurs in the drain bus line 109b, the drain bus line 109b is repaired as shown by D and D 'in the drawing in order to repair the drain bus line 109b. The intersections with the wiring lines 135a and 135b are connected. When the drain bus line 109b is connected to the repair wirings 135a and 135b, the potential may fluctuate due to the influence of the potential of the repair wirings 135a and 135b. In this case, since the gate-drain voltage of the TFTs 111b and 111d fluctuates, a leak current flows through the TFTs 111b and 111d, and the potentials of the pixel electrodes 113b and 113d fluctuate. In this case, in all the pixel regions connected to the drain bus line 109b, the pretilt angle of the liquid crystal molecules is different from the other pixel regions when the monomers are polymerized. As a result, during actual drive display, only the relevant portions have different brightness and are visually recognized as line-defect-like display unevenness.

  As indicated by E in FIG. 11, when the drain bus line 109a and the common electrode 121 are short-circuited (problem (5)), the potential of the drain bus line 109a is equal to the potential applied to the common electrode 121. Become. Therefore, the potential difference between the drain bus line 109a and the gate bus lines 107a and 107b varies. If this happens, the gate-drain voltages of the TFTs 111a and 111c may fluctuate, and a leakage current may flow through the TFTs 111a and 111c. As a result, in all the pixel regions connected to the drain bus line 109a, the pretilt angle of the liquid crystal molecules is different from the other pixel regions when the monomers are polymerized. As a result, during actual drive display, only the relevant portions have different brightness and are visually recognized as line-defect-like display unevenness.

  As shown in Patent Document 1, a predetermined DC voltage is applied to a gate bus line, a drain bus line, a storage capacitor bus line, and a repair wiring, and all wirings on the TFT substrate are set to the same potential in advance. In other words, since it can be considered that all the wirings are short-circuited, even if a short-circuit defect occurs in a predetermined place, the influence of the short-circuit defect can be prevented.

  If this method is used, the problems shown in (1) to (4) can be solved. For this purpose, a circuit for applying a predetermined DC voltage to all the wirings on the TFT substrate is required. . However, a process for connecting the circuit to the liquid crystal display panel is required, and the polymerizing process takes a long time, and the manufacturing efficiency of the liquid crystal display devices 101 and 201 is lowered.

  In the method of applying a predetermined voltage to all the wirings on the TFT substrate, the drain bus line 109a has the same potential as the storage capacitor bus line 115a. Therefore, when the drain bus line 109a and the common electrode 121 are short-circuited (problem (5)), the common electrode 121 has the same potential as the drain bus line 109a and at the same time the storage capacitor bus line 115a. Accordingly, the voltage of the alternating voltage shown in the equation (1) becomes almost zero, so the voltage Vlc becomes almost zero, and the desired voltage Vlc cannot be applied to the liquid crystal.

  As described above, when all the wirings such as the gate bus lines 107a and 107b and the drain bus lines 109a and 109b are set in a floating state, the time for inputting voltage to the wirings can be saved, thereby simplifying the polymerization process. Can do. However, if the drain bus lines 109a and 109b are short-circuited with the common electrode 121, the storage capacitor bus line 115a, etc., it is impossible to apply a desired voltage Vlc to the liquid crystal when the monomer is polymerized. As a result, the pretilt angle of the liquid crystal molecules formed initially is not formed to a desired angle, and the transmittance characteristics of the liquid crystal display device are different.

  In addition, when a predetermined DC voltage is applied to all the wirings on the TFT substrate in order to remove the influence of a short circuit between the drain bus lines 109a and 109b and the other wirings other than the common electrode 121, a predetermined DC voltage is applied to the wirings. It becomes necessary to apply a voltage, and the manufacturing efficiency of the liquid crystal display devices 101 and 201 decreases due to the longer polymerization time.

  It is an object of the present invention to apply a desired voltage to the liquid crystal when polymerizing a polymerizable component (material) mixed in the liquid crystal, and to control the pretilt angle of liquid crystal molecules that are initially formed to achieve a good display. An object of the present invention is to provide a liquid crystal display device having characteristics and a manufacturing method thereof.

The object is to provide a pair of opposed substrates, a liquid crystal mixed with a polymerizable component sealed between the pair of substrates, and a plurality of gate bus lines formed on one of the pair of substrates. A plurality of drain bus lines intersecting the plurality of gate bus lines through an insulating film, the plurality of gate bus lines, a thin film transistor formed at each intersection of the plurality of drain bus lines, and the thin film transistor Connected to the connected pixel electrode, the first control wiring to which a control signal for controlling switching is input when polymerizing the polymerizable component, and one of the two adjacent drain bus lines A drain electrode; a source electrode connected to the other; and a gate electrode connected to the first control wiring, wherein switching is controlled based on the control signal. The liquid crystal display device characterized by having a first polymer thin film transistor that.
Achieved by:

  According to the present invention, when a polymerizable component (material) mixed in a liquid crystal is polymerized, a desired voltage can be applied to the liquid crystal, and the pretilt angle of liquid crystal molecules formed in the initial stage is controlled to provide a good display. A liquid crystal display device having characteristics can be realized.

[First Embodiment]
A liquid crystal display device according to a first embodiment of the present invention and a method for manufacturing the same will be described with reference to FIGS. First, a schematic configuration of the liquid crystal display device 1 according to the present embodiment will be described with reference to FIGS. FIG. 1 schematically shows a configuration of a liquid crystal display device 1 according to the present embodiment. FIG. 1A shows nine adjacent pixels of 3 rows and 3 columns among a plurality of pixels of m rows and n columns arranged in a matrix. FIG. 1B shows a cross-sectional configuration of the liquid crystal display device 1. FIG. 2 shows an equivalent circuit of two adjacent pixels in 2 rows and 1 column among a plurality of pixels in m rows and n columns.

  As shown in FIG. 1A, the liquid crystal display device 1 includes a plurality of (four in FIG. 1A) gate bus lines 7a, 7b, 7c, and 7d extending in the left-right direction in parallel with each other. It is formed on the TFT substrate 2. One ends of the gate bus lines 7a to 7d are connected to input terminals 8a, 8b, 8c, and 8d, respectively. When the liquid crystal display device 1 is used as a display unit of an electronic device, a gate bus line driving circuit (not shown) for driving a gate bus line is connected to the input terminals 8a to 8d.

  A plurality of (four in FIG. 1 (a)) drain bus lines 9a, 9b, 9c, 9d extending in the vertical direction in the figure intersecting the gate bus lines 7a-7d via an insulating film are formed in parallel with each other. Has been. One ends of the drain bus lines 9a to 9d are connected to the input terminals 10a, 10b, 10c, and 10d, respectively. When the liquid crystal display device 1 is used as a display unit of an electronic device, a drain bus line driving circuit (not shown) for driving the drain bus lines 9a to 9d is connected to the input terminals 10a to 10d.

  Between the adjacent drain bus lines 9a and 9b, a polymerization TFT 29a (first polymerization thin film transistor) is formed which conducts between the drain bus lines 9a and 9b when the monomer mixed in the liquid crystal is polymerized. . As shown in FIG. 2, the drain electrode (D) of the superposition TFT 29a is connected to the drain bus line 9a, and the source electrode (S) is connected to the drain bus line 9b. Further, the gate electrode (G) of the superposition TFT 29 a is connected to the control wiring (first control wiring) 31. A control signal for controlling on / off switching of the superposition TFT 29 a is input to the control wiring 31. The control wiring 31 intersects with the drain bus lines 9a, 9b, 9c via an insulating film and extends in the left-right direction in the drawing. An input terminal 33 to which a control signal is input is connected to one end of the control wiring 31.

  Similarly, between the adjacent drain bus lines 9b and 9c, a polymerization TFT (first polymerization thin film transistor) 29b is formed which conducts between the drain bus lines 9b and 9c when the monomer is polymerized. The drain electrode (D) of the superposition TFT 29b is connected to the drain bus line 9b, the source electrode (S) is connected to the drain bus line 9c, and the gate electrode (G) is connected to the control wiring 31.

  Returning to FIG. 1, a polymerization TFT (first polymerization thin film transistor) 29c is formed between the adjacent drain bus lines 9c and 9d to conduct the drain bus lines 9c and 9d when the monomer is polymerized. ing. The drain electrode of the polymerization TFT 29c is connected to the drain bus line 9c, the source electrode is connected to the drain bus line 9d, and the gate electrode is connected to the control wiring 31. Thereafter, similarly, a polymerization TFT (first polymerization thin film transistor) having the same configuration is formed between adjacent drain bus lines (not shown) formed in parallel with the drain bus lines 9a to 9d. Has been.

  Each gate electrode of a superposition TFT (hereinafter abbreviated as superposition TFTs 29a, 29b, 29c) formed between adjacent drain bus lines is connected to a control wiring 31. On / off of the superposition TFTs 29a, 29b, and 29c can be simultaneously controlled based on a control signal flowing through the control wiring 31. Further, when the monomers are polymerized, the drain bus lines 9a, 9b, and 9c can be connected to each other with a low resistance and conductive by turning on the polymerization TFTs 29a, 29b, and 29c. On the other hand, for example, when the liquid crystal display device 1 is used as a display screen of an electronic device, the drain bus lines 9a, 9b, and 9c are connected with high resistance by turning off the polymerization TFTs 29a, 29b, and 29c. Thus, a non-conductive state can be obtained.

  As shown in FIGS. 1A and 2, a TFT 11a is formed near the intersection of the gate bus line 7a and the drain bus line 9a. As shown in FIG. 2, the gate electrode (G) of the TFT 11a is connected to the gate bus line 7a, and the drain electrode (D) is connected to the drain bus line 9a. The source electrode (S) is connected to the pixel electrode 13a formed in the pixel region.

  A TFT 11b is formed in the vicinity of the intersection of the gate bus line 7b and the drain bus line 9a. The gate electrode (G) of the TFT 11b is connected to the gate bus line 7b, and the drain electrode (D) is connected to the drain bus line 9a. The source electrode (S) is connected to the pixel electrode 13b formed in the pixel region.

  As shown in FIG. 1A, TFTs 11 are also formed in the vicinity of other intersecting positions of the gate bus lines 7a to 7d and the drain bus lines 9a to 9d. The gate electrode of each TFT 11 is connected to the gate bus lines 7a to 7d, and the drain electrode is connected to the drain bus lines 9a to 9d. The source electrode is connected to the pixel electrode 13 formed for each pixel. Similarly, a plurality of gate bus lines (not shown) formed in parallel with both bus lines 7a to 7d and a plurality of drain bus lines (not shown) formed in parallel with the drain bus lines 9a to 9d. A TFT is also formed in the vicinity of the crossing position. A pixel electrode is connected to each TFT.

  Four storage capacitor bus lines 15a, 15b, 15c, 15d extending in parallel with the gate bus lines 7a-7d are formed crossing the drain bus lines 9a-9d via an insulating film. As shown in FIG. 2, a storage capacitor Cs1 is formed by the storage capacitor bus line 15a, the pixel electrode 13a, and an insulating film sandwiched therebetween. Similarly, a storage capacitor Cs2 is formed by the storage capacitor bus line 15b, the pixel electrode 13b, and an insulating film sandwiched therebetween. The storage capacitor formed by the storage capacitor bus line, the pixel electrode, and the insulating film sandwiched between them is formed for each pixel. One end of each storage capacitor bus line 15 a to 15 d is electrically connected to one common storage capacitor line 17. A common storage capacitor terminal 19 is disposed at one end of the common storage capacitor wiring 17. A predetermined voltage Vcs can be applied to the common storage capacitor line 17 and the storage capacitor bus lines 15 a to 15 d via the common storage capacitor terminal 19.

  The repair wirings 35a and 35b extend substantially in parallel to the gate bus lines 7a to 7d, and are formed with the gate bus lines 7a to 7d interposed therebetween. Further, the repair wirings 35a and 35b are formed so as to intersect the drain bus lines 9a to 9d via an insulating film. Connection terminals 37a and 37b are connected to one ends of the repair wirings 35a and 35b, respectively. The connection terminals 37a and 37b are connected to, for example, a repair wiring formed on the gate bus line driving circuit.

  A common electrode 21 is formed on almost the entire surface of the counter substrate. As shown in FIG. 2, a liquid crystal capacitor Clc1 is formed by the common electrode 21, the pixel electrode 13a, and the liquid crystal 45 sandwiched therebetween. A liquid crystal capacitor Clc2 is formed by the common electrode 21, the pixel electrode 13b, and the liquid crystal 45 sandwiched therebetween. Similarly, in each pixel, a liquid crystal capacitor is formed by a common electrode, a pixel electrode, and a liquid crystal sandwiched between them. A common electrode terminal 23 is connected to one end of the common electrode 21. A predetermined voltage Vc can be applied to the common electrode 21 via the common electrode terminal 23. The other end of the common electrode 21 and the other end of the common storage capacitor line 17 are electrically connected via the connection line 125 like the conventional liquid crystal display device 101 after the step of polymerizing the monomer to form a polymer. It may be connected.

  As shown in FIG. 1B, a liquid crystal 45 is sealed between the TFT substrate 2 and the counter substrate 4 bonded together. The liquid crystal 45 is a negative liquid crystal material having a dielectric anisotropy Δε of −3 to −5, and a small amount (0.1 to 1%) of a liquid crystal acrylate material is blended as a polymerizable component. On the glass substrate 39 on the TFT substrate 2 side, the TFT 11 and the pixel electrode 13 are formed. Furthermore, a vertical alignment film 43 that determines the initial alignment state of the liquid crystal molecules is formed on the glass substrate 39. The vertical alignment film 43 is formed of a polyimide material having vertical alignment properties. On the glass substrate 41 on the counter substrate 4 side, a color filter (CF) resin layer 49, a common electrode 21 and a vertical alignment film 47 are formed. Similarly, the vertical alignment film 47 is formed of a polyimide material having vertical alignment. The cell gap between the substrates 2 and 4 is maintained by the spherical spacers 51 dispersed on the TFT substrate 2 or the counter substrate 4.

Each pixel is formed with a circuit in which a liquid crystal capacitor Clc and a storage capacitor Cs are coupled in series, each having a common electrode terminal 23 and a common storage capacitor terminal 19 at both ends. When an alternating voltage Va having a voltage value of Va is applied between the common electrode 21 and the storage capacitor bus lines 15a to 15d via the common electrode terminal 23 and the common storage capacitor terminal 19, the liquid crystal capacitors Clc1 and Clc2 have a conventional structure. Similarly to the liquid crystal display devices 101 and 201, a voltage Vlc represented by the following equation is applied.
Vlc = {Cs / (Clc + Cs)} × Va (1)
In the formula (1), Clc represents each capacitance value such as liquid crystal capacitances Clc1 and Clc2, and Cs represents each capacitance value such as storage capacitors Cs1 and Cs2. Note that the voltage applied between the common electrode terminal 23 and the common storage capacitor terminal 19 may be a DC voltage.

  In the manufacturing process of the liquid crystal display device 1, when light (UV light) is irradiated in the direction of the thick arrow in FIG. 1B with the voltage Vlc applied to the liquid crystal 45, the monomer mixed in the liquid crystal 45 is polymerized. As a result, a polymer is formed. Thereby, a predetermined pretilt angle is obtained as the initial alignment state of the liquid crystal molecules. The pretilt angle becomes smaller as the voltage value applied to the liquid crystal 45 is larger when the polymer is formed.

  When the liquid crystal display device 1 is actually used as a display device, gate pulses with a voltage of, for example, + 25V are sequentially applied to the gate bus lines 7a to 7d at a predetermined timing, and the TFTs 11 are sequentially turned on. In accordance with the timing, a grayscale voltage of, for example, about 0V ± 5V written to a predetermined pixel is applied to the drain bus lines 9a to 9d. The common electrode 21 and the common storage capacitor wiring 17 are electrically connected via a transfer, and for example, a voltage of 0 V is applied.

  As shown in FIG. 2, the drain bus line 9a, the storage capacitor bus lines 15a and 15b, and other storage capacitor bus lines (not shown) (hereinafter abbreviated as storage capacitor bus lines 15a and 15b) and between them. A coupling capacitance Cps1 is formed by the sandwiched insulating films. Further, a coupling capacitor Cpc1 is formed by the drain bus line 9a, the common electrode 21, and the liquid crystal sandwiched therebetween. Similarly, a coupling capacitor Cps2 is formed by the drain bus line 9b, the storage capacitor bus lines 15a and 15b, and the insulating film sandwiched therebetween. Further, a coupling capacitor Cpc2 is formed by the drain bus line 9b, the common electrode 21, and the liquid crystal sandwiched therebetween. Similarly, a coupling capacitor Cps3 is formed by the drain bus line 9c, the storage capacitor bus lines 15a and 15b, and the insulating film sandwiched therebetween. Further, a coupling capacitor Cpc3 is formed by the drain bus line 9c, the common electrode 21, and the liquid crystal sandwiched therebetween.

  By the way, when the superposition TFTs 29a and 29b are turned on, the drain bus line 9a is connected in parallel to the drain bus lines 9b and 9c. For this reason, the coupling capacitors Cps1 to Cps3 formed between the drain bus lines 9a, 9b and 9c and the storage capacitor bus lines 15a and 15b are also connected in parallel. Similarly, the coupling capacitors Cpc1 to Cpc3 formed between the drain bus lines 9a, 9b, and 9c and the common electrode 21 are also connected in parallel. Therefore, when the superposition TFTs 29a and 29b are turned on, the capacitance values of the coupling capacitors Cps1 and Cpc1 formed by the drain bus line 9a between the storage capacitor bus lines 15a and 15b and the common electrode 21, respectively, are capacitances in the off state. It is almost 3 times the value.

  For example, in an XGA type liquid crystal display device, 1024 × 3 = 3072 drain bus lines are formed. When polymerization TFTs are formed between the drain bus lines, by turning on all the polymerization TFTs, one drain bus line is connected between the storage capacitor bus line and the common electrode. The capacitance value of the coupling capacitance formed is 3072 times that of the conventional liquid crystal display device.

Further, the capacitance value of the coupling capacitor Cps1 is Cps, the capacitance value of the coupling capacitor Cpc1 is Cpc, the voltage applied to the storage capacitor bus lines 15a and 15b is Vcs, and the voltage applied to the common electrode 21 is Vc. The potential Vd of the drain bus line 9a in the floating state when the polymerization TFT 29a is off can be expressed as follows.
Vd = {Cpc / (Cps + Cpc)} × (Vc−Vcs) (2)
Equation (2) holds true for the drain bus line when the connected superposition TFT is off.

Here, it is assumed that the capacitance values of the coupling capacitors Cps1 to Cpsn formed by the n drain bus lines with the m storage capacitor bus lines are substantially the same, and the coupling formed with the common electrode 21, respectively. It is assumed that the capacitance values of the capacitors Cpc1 to Cpcn are substantially the same. When the n-1 superposition TFTs formed between the n drain bus lines are turned on, the n drain bus lines are connected in parallel, so that one of the n TFTs in the floating state is connected. The potential Vdn of the drain bus line can be expressed as follows.
Vdn = {(n × Cpc) / (n × Cps + n × Cpc)} × (Vc−Vcs)
= {Cpc / (Cps + Cpc)} × (Vc−Vcs) (3)

  As shown in Expression (3), even if n drain bus lines are connected in parallel, the potential Vdn of each drain bus line is almost the same as the potential Vd in the case of one. Therefore, for example, the potential Vd of the drain bus line 9a in the floating state is maintained at substantially the same potential regardless of whether the polymerization TFTs 29a and 29b are turned on or off.

  As described above, when the polymerization TFTs 29a and 29b are turned on, the magnitude of the potential Vd of the drain bus line 9a in the floating state hardly changes. However, the capacitance values Cps and Cpc of the coupling capacitors Cps1 and Cpc1 formed between the storage capacitor bus lines 15a and 15b and the common electrode 21, respectively, are n times (3 times in FIG. 2). For this reason, it takes time to charge and discharge the coupling capacitance, and the potential Vd of the drain bus line 9a hardly changes.

  By the way, as indicated by A in FIG. 2, when the pixel electrode 13b and the storage capacitor bus line 15b are short-circuited (problem (1)), when the monomer is polymerized, it is applied to the liquid crystal capacitor Clc2. The applied voltage Vlc is substantially equal to the alternating voltage Va applied between the common electrode terminal 23 and the common storage capacitor terminal 19. For this reason, the desired voltage Vlc is not applied to the liquid crystal capacitance Clc2.

  In this case, the potential of the pixel electrode 13 b is substantially equal to the voltage Vcs applied to the common storage capacitor terminal 19. For this reason, when the potential of the pixel electrode 13b becomes lower than the potential determined by the ratio of the capacitance value Cs and the capacitance value Clc, and the gate-source voltage of the TFT 11b increases, the potential from the pixel electrode 13b toward the drain bus line 9a becomes the TFT 11b. A weak leak current flows.

  However, the drain bus line 9a is held at the predetermined potential Vd by the coupling capacitors Cps1 and Cpc1 having a larger capacitance value than the conventional drain bus line 109a by turning on the superposition TFTs 29a and 29b. . For this reason, even if a weak leak current flows from the TFT 11b, the potential variation of the potential Vd of the drain bus line 9a hardly occurs. As a result, the gate-drain voltage of the TFT 11a connected to the drain bus line 9a hardly changes, and no leak current is generated in the TFT 11a. Therefore, the voltage Vlc of the liquid crystal capacitor Clc1 can maintain a desired voltage value. Similarly, for the other pixels related to the drain bus line 9a, the voltage Vlc of the liquid crystal capacitance Clc can maintain a desired voltage value. Note that the resistance value of the combined resistance of the storage capacitor bus lines 15a and 15b and the common storage capacitor line 17 is relatively large. For this reason, even if the pixel electrode 13b is short-circuited to the storage capacitor bus line 15b, the voltage drop of the voltage Vcs applied to the storage capacitor bus lines 15a and 15b and the common storage capacitor line 17 hardly occurs.

  As indicated by B in FIG. 2, when the pixel electrode 13b and the common electrode 21 are short-circuited (problem (2)), the potential Vd of the drain bus line 9a hardly fluctuates. Leakage current does not flow, and the voltage Vlc applied to the liquid crystal capacitance Clc1 can maintain a desired voltage value. Similarly, leak current does not flow for TFTs other than the TFTs 11a and 11b connected to the drain bus line 9a, and the voltage Vlc applied to the liquid crystal capacitor can maintain a desired voltage value.

  Further, since the drain bus line 9a is maintained at a predetermined potential Vd by the coupling capacitance Cps1 and the coupling capacitance Cpc1 having large capacitance values, the drain bus line 9a is connected to the gate bus as indicated by C in FIG. Even if the line 7a is short-circuited (problem (3)), the potential fluctuation of the drain bus line 9a hardly occurs. In this case, since the voltage between the gate and the drain of the TFT 11a is almost zero, the TFT 11a remains off. Furthermore, since the gate-drain voltage of the TFT 11b formed at the intersection of the drain bus line 9a and the gate bus line 7b hardly fluctuates, the TFT 11b remains off. Similarly, the TFT formed at the intersection of the drain bus line 9a and another gate bus line remains in the OFF state. Accordingly, no leak current flows through all the TFTs 11a and 11b connected to the drain bus line 9a, and the voltage Vlc applied to the liquid crystal capacitors Clc1 and Clc2 can maintain a desired voltage value. The resistance value of the common electrode 21 is relatively large. For this reason, even if the pixel electrode 13b is short-circuited to the common electrode 21, the voltage drop of the voltage Vc applied to the common electrode 21 hardly occurs.

  As described above, the liquid crystal display device 1 according to the present embodiment includes the superposition TFTs 29a and 29b between the adjacent drain bus lines. When the monomer is polymerized, the liquid crystal display device 1 turns on the polymerization TFTs 29a and 29b so that the drain bus lines 9a, 9b, and 9c are electrically connected to each other, and the drain bus lines 9a, 9b, and 9c are connected to the storage capacitor bus line. The capacitance values of the coupling capacitors Cps1, Cps2, and Cps3 formed between 15a and 15b and the coupling capacitors Cpc1, Cpc2, and Cpc3 formed between the common electrode 21 can be increased.

  Accordingly, the liquid crystal display device 1 can easily maintain the potential Vd of the drain bus lines 9a, 9b, and 9c at a predetermined value even when the drain bus lines 9a, 9b, and 9c are in a floating state. Therefore, for example, even if a short circuit between the pixel electrode 13b and the storage capacitor bus line 15b or a short circuit between the pixel electrode 13b and the common electrode 21 occurs and a leak current flows through the TFT 11b, the potential Vd of the drain bus line 9a hardly changes. . Thus, when the monomer is polymerized, the voltage Vlc applied to the liquid crystal capacitance Clc1 in the pixel region connected to the drain bus line 9a hardly changes, and the pretilt angle of the liquid crystal molecules in the pixel region is changed to the drain bus line 9a. It can be formed at substantially the same angle as the pretilt angle of the liquid crystal molecules in the other pixel region connected to the drain bus line other than. Accordingly, when used as a display unit, the liquid crystal display device 1 can prevent the occurrence of display unevenness in the form of line defects with different brightness that occurs on the display screen.

  The pixel electrodes 13a and 13b and the storage capacitor bus lines 15a and 15b or the common electrode 21 are short-circuited, and pixels in which the pretilt angle of the liquid crystal molecules is not formed at a desired angle are formed dispersed in millions of pixels. However, the display defect due to this is hardly noticeable and does not become a problem in actual use of the liquid crystal display device 1.

  Next, a manufacturing method of the liquid crystal display device according to the present embodiment will be described. In the following, description will be given by taking, as an example, nine adjacent pixels of 3 rows and 3 columns among a plurality of pixels of m rows and n columns arranged in a matrix. As shown in FIG. 1, nothing is provided to the input terminals 8a to 8d of the gate bus lines 7a to 7d, the input terminals 10a to 10d of the drain bus lines 9a to 9d, and the connection terminals 37a and 37b of the repair wirings 35a and 35b. A control signal is input from the input terminal 33 connected to the control wiring 31 without being connected. As a result, the superposition TFTs 29a and 29b are turned on, and the drain bus lines 9a, 9b and 9c are brought into conduction. For example, a positive DC voltage is applied to the control wiring 31 with respect to a reference potential (ground potential).

  Next, an alternating voltage (square wave) with a voltage Vcs = ± 20 V is applied to the common electrode terminal 23, and a voltage Vcs = 0 V is applied to the common storage capacitor terminal 19. Accordingly, a desired voltage Vlc is applied to the liquid crystal capacitors Clc1 and Clc2 of each pixel based on the equation (1). If the capacitance value Clc of the liquid crystal capacitors Clc1 and Clc2 is 250 fF, and the capacitance value Cs of the storage capacitors Cs1 and Cs2 is 250 fF, the voltage value of the voltage Vlc is about ± 10V.

  Next, as shown by a thick arrow in FIG. 1B, the liquid crystal display device 1 is irradiated with UV light from the TFT substrate 2 side. Since the voltage Vlc = ± 10 V is applied to the liquid crystal 45, the liquid crystal molecules are inclined in a predetermined direction. For this reason, the liquid crystal acrylate material mixed in the liquid crystal 45 is bridged by being dragged in the direction in which the liquid crystal molecules are tilted. Next, the application of the voltages Vc and Vcs to the common electrode terminal 23 and the common storage capacitor terminal 19 is finished. Next, the input of the control signal to the control wiring 31 is terminated, and the superposition TFTs 29a, 29b, and 29c are turned off. Thus, the initial alignment state of the liquid crystal molecules in all the pixel regions of the liquid crystal display device 1 is formed in a state slightly tilted in a predetermined direction from the vertical alignment state.

  When polymerizing the liquid crystal acrylate material of the polymerizable component, by turning on the polymerization TFTs 29a and 29b, the drain bus lines 9a, 9b and 9c are coupled capacitors Cps1 to Cps3 and Cpc1 to Cpc3 having large capacitance values. Each is held at a predetermined potential Vd. Therefore, for example, as indicated by A in FIG. 2, even if the pixel electrode 13b and the storage capacitor bus line 15b are short-circuited, the potential Vd of the drain bus line 9a hardly varies. As a result, the gate-drain voltage of the TFT 11a connected to the drain bus line 9a hardly changes, and no leak current is generated in the TFT 11a. Therefore, the voltage Vlc applied to the liquid crystal capacitor Clc1 can maintain a desired voltage value.

  As described above, according to the method of manufacturing the liquid crystal display device 1 according to the present embodiment, when the monomers are polymerized, the polymerization TFTs 29a and 29b are turned on so that the drain bus lines 9a, 9b, and 9c are electrically connected. be able to. Thereby, the coupling capacitors Cpc1, Cpc2 formed between the coupling capacitors Cps1, Cps2, Cps3 formed between the drain bus lines 9a, 9b, 9c and the storage capacitor bus lines 15a, 15b and the common electrode 21. , Cpc3 can be increased in capacitance.

  Accordingly, the liquid crystal display device 1 can easily maintain the potential Vd of the drain bus lines 9a, 9b, and 9c at a predetermined value even when the drain bus lines 9a, 9b, and 9c are in a floating state. Therefore, for example, even if a short circuit between the pixel electrode 13b and the storage capacitor bus line 15b or a short circuit between the pixel electrode 13b and the common electrode 21 occurs, this influence does not reach other pixel regions, but affects the drain bus line 9a. A predetermined voltage Vlc = ± 10 V can be applied to the liquid crystal capacitor Clc1 in the connected pixel region. Thereby, the pretilt angle of the liquid crystal molecules in the pixel region can be formed at substantially the same angle as the pretilt angles of the liquid crystal molecules in the other pixel regions connected to the drain bus lines 9b and 9c. Therefore, the liquid crystal display device 1 can prevent the occurrence of display defects such as line defects with different brightness that occur on the display screen.

  Further, the liquid crystal display device 1 does not need to input a predetermined voltage to the gate bus lines 7a to 7d and the drain bus lines 9a to 9d in the polymerization step, and therefore the step of inputting a voltage to the wiring is omitted. Therefore, the manufacturing efficiency of the liquid crystal display device 1 can be improved.

[Second Embodiment]
Next, a liquid crystal display device according to a second embodiment of the present invention and a method for manufacturing the same will be described with reference to FIGS. The liquid crystal display device according to the present embodiment is characterized in that it is provided with a polymerization TFT that conducts between the gate bus lines when the monomer mixed in the liquid crystal is polymerized. FIG. 3 shows an equivalent circuit of two adjacent pixels of 2 rows and 1 column among a plurality of pixels of m rows and n columns arranged in a matrix of the liquid crystal display device 50 according to the present embodiment.

  As shown in FIG. 3, in addition to the configuration of the liquid crystal display device 1 according to the first embodiment, the liquid crystal display device 50 according to the present embodiment has a gate bus line when polymerizing monomers mixed in the liquid crystal. Polymerization TFTs (second polymerization thin film transistors) 53a and 53b that conduct between 7a, 7b, and 7c, and polymerization auxiliary TFTs that conduct between the gate bus line 7a and the drain bus line 9a (first polymerization use) Auxiliary thin film transistor) 55.

  A superposition TFT 53a is formed between the adjacent gate bus lines 7a and 7b. The drain electrode (D) of the superposition TFT 53a is connected to the gate bus line 7a, and the source electrode (S) is connected to the gate bus line 7b. Further, the gate electrode (G) of the superposition TFT 53 a is connected to a control wiring (second control wiring) 59. A control signal for controlling the switching of the superposition TFT 53a is input to the control wiring 59. The control wiring 59 intersects with the gate bus lines 7a, 7b, 7c via an insulating film and extends in the vertical direction in the figure. One end of the control wiring 59 is connected to the control wiring 31, for example.

  Similarly, a superposition TFT 53b is formed between the adjacent gate bus lines 7b and 7c. The drain electrode (D) of the polymerization TFT 53b is connected to the gate bus line 7b, and the source electrode (S) is connected to the gate bus line 7c. The gate electrode (G) of the superposition TFT 53 b is connected to the control wiring 59. Thereafter, similarly, a polymerization TFT having the same configuration as the polymerization TFTs 53a and 53b is formed between the gate bus lines.

  A superposition auxiliary TFT 55 is formed between the gate bus line 7a and the drain bus line 9a. The drain electrode (D) of the auxiliary TFT 55 for polymerization is connected to the drain bus line 9a, and the source electrode (S) is connected to the gate bus line 7a. The gate electrode (G) of the polymerization auxiliary TFT 55 is connected to the control wiring 31. A control signal flowing through the control wiring 31 is input to the gate electrode (G), and switching of the superposition auxiliary TFT 55 is controlled.

  The superimposing auxiliary TFT 55 is not necessarily connected to the gate bus line 7a and the drain bus line 9a. It is only necessary that the source electrode (S) of the superposition auxiliary TFT 55 is connected to any one of the gate bus lines, and the drain electrode (D) is connected to at least one of the drain bus lines. In addition, the drain electrode (D) of the polymerization auxiliary TFT 55 may be connected to any one of the gate bus lines, and the source electrode (S) may be connected to at least one of the drain bus lines. Further, the gate electrode (G) of the polymerization auxiliary TFT 55 may be connected to the control wiring 59.

  When the superposition TFTs 53a and 53b are turned on, the gate bus lines 7a, 7b and 7c are connected in parallel. Further, when the polymerization auxiliary TFT 55 and the polymerization TFTs 29a and 29b are turned on, the potential Vg of the gate bus lines 7a, 7b and 7c becomes the same as the potential Vd of the drain bus lines 9a, 9b and 9c. As a result, the voltage between the gate and the drain becomes almost 0V, so that the TFTs 11a and 11b are turned off. Further, as indicated by C in FIG. 3, even when a short-circuit defect occurs between the gate bus line 7a and the drain bus line 9a (problem (3)), the superposition TFTs 53a and 53b and the superposition aid Due to the TFT 55, the potential Vg of the gate bus lines 7a, 7b, and 7c and the potential Vd of the drain bus lines 9a, 9b, and 9c are the same potential, so that the short-circuit defect does not affect.

  Thus, in the polymerization step, all the gate bus lines 7a, 7b, 7c, etc. on the TFT substrate 2 and the drain bus lines 9a, 9b, etc. on the TFT substrate 2 using the polymerization TFTs 53a, 53b and the auxiliary TFT 55 for polymerization. If the potentials 9c and the like are previously set to the same potential, for example, the influence of a short circuit defect between the gate bus line 7a and the drain bus line 9a does not occur. As a result, the occurrence of leakage current of the TFTs 11a and 11b is prevented, and the voltage Vlc applied to the liquid crystal capacitors Clc1 and Clc2 can maintain a desired voltage value. Therefore, the pretilt angles of the liquid crystal molecules in all the pixel regions can be formed at a desired angle. Thereby, when using as a display part, the liquid crystal display device 50 can prevent the occurrence of display unevenness in the form of line defects with different brightness that occurs on the display screen.

  The liquid crystal display device 50 ensures that the potential Vg of the gate bus lines 7a, 7b, 7c, etc. and the potential Vd of the drain bus lines 9a, 9b, 9c, etc. are almost the same potential by the superposition TFTs 53a, 53b and the superposition auxiliary TFT 55. Can be. For this reason, the liquid crystal display device 50 can prevent the influence of the short-circuit defect between the gate bus line and the drain bus line more reliably than the liquid crystal display device 1.

  The manufacturing method of the liquid crystal display device 50 according to the present embodiment is the same as that described above except that the polymerization TFTs 53a and 53b and the polymerization auxiliary TFT 55 are turned on when the monomer mixed in the liquid crystal is polymerized. Since it is the same as that of the liquid crystal display device 1 according to the form, the description is omitted.

[Third Embodiment]
Next, a liquid crystal display device according to a third embodiment of the present invention and a method for manufacturing the same will be described with reference to FIGS. The liquid crystal display device according to the present embodiment is characterized in that it includes a polymerization TFT that conducts between the drain bus line and the repair wiring when the monomer mixed in the liquid crystal is polymerized. FIG. 4 shows an equivalent circuit of two adjacent pixels in 2 rows and 1 column among a plurality of pixels in m rows and n columns arranged in a matrix of the liquid crystal display device 70 according to the present embodiment.

  As shown in FIG. 4, in addition to the configuration of the liquid crystal display device 1 according to the first embodiment, the liquid crystal display device 70 according to the present embodiment repairs the repair wiring 35a when polymerizing monomers mixed in the liquid crystal. , 35b and the drain bus line 9a are connected to the polymerization TFT (third polymerization thin film transistor) 57a, 57b, and the repair wiring 35a, 35b are connected to the polymerization auxiliary TFT (second polymerization auxiliary). Thin film transistor) 58.

  A superposition TFT 57a is formed between the repair wiring 35a and the drain bus line 9a. The source electrode (S) of the superposition TFT 57a is connected to the repair wiring 35a, and the drain electrode (D) is connected to the drain bus line 9a. Further, the gate electrode (G) of the superposition TFT 57 a is connected to a control wiring (third control wiring) 61. A control signal for controlling the switching of the superposition TFT 57a is input to the control wiring 61. The control wiring 61 is formed so as to cross the gate bus lines 7a, 7b, 7c via an insulating film and extend in the vertical direction in the drawing. One end of the control wiring 61 is connected to the control wiring 31, for example.

  Similarly, a superposition TFT 57b is formed between the repair wiring 35b and the drain bus line 9a. The source electrode (S) of the superposition TFT 57b is connected to the repair wiring 35b, and the drain electrode (D) is connected to the drain bus line 9a. The gate electrode (G) of the superposition TFT 57 b is connected to the control wiring 61.

  The drain electrodes (D) of the superposition TFTs 57a and 57b are not necessarily connected to the drain bus line 9a. The drain electrode (D) only needs to be connected to at least one of the drain bus lines 9a, 9b, 9c. The drain electrodes (D) of the superposition TFTs 57a and 57b are connected to the repair wirings 35a and 35b, respectively, and the source electrode (S) is connected to at least one of the drain bus lines 9a, 9b and 9c. Also good. Further, the gate electrodes (G) of the superposition TFTs 57 a and 57 b may be directly connected to the control wiring 31 without being connected to the control wiring 61.

  A superposition auxiliary TFT 58 is formed between the repair wirings 35a and 35b. The source electrode (S) of the polymerization auxiliary TFT 58 is connected to the repair wiring 35a, and the drain electrode (D) is connected to the repair wiring 35b. The gate electrode (G) of the polymerization auxiliary TFT 58 is connected to the control wiring 61. A control signal flowing in the control wiring 61 is input to the gate electrode (G), and switching of the superposition auxiliary TFT 58 is controlled. The gate electrode (G) of the polymerization auxiliary TFT 58 may be connected to the control wiring 31 without being connected to the control wiring 61.

  When the monomers mixed in the liquid crystal are polymerized, if the polymerization TFTs 29a and 29b, the polymerization TFTs 57a and 57b, and the polymerization auxiliary TFT 58 are turned on, the drain bus lines 9a, 9b, and 9c are connected to the repair wirings 35a and 35b. Since conduction is made with a low resistance, the potential Vd of the drain bus lines 9a, 9b, 9c is the same as the potential of the repair wirings 35a, 35b. As shown in FIG. 4, when a disconnection defect (x mark) occurs in the drain bus line 9a, the drain bus line 9a is repaired as shown by D and D 'in the drawing in order to repair the drain bus line 9a. The intersections with the wirings 35a and 35b are connected (problem (4)). Since the drain bus line 9a is connected to the repair wirings 35a and 35b in advance using the superposition TFTs 57a and 57b and the superposition auxiliary TFT 58, even if the drain bus line 9a is repaired, the potential Vd of the drain bus line 9a is Almost no change.

  Further, because of the superposition TFTs 29a and 29b, the drain bus line 9a has a large capacitance value of the coupling capacitors Cps1 and Cpc1 formed between the storage capacitor bus lines 15a and 15b and the common electrode 21, so The potential Vd of the line 9a is difficult to change. Therefore, even if the disconnection of the drain bus line 9a is repaired, the gate-drain voltages of the TFTs 11a, 11b, etc. connected to the drain bus line 9a do not fluctuate and no leak current is generated. Thereby, the voltage Vlc applied to the liquid crystal capacitors Clc1 and Clc2 can maintain a desired voltage value. Therefore, when the monomer is polymerized, the pretilt angles of the liquid crystal molecules in all the pixel regions can be formed at a desired angle. Thereby, when used as a display unit, the liquid crystal display device 70 can prevent the occurrence of display unevenness in the form of line defects with different brightness that occurs on the display screen.

  By forming the polymerization TFTs 53a and 53b and the polymerization auxiliary TFT 55 of the liquid crystal display device 50 according to the second embodiment on the liquid crystal display device 70 according to the present embodiment, the gate bus lines 7a, 7b and 7c, The influence of the short-circuit defect with the drain bus lines 9a, 9b, 9c is more reliably prevented. Thereby, the liquid crystal display device 70 can cope with the problems (1) to (4).

  The manufacturing method of the liquid crystal display device 70 according to the present embodiment is the same as that described above except that the polymerization TFTs 57a and 57b and the polymerization auxiliary TFT 58 are turned on when the monomer mixed in the liquid crystal is polymerized. Since it is the same as that of the liquid crystal display device 1 according to the form, the description is omitted.

[Fourth Embodiment]
Next, a liquid crystal display device and a method for manufacturing the same according to a fourth embodiment of the present invention will be described with reference to FIGS. The liquid crystal display device 80 according to the present embodiment is characterized in that it has two pixel electrodes for each pixel region and has a predetermined capacitance formed by the two pixel electrodes. FIG. 5 shows an equivalent circuit of two adjacent pixels in 2 rows and 1 column among a plurality of pixels in m rows and n columns arranged in a matrix in the liquid crystal display device 80 according to the present embodiment.

  As shown in FIG. 5, the first pixel electrode 63a formed in the pixel region is connected to the source electrode (S) of the TFT 11a formed at the intersection of the gate bus line 7a and the drain bus line 9a. Yes. A second pixel electrode 64a is formed in the pixel region. The first pixel electrode 63a, the second pixel electrode 64a, and the insulating film sandwiched therebetween form a polymerization capacitance (predetermined capacitance) Cpp1. Further, the storage capacitor Cs1 is formed by the second pixel electrode 64a, the storage capacitor bus line 15a, and the insulating film sandwiched therebetween. The storage capacitor bus line 15a serves as one electrode of the storage capacitor Cs1, and the second pixel electrode 64a serves as the other electrode. In addition, a liquid crystal capacitor Clc1 is formed by the second pixel electrode 64a, the common electrode 21, and the liquid crystal 45 sandwiched therebetween. The common electrode 21 is one electrode of the liquid crystal capacitor Clc1, and the second pixel electrode 64a is the other electrode.

  Similarly, the first pixel electrode 63b formed in the pixel region is connected to the source electrode (S) of the TFT 11b formed at the intersection of the gate bus line 7b and the drain bus line 9a. In addition, a second pixel electrode 64b is formed in the pixel region. An electric capacity for polymerization (predetermined electric capacity) Cpp2 is formed by the first pixel electrode 63b, the second pixel electrode 64b, and the insulating film sandwiched therebetween. Further, the storage capacitor Cs2 is formed by the second pixel electrode 64b, the storage capacitor bus line 15b, and the insulating film sandwiched therebetween. The storage capacitor bus line 15b is one electrode of the storage capacitor Cs2, and the second pixel electrode 64b is the other electrode. Further, a liquid crystal capacitor Clc2 is formed by the second pixel electrode 64b, the common electrode 21, and the liquid crystal 45 sandwiched therebetween. The common electrode 21 becomes one electrode of the liquid crystal capacitor Clc2, and the second pixel electrode 64b becomes the other electrode. Thereafter, similarly, the other pixel regions have the same pixel configuration.

The voltage Vlc applied to the liquid crystal capacitances Clc1 and Clc2 when polymerizing the monomer mixed in the liquid crystal is the same as the capacitance values Cc of the storage capacitors Cs1 and Cs2, and the capacitance values Clc of the liquid crystal capacitances Clc1 and Clc2. When the alternating voltage applied between the electrode terminal 23 and the common storage capacitor terminal 19 is Va, it can be expressed as follows.
Vlc = {Cs / (Cs + Clc)} × Va (4)

When the liquid crystal display device 80 is used as a display unit of an electronic device, it is assumed that a voltage Vc having the same potential is applied to the common electrode 21 and the storage capacitor bus lines 15a and 15b. Further, assuming that the potential of the first pixel electrodes 63a and 63b is Vp and the capacitance values of the superposition capacitances Cpp1 and Cpp2 are Cpp, the voltage Vlc applied to the liquid crystal capacitances Clc1 and Clc2 is expressed as follows. Can do.
Vlc = {Cpp / (Cs + Clc + Cpp)} × (Vp−Vc) (5)

Further, the relationship between the capacitance value Cpp of the polymerization capacitances Cpp1 and Cpp2, the capacitance value Clc of the liquid crystal capacitances Clc1 and Clc2, and the capacitance value Cs of the storage capacitors Cs1 and Cs2 is expressed as Cpp >> Clc, Cs (6).
Thus, the equation (5) becomes as follows.
Vlc≈ (Vp−Vc) (7)
Therefore, by forming the superposition capacitances Cpp1 and Cpp2, the liquid crystal capacitances Clc1 and Clc2, and the storage capacitances Cs1 and Cs2 so that the capacitance value in the pixel region satisfies the formula (6), the superposition capacitances Cpp1 and Cpp2 Can be applied to the liquid crystal capacitors Clc1 and Clc2.

  Further, the gradation voltage applied to the drain bus line 9a is applied to the first pixel electrodes 63a and 63b via the TFTs 11a and 11b. Therefore, the potential difference between the reference potential (ground potential) and the potential Vp of the first pixel electrodes 63a and 63b can be regarded as a gradation voltage. Therefore, even when the superposition electric capacities Cpp1 and Cpp2 are provided, the liquid crystal display device 80 applies the voltage Vlc of the difference between the gradation voltage and the voltage Vc of the common electrode 21 to the liquid crystal capacities Clc1 and Clc2 at the time of actual driving display. can do.

  By the way, in the conventional liquid crystal display devices 101 and 201, the line defect-like display defect based on the above problems (1) to (4) occurs when the drain bus line 109a and the pixel electrode are polymerized when the monomers are polymerized. This is because 113a and 113c are not completely insulated from each other, or a resistance state in which no leak current is generated in the TFTs 111a and 111c is not realized. However, it is very difficult to apply a voltage for completely turning off the TFTs 111a and 111c connected to the pixel electrodes 113a and 113c to the gate electrodes (G). This is because a voltage of about ± 10V is applied between the pixel electrodes 113a and 113c and the common electrode 121, so that the TFTs 111a and 111c have sufficient off characteristics at both extreme voltages of ± 10V. It is because it is difficult to realize. That is, even if the voltage of the pixel electrodes 113a and 113c is larger or smaller than the gate voltage of the TFTs 111a and 111c, the leakage current of the TFTs 111a and 111c increases.

  As shown in FIG. 5, in the liquid crystal display device 80 according to the present embodiment, the second pixel electrodes 64a and 64b are connected to the source electrodes of the TFTs 11a and 11b via the polymerization capacitances Cpp1 and Cpp2 having relatively large capacitance values. Each is connected to (S). Therefore, when the monomer mixed in the liquid crystal 45 is polymerized, for example, even if the second pixel electrode 64a and the storage capacitor bus line 15a or the common electrode 21 are short-circuited (in (1) and (2) Problem) Since it takes time to charge and discharge the polymerization capacitance Cpp1, the voltage applied to the polymerization capacitance Cpp1 hardly fluctuates. For this reason, the voltage of the source electrode (S) of the TFT 11a hardly fluctuates and no leak current is generated in the TFT 11a. Therefore, the potential fluctuation of the drain bus line 9a does not occur. For this reason, the gate-drain voltage of the TFT 11b does not fluctuate, and no leak current flows through the TFT 11b. Accordingly, the voltage applied to the superposition electric capacity Cpp2 hardly fluctuates and the potential of the second pixel electrode 64b does not fluctuate, so that the desired voltage Vlc is applied to the liquid crystal capacity Clc2.

  Further, for example, even if the drain bus line 9a is short-circuited to the gate bus line 7a (problem (3)), the potential of the drain bus line 9a fluctuates, and a leakage current occurs in the TFTs 11a and 11b. Cpp1 and Cpp2 can prevent potential fluctuations of the second pixel electrodes 64a and 64b. As a result, a predetermined voltage Vlc can be applied to the liquid crystal capacitors Clc1 and Clc2.

  For example, when the drain bus line 9a is connected to the repair wirings 35a and 35b to repair the disconnection defect (problem (4)), the potential of the drain bus line 9a may fluctuate. Even if a leak current occurs in the TFTs 11a and 11b due to the potential fluctuation, the potential fluctuations of the second pixel electrodes 64a and 64b can be prevented by the superposition electric capacitances Cpp1 and Cpp2. As a result, a predetermined voltage Vlc can be applied to the liquid crystal capacitors Clc1 and Clc2.

  Thus, the liquid crystal display device 80 according to the present embodiment has a superposition capacitance in each pixel region. Thereby, for example, the second pixel electrodes 64a and 64b can be regarded as being insulated from the drain bus line 9a or connected with high resistance. For this reason, even when the second pixel electrode 64a is short-circuited to the storage capacitor bus line 15a or the common electrode 21 when the monomer is polymerized, fluctuations in the potential of the drain bus line 9a can be prevented. Even if the drain bus line 9a is short-circuited to the gate bus line 7a or short-circuited to the repair wirings 35a and 35b, and the potential fluctuation of the drain bus line 9a occurs, the potential of the second pixel electrodes 64a and 64b. Fluctuation can be prevented. Therefore, substantially the same voltage Vlc can be applied to the liquid crystals 45 of all the pixels except for the pixels short-circuited to the storage capacitor bus lines 15a and 15b or the common electrode 21. Similarly, in other pixel regions, even if the second pixel electrode is short-circuited to the common electrode 21 or the like, the potential fluctuation of the second pixel electrode can be prevented. Thereby, when polymerizing a monomer, the pretilt angle of a liquid crystal molecule can be formed in a desired angle. Therefore, the liquid crystal display device 80 can prevent the occurrence of non-uniform display of line defects with different brightness that occurs on the display screen during actual driving display.

  The second pixel electrodes 64a and 64b and the storage capacitor bus lines 15a and 15b or the common electrode 21 are short-circuited, and pixels in which the pretilt angle of liquid crystal molecules is not formed at a desired angle are dispersed in millions of pixels. Even if formed, the display defect due to this is hardly noticeable, and does not become a problem in practical use of the liquid crystal display device 80.

  Next, a manufacturing method of the liquid crystal display device according to the present embodiment will be described. Hereinafter, two adjacent pixels in 2 rows and 1 column among a plurality of pixels in m rows and n columns arranged in a matrix will be described as an example. As shown in FIG. 5, nothing is connected to all the input terminals 8a, 8b, 10a, 10b, 10c, etc. and the connection terminals 37a, 37b, the gate bus lines 7a, 7b, etc., the drain bus lines 9a, 9b, 9c, etc. and the repair wirings 35a, 35b are brought into a floating state.

  Next, an alternating voltage (square wave) with a voltage Vcs = ± 20 V is applied to the common electrode terminal 23, and a voltage Vcs = 0 V is applied to the common storage capacitor terminal 19. As a result, the voltage Vlc is applied to the liquid crystal capacitors Clc1 and Clc2 of each pixel based on the equation (1).

  Next, the liquid crystal display device 80 is irradiated with UV light from the TFT substrate side to polymerize the polymerizable component mixed in the liquid crystal 45. Since the voltage Vlc is applied to the liquid crystal 45, the liquid crystal molecules are inclined in a predetermined direction. For this reason, the liquid crystal acrylate-based material of the polymerizable component is crosslinked by dragging in the direction in which the liquid crystal molecules are tilted. Next, the application of the voltages Vc and Vcs to the common electrode terminal 23 and the common storage capacitor terminal 19 is finished. Thus, the initial alignment state of the liquid crystal molecules in all the pixel regions of the liquid crystal display device 80 is formed in a state slightly tilted in a predetermined direction from the vertical alignment state.

  When the monomer is polymerized, for example, even if the second pixel electrode 64a and the storage capacitor bus line 15a are short-circuited, the second pixel electrode 64a is insulated from the drain bus line 9a by the polymerization capacitance Cpp1. It can be regarded as a connected state or a connected state with high resistance. For this reason, since the potential of the drain bus line 9a does not fluctuate due to the short circuit, the potential fluctuation of the second pixel electrode 64b in another pixel region connected to the drain bus line 9a can be prevented. Therefore, substantially the same voltage Vlc can be applied to the liquid crystals 45 of all the pixels except for the pixels short-circuited to the storage capacitor bus lines 15a and 15b or the common electrode 21. Thereby, the pretilt angle of the liquid crystal molecules can be formed to a desired angle.

  Thus, according to the manufacturing method of the liquid crystal display device according to the present embodiment, since the liquid crystal display device 80 has the polymerization capacitances Cpp1 and Cpp2, the second due to the short-circuit defect is caused when the monomers are polymerized. The influence of the potential fluctuation of the pixel electrodes 64a and 64b does not reach the potential of the drain bus line 9a. Further, the influence of the potential fluctuation of the drain bus line 9a does not reach the potential of the second pixel electrodes 64a and 64b. Thereby, when the monomers are polymerized, almost the same voltage Vlc can be applied to the liquid crystals 45 in all the pixel regions in the display region of the liquid crystal display device 80, so that the pretilt angle of the liquid crystal molecules can be formed at a desired angle. Therefore, it is possible to prevent the occurrence of non-uniform display of line defects having different brightness that occurs on the display screen of the liquid crystal display device 80 during actual driving display.

  Further, the liquid crystal display device 80 does not need to input a predetermined voltage to the gate bus lines 7a, 7b and the drain bus lines 9a, 9b, 9c when the monomer is polymerized. The process can be omitted, and the polymerization process can be simplified. Thereby, the manufacturing efficiency of the liquid crystal display device 80 can be improved.

[Fifth Embodiment]
Next, a liquid crystal display device and a method for manufacturing the same according to a fifth embodiment of the present invention will be described with reference to FIGS. The liquid crystal display device according to the present embodiment is characterized in that it includes a polymerization TFT that conducts between the drain bus line and the common storage capacitor line when the monomer mixed in the liquid crystal is polymerized. Yes. FIG. 6 shows an equivalent circuit of two adjacent pixels in 2 rows and 1 column among a plurality of pixels in m rows and n columns arranged in a matrix of the liquid crystal display device 85 according to the present embodiment.

  As shown in FIG. 6, in addition to the configuration of the liquid crystal display device 80 according to the fourth embodiment, the liquid crystal display device 85 according to the present embodiment uses a drain bus line when polymerizing monomers mixed in the liquid crystal 45. Superposition TFTs 65a and 65b are provided for conducting between 9a and 9b and the common storage capacitor wiring 17.

  The drain electrode (D) of the superposition TFT 65 a is connected to the drain bus line 9 a, and the source electrode (S) is connected to the common storage capacitor line 17. The gate electrode (G) of the superposition TFT 65 a is connected to the control wiring 67. The control wiring 67 receives a control signal for controlling the switching of the superposition TFT 65a. The control wiring 67 intersects with the drain bus lines 9a and 9b through an insulating film and extends in the left-right direction in the drawing. One end of the control wiring 67 is connected to an input terminal 69 for inputting a control signal.

  Similarly, the drain electrode (D) of the superposition TFT 65 b is connected to the drain bus line 9 b, and the source electrode (S) is connected to the common storage capacitor wiring 17. The gate electrode (G) of the superposition TFT 65 b is connected to the control wiring 67. Similarly, a superposition TFT having the same configuration as the superposition TFTs 65a and 65b is formed between the drain bus line and the common storage capacitor line 17 in the same manner.

  The source electrodes (S) of the superposition TFTs 65 a and 65 b may be connected to the storage capacitor bus lines 15 a and 15 b instead of the common storage capacitor line 17. Further, the source electrodes (S) of the superposition TFTs 65a and 65b are connected to the drain bus lines 9a and 9b, respectively, and the drain electrode (D) is connected to the common storage capacitor line 17 or the storage capacitor bus lines 15a and 15b. Good.

  When polymerizing the monomer mixed in the liquid crystal 45, when the polymerization TFTs 65a and 65b are turned on, the drain bus lines 9a and 9b are electrically connected to the common storage capacitor wiring 17 with a low resistance. The potential of 9b is almost the same as the potential of the common storage capacitor wiring 17. Since the common storage capacitor line 17 is connected to the storage capacitor bus lines 15a and 15b, the drain bus lines 9a and 9b have substantially the same potential as the storage capacitor bus lines 15a and 15b. Therefore, the drain bus lines 9a and 9b maintain the same potential as that of the storage capacitor bus lines 15a and 15b regardless of the presence or absence of a short circuit defect between the drain bus lines 9a and 9b and the storage capacitor bus lines 15a and 15b. Can do.

  Therefore, even if a short circuit defect occurs between the drain bus lines 9a and 9b and the storage capacitor bus lines 15a and 15b, the potential fluctuation does not occur in the drain bus lines 9a and 9b, and the potential also occurs in the second pixel electrodes 64a and 64b. Fluctuation hardly occurs. As a result, a desired voltage Vlc can be applied to the liquid crystal capacitors Clc1 and Clc2. Therefore, when the monomers are polymerized, the pretilt angles of the liquid crystal molecules in all the pixel regions of the liquid crystal display device 85 can be formed at a desired angle. Thereby, it is possible to prevent the occurrence of non-uniform display of line defects with different brightness that occurs on the display screen of the liquid crystal display device 85 during actual driving display.

  The manufacturing method of the liquid crystal display device 85 according to the present embodiment is the same as the fourth embodiment except that the polymerization TFTs 65a and 65b are turned on when the monomer mixed in the liquid crystal 45 is polymerized. Since it is the same as that of the liquid crystal display device 80 according to FIG.

[Sixth Embodiment]
Next, a liquid crystal display device and a method for manufacturing the same according to a sixth embodiment of the present invention will be described with reference to FIGS. The liquid crystal display device according to the present embodiment is characterized in that it includes a polymerization TFT that conducts between the drain bus line and the common electrode when the monomer mixed in the liquid crystal is polymerized. FIG. 7 shows an equivalent circuit of two adjacent pixels in 2 rows and 1 column among a plurality of pixels in m rows and n columns arranged in a matrix of the liquid crystal display device 90 according to the present embodiment.

  As shown in FIG. 7, in addition to the configuration of the liquid crystal display device 80 according to the fourth embodiment, the liquid crystal display device 90 according to this embodiment has a drain bus line 9a when polymerizing monomers mixed in the liquid crystal. , 9b and the common electrode 21 are provided with polymerization TFTs (another polymerization thin film transistors) 71a and 71b.

  The source electrode (S) of the polymerization TFT 71a is connected to the common electrode 21, and the drain electrode (D) is connected to the drain bus line 9a. The gate electrode (G) of the superposition TFT 71 a is connected to a control wiring (another control wiring) 73. A control signal for controlling the switching of the superposition TFT 71a is input to the control wiring 73. The control wiring 73 crosses the drain bus lines 9a and 9b via an insulating film and extends in the left-right direction in the drawing. One end of the control wiring 73 is connected to an input terminal 75 for inputting a control signal.

  Similarly, the source electrode (S) of the superposition TFT 71b is connected to the common electrode 21, and the drain electrode (D) is connected to the drain bus line 9b. Similarly, a polymerization TFT having the same configuration as that of the polymerization TFTs 71a and 71b is formed between the drain bus line and the common electrode 21.

  The gate electrode (G) of the superposition TFT 71 b is connected to the control wiring 73. The source electrodes (S) of the superposition TFTs 71 a and 71 b may be connected to the drain bus lines 9 a and 9 b, respectively, and the drain electrode (D) may be connected to the common electrode 21.

  When polymerizing the monomer mixed in the liquid crystal 45, if the polymerization TFTs 71a and 71b are turned on, the drain bus lines 9a and 9b are electrically connected to the common electrode 21 with a low resistance, so that the drain bus lines 9a and 9b The potential is substantially the same as the potential of the common electrode 21. Therefore, the drain bus lines 9 a and 9 b maintain the same potential as that of the common electrode 21 regardless of the presence or absence of short-circuit defects between the drain bus lines 9 a and 9 b and the common electrode 21. Accordingly, even if a short-circuit defect occurs between the drain bus lines 9a and 9b and the common electrode 21 (problem (5)), the potential Vd of the drain bus lines 9a and 9b does not fluctuate, so the second pixel electrodes 64a and 64b. No potential fluctuation occurs, and a desired voltage Vlc can be applied to the liquid crystal capacitors Clc1 and Clc2. Thereby, when the monomer is polymerized, the pretilt angles of the liquid crystal molecules in all the pixel regions of the liquid crystal display device 90 can be formed at a desired angle. Therefore, it is possible to prevent the occurrence of a display defect such as a line defect having a different brightness that occurs on the display screen of the liquid crystal display device 90 during actual driving display.

  The manufacturing method of the liquid crystal display device 90 according to the present embodiment is the same as that of the fourth embodiment except that the polymerization TFTs 71a and 71b are turned on when the monomer mixed in the liquid crystal 45 is polymerized. Since it is the same as that of the liquid crystal display device 80 according to FIG.

The present invention is not limited to the above embodiment, and various modifications can be made.
In the liquid crystal display devices 1, 50, and 70 according to the first to third embodiments, adjacent drain bus lines are electrically connected to each other by the superposition TFT, but the present invention is not limited to this. Each of the coupling capacitance formed by the drain bus line, the common electrode 21 and the liquid crystal sandwiched between them, and the coupling capacitance formed by the drain bus line, the storage capacitor bus line and the insulating film sandwiched therebetween. The capacitance value only needs to be larger than each capacitance value of the coupling capacitance of the conventional liquid crystal display devices 101 and 201. Therefore, the superposition | polymerization TFT should just be formed so that at least 2 or more drain bus lines may be conduct | electrically_connected. For example, in FIG. 1, even if the superposition TFT 29b is not formed, the drain bus lines 9a and 9b are conducted by the superposition TFT 29a, and the drain bus lines 9c and 9d are conducted by the superposition TFT 29c. The same effect as the form can be obtained.

  In the liquid crystal display device 50 according to the second embodiment, the gate bus lines are electrically connected to each other by the superposition TFT formed between the adjacent gate bus lines, but the present invention is not limited to this. For example, the superposition TFT may be formed so that at least two or more gate bus lines can be connected to each other. Also in this case, the same effect as the above embodiment can be obtained.

  In the liquid crystal display devices 50 and 70 according to the second and third embodiments, the control wirings 59 and 61 are connected to the control wiring 31, respectively, but the present invention is not limited to this. For example, the control wirings 59 and 61 are not connected to the control wiring 31 but connected to different input terminals so that the second polymerization TFT and the third polymerization TFT can be independently controlled on / off. May be. Also in this case, the same effect as the above embodiment can be obtained.

  In the liquid crystal display devices 80, 85, 90 according to the fourth to sixth embodiments, a storage capacitor is formed by the second pixel electrode, the storage capacitor bus line, and an insulating film sandwiched between them. However, the present invention is not limited to this. For example, in a Cs-on-gate liquid crystal display device in which a gate bus line also serves as a storage capacitor bus line, a storage capacitor may be formed by the second pixel electrode, the gate bus line, and an insulating film sandwiched therebetween. By forming the storage capacitor so as to satisfy Expression (6), the same effect as in the above embodiment can be obtained.

  In the liquid crystal display devices 1, 50, 70, 80, 85, 90 according to the first to sixth embodiments, a polymer is formed by polymerizing polymerizable components mixed in the liquid crystal by irradiating UV light. However, the present invention is not limited to this. For example, even when heat is applied to the liquid crystal to polymerize the polymerizable component to form a polymer, the same effect as in the above embodiment can be obtained.

The liquid crystal display devices and the manufacturing methods thereof according to the first to sixth embodiments described above can be summarized as follows.
(Appendix 1)
A pair of opposed substrates;
Liquid crystal sealed between the pair of substrates and mixed with a polymerizable component;
A plurality of gate bus lines formed on one of the pair of substrates;
A plurality of drain bus lines intersecting the plurality of gate bus lines via an insulating film;
A plurality of gate bus lines; and a thin film transistor formed at each intersection of the plurality of drain bus lines;
A pixel electrode connected to the thin film transistor;
A first control wiring to which a control signal for controlling switching is input when polymerizing the polymerizable component;
A drain electrode connected to one of the two adjacent drain bus lines; a source electrode connected to the other; and a gate electrode connected to the first control wiring; And a first polymerization thin film transistor whose switching is controlled based on the liquid crystal display device.
(Appendix 2)
In the liquid crystal display device according to appendix 1,
A second control wiring to which a control signal for controlling switching is input when polymerizing the polymerizable component;
A drain electrode connected to one of the two adjacent gate bus lines; a source electrode connected to the other; and a gate electrode connected to the second control wiring; A liquid crystal display device comprising a second polymerization thin film transistor whose switching is controlled based on the second thin film transistor.
(Appendix 3)
In the liquid crystal display device according to attachment 2,
A source / drain electrode connected to any one of the plurality of drain bus lines, a drain / source electrode connected to any one of the plurality of gate bus lines, and a gate to which the control signal is input And a first auxiliary thin film transistor for polymerization whose switching is controlled based on the control signal.
(Appendix 4)
In the liquid crystal display device according to any one of appendices 1 to 3,
One of the pair of substrates further has a repair wiring for repairing a disconnection defect of the drain bus line,
A third control wiring to which a control signal for controlling switching is input when polymerizing the polymerizable component;
A source / drain electrode connected to the repair wiring, a drain / source electrode connected to any one of the plurality of drain bus lines, and a gate electrode connected to the third control wiring. And a third polymerization thin film transistor whose switching is controlled based on the control signal.
(Appendix 5)
In the liquid crystal display device according to appendix 4,
One of the pair of substrates has two repair wirings,
A source / drain electrode connected to one of the two repair wirings, a drain / source electrode connected to the other, and a gate electrode to which the control signal is input, and based on the control signal And a second auxiliary thin film transistor for polymerization whose switching is controlled.
(Appendix 6)
A pair of opposed substrates;
Liquid crystal sealed between the pair of substrates;
A plurality of gate bus lines formed on one of the pair of substrates;
A plurality of drain bus lines intersecting the plurality of gate bus lines via an insulating film;
A plurality of gate bus lines; and a thin film transistor formed at each intersection of the plurality of drain bus lines;
A first pixel electrode connected to the thin film transistor;
A liquid crystal display device comprising: a second pixel electrode that forms a predetermined capacitance with an insulating film interposed between the first pixel electrode and the first pixel electrode.
(Appendix 7)
In the liquid crystal display device according to appendix 6,
One of the pair of substrates further includes a plurality of storage capacitor bus lines intersecting the drain bus line via the insulating film, and a common storage capacitor wiring connecting the plurality of storage capacitor bus lines.
When superposing the polymerizable component, a control wiring to which a control signal for controlling switching is input,
A source / drain electrode connected to any one of the common storage capacitor wiring or the plurality of storage capacitor bus lines; a drain / source electrode connected to any one of the plurality of drain bus lines; A liquid crystal display device comprising: a thin film transistor for polymerization having a gate electrode connected to a control wiring and whose switching is controlled based on the control signal.
(Appendix 8)
In the liquid crystal display device according to appendix 6 or 7,
The capacitance value of the predetermined capacitance is a capacitance of the capacitance formed by the gate bus line, the second pixel electrode, and an insulating film sandwiched between the gate bus line and the second pixel electrode. A liquid crystal display device having a larger value.
(Appendix 9)
In the liquid crystal display device according to appendix 7,
The capacitance value of the predetermined capacitance is the capacitance formed by the storage capacitor bus line, the second pixel electrode, and an insulating film sandwiched between the storage capacitor bus line and the second pixel electrode. A liquid crystal display device having a capacitance value greater than
(Appendix 10)
The liquid crystal display device according to any one of appendices 6 to 9,
One of the pair of substrates has a common electrode,
When polymerizing the polymerizable component, another control wiring to which a control signal for controlling switching is input,
A source / drain electrode connected to the common electrode; a drain / source electrode connected to any one of the plurality of drain bus lines; and a gate electrode connected to the another control wiring. A liquid crystal display device comprising: another thin film transistor for polymerization whose switching is controlled based on the control signal.
(Appendix 11)
Sealing the liquid crystal mixed with a polymerizable component between a pair of substrates arranged opposite to each other,
A plurality of storage capacitor bus lines formed on one of the pair of substrates and a common formed on the other of the pair of substrates while conducting a plurality of drain bus lines formed on one of the pair of substrates. A method for producing a liquid crystal display device, comprising applying a voltage between the electrodes and applying light or heat to polymerize the polymerizable component.
(Appendix 12)
In the method for manufacturing a liquid crystal display device according to appendix 11,
A method of manufacturing a liquid crystal display device, wherein a plurality of gate bus lines intersecting the plurality of drain bus lines via an insulating film are electrically connected.
(Appendix 13)
In the method for manufacturing a liquid crystal display device according to attachment 12,
A method of manufacturing a liquid crystal display device, wherein one of the plurality of drain bus lines is electrically connected to one of the plurality of gate bus lines.
(Appendix 14)
In the manufacturing method according to any one of appendices 11 to 13,
A method of manufacturing a liquid crystal display device, wherein conduction is established between one of the plurality of drain bus lines and a repair wiring intersecting the plurality of drain bus lines with an insulating film interposed therebetween.

1 is a diagram schematically showing a schematic configuration of a liquid crystal display device 1 according to a first embodiment of the present invention. It is a figure which shows the equivalent circuit of the liquid crystal display device 1 by the 1st Embodiment of this invention. It is a figure which shows the equivalent circuit of the liquid crystal display device 50 by the 2nd Embodiment of this invention. It is a figure which shows the equivalent circuit of the liquid crystal display device 70 by the 3rd Embodiment of this invention. It is a figure which shows the equivalent circuit of the liquid crystal display device 80 by the 4th Embodiment of this invention. It is a figure which shows the equivalent circuit of the liquid crystal display device 85 by the 5th Embodiment of this invention. It is a figure which shows the equivalent circuit of the liquid crystal display device 90 by the 6th Embodiment of this invention. It is a figure which shows typically the schematic structure of the conventional liquid crystal display device. It is a figure which shows typically a schematic structure in the conventional liquid crystal display device. It is a figure which shows the equivalent circuit of the conventional liquid crystal display device. It is a figure which shows the equivalent circuit of the conventional liquid crystal display device.

Explanation of symbols

1, 50, 70, 80, 85, 90, 101, 201 Liquid crystal display device 2 TFT substrate 4 Counter substrate 7a, 7b, 7c, 7d, 107a, 107b, 107c, 107d Gate bus lines 8a, 8b, 8c, 8d, 10a, 10b, 10c, 10d, 33, 69, 75 Input terminals 9a, 9b, 9c, 9d, 109a, 109b, 109c, 109d, 109a ′ Drain bus lines 11, 11a, 11b, 111, 111a, 111b, 111c, 111d TFT
13, 13a, 13b, 113, 113a, 113b, 113c, 113d Pixel electrodes 15a, 15b, 15c, 15d, 115a, 115b, 115c, 115d Storage capacitor bus line 17, 117 Common storage capacitor line 19, 119 Common storage capacitor terminal 21, 121 Counter electrode 23, 123 Counter electrode terminal 29a, 29b, 29c, 53a, 53b, 57a, 57b, 65a, 65b, 71a, 71b Polymerization TFT
31, 59, 67, 73 Control wires 35a, 35b, 135a, 135b Repair wires 37a, 37b Connection terminals 39, 41 Glass substrate 43, 47 Vertical alignment film 45 Liquid crystal 49 Color filter resin layer 51 Spherical spacers 55, 58 Auxiliary TFT for polymerization
63a, 63b First pixel electrode 64a, 64b Second pixel electrode 125 Connection wiring 127 Gate bus line drive circuit 129 Drain bus line drive circuit

Claims (3)

A pair of opposed substrates;
Liquid crystal sealed between the pair of substrates and mixed with a polymerizable component;
A plurality of gate bus lines formed on one of the pair of substrates;
A plurality of drain bus lines intersecting the plurality of gate bus lines via an insulating film;
A plurality of gate bus lines; and a thin film transistor formed at each intersection of the plurality of drain bus lines;
A pixel electrode connected to the thin film transistor ;
A drain electrode connected to one of the two contact next to the drain bus line, a source electrode connected to the other, a first polymerization thin film transistor for chromatic and Gate electrodes,
And a first control wiring connected to the gate electrode and to which a control signal for controlling switching of the first polymerization thin film transistor is input when the polymerizable component is polymerized. Display device. The liquid crystal display device according to claim 1 .
A drain electrode connected to one of the two contact next to the gate bus line, a source electrode connected to the other, and a second polymerization thin film transistor for chromatic and Gate electrodes,
A second control wiring connected to the gate electrode of the second polymerization thin film transistor and to which a control signal for controlling switching of the second polymerization thin film transistor is input when polymerizing the polymerizable component; A liquid crystal display device comprising: The liquid crystal display device according to claim 1 or 2,
One of the pair of substrates further has a repair wiring for repairing a disconnection defect of the drain bus line ,
A source / drain electrode connected to the front Symbol repair wiring, and the drain / source electrode connected to one of said plurality of drain bus lines, the third polymerization thin film transistor for chromatic and Gate electrode and,
A third control wiring connected to the gate electrode of the third polymerization thin film transistor, to which a control signal for controlling switching of the third polymerization thin film transistor is input when polymerizing the polymerizable component; A liquid crystal display device comprising:

Images