JP4459928B2 - PLL synthesizer - Google Patents

Description

The present invention relates to a PLL synthesizer The used for transmitting and receiving device.

  FIG. 6 shows a configuration example of a conventional integer frequency division type PLL synthesizer (Non-Patent Document 1). In FIG. 6, an integer frequency division type PLL synthesizer includes a reference oscillator 1, a reference frequency divider 2, a phase comparator 3, a loop filter 4, a voltage controlled oscillator (VCO) 5, a frequency divider that outputs a highly accurate reference frequency signal. It is composed of a variable integer frequency divider 6A having a variable circumferential ratio and an integer.

  The output signal of the voltage controlled oscillator 5 is branched and input to the variable integer frequency divider 6A, and frequency-divided and fed back as one input of the phase comparator 3. The reference frequency signal output from the reference oscillator 1 is frequency-divided by the reference frequency divider 2 and provided as the other input of the phase comparator 3. The phase comparator 3 compares the phases of the two input signals, gives the output signal to the voltage controlled oscillator 5 via the loop filter 4, and controls the oscillation frequency to correspond to the reference frequency.

In the PLL synthesizer having such a configuration, it is necessary to increase the output frequency of the reference frequency divider 2 in order to shorten the pull-in time. Here, the initial output frequency of the reference frequency divider 2 is set to fr = Δf, and the frequency dividing ratios taken by the variable integer frequency divider 6A are..., N−1, N, N + 1,.
Then, the output frequency of the voltage controlled oscillator 5 after the pull-in is
..., (N-1)? F, N? F, (N + 1)? F, ...
Thus, there are frequency channels with an interval Δf.

In order to shorten the pull-in time, the output frequency of the reference frequency divider 2 is set to fr = LΔf which is L times (L is an integer), and the frequency division ratio taken by the variable integer frequency divider 6A is ..., N / L-1 , N / L, N / L + 1,.
Then (N / L is an integer), the output frequency of the voltage controlled oscillator 5 after the pull-in is
..., (N-L) Δf, NΔf, (N + L) Δf, ...
It becomes. At this time, since the frequency changes with the interval LΔf, there is a frequency channel that cannot be used for the frequency channel with the interval Δf, and there is a problem that the convergence time cannot be necessarily shortened.

  FIG. 7 shows a configuration example of a conventional fractional frequency division (fractional N) PLL synthesizer. The difference from the integer frequency division type PLL synthesizer shown in FIG. 6 is that a variable fractional frequency divider 6B is used instead of the variable integer frequency divider 6A.

The output frequency of the reference frequency divider 2 is set to fr = LΔf which is L times (L is an integer), and the division ratios taken by the variable fractional divider 6B are N / L, (N + 1) / L, (N + 2) / L , ...
Then, the output frequency of the voltage controlled oscillator 5 after the pull-in is
NΔf, (N + 1) Δf, (N + 2) Δf,...
Since the frequency changes at the interval Δf, all frequency channels can be used.

  FIG. 8 shows a configuration example of the variable fractional frequency divider 6B. In FIG. 8, the variable fractional frequency divider 6 </ b> B is configured using a variable frequency divider 61 and an accumulator (ACC) 62. The accumulator 62 receives the reference frequency signal from the reference frequency divider 2 as a clock, increments by n for each clock, outputs an overflow signal when the content exceeds m, and divides the variable frequency divider 61. Switch the ratio from N to N + 1.

That is, in the accumulator 62, the content after α clocks are input is αn. Here, it is an integer having a relationship of α> 1, n ≧ 0, m> n. When αn ≧ m, the accumulator 62 outputs an overflow signal, sets the frequency division ratio of the variable frequency divider 61 to N + 1, and simultaneously sets the content to αn−m, and again increments every clock. As described above, since the accumulator 62 overflows n times during m clocks, the frequency dividing ratio of the variable frequency divider 61 is N + 1 for n times during m clocks and N for the remaining (mn) times. Therefore, the average frequency division ratio per clock of m clocks is
((N + 1) n + N (mn)) / m = N + n / m
It becomes. Here, since m> n, n / m <1.

For example, if m = 8 and n = 3, the contents of the accumulator 62 are accumulated as 3 and 6 for each clock input. At the next clock input, it becomes 9, but at this time, an overflow occurs, and the accumulation operation is continued with the remaining 1 minus 8 being the initial value. As a result, the contents of the accumulator 62 are
3, 6, 1 , 4, 7, 2 , 5, 0 , 3, ...
And causes three overflows, underlined for 8 clocks. The variable frequency divider 61 changes the frequency division ratio from N to N + 1 according to the overflow signal. Therefore, the frequency division ratio is N + 1 3 times in 8 clocks and N is 5 times, so the average frequency division ratio is N + 3/8.

  As described above, the fractional frequency division type (fractional N) PLL synthesizer can increase the output frequency of the reference frequency divider 2 without increasing the variable frequency step width, so that the pull-in time can be shortened.

  However, in this method, since the output of the phase comparator 3 changes with a periodicity of m clocks, the control voltage of the voltage controlled oscillator 5 has a periodicity, and the output of the voltage controlled oscillator 5 causes spurious. This spurious is undesirable because it causes interchannel interference in a steady state where the frequency of the PLL synthesizer is constant.

  As a method of reducing this spurious, a phase error diffusion circuit shown in FIG. 9 is used (Non-Patent Documents 2 and 3). In FIG. 9, accumulators (ACC) 62-1 to 62-4 are connected in cascade, and overflow signals OVF1 to OVF4 are input to adder 64 directly or via delay element (τ) 63, and the adders are added. 64 outputs are supplied to the variable frequency divider 61. Here, the delay element 63 delays the signal by one clock.

  When an overflow occurs, the first-stage ACC 62-1 sets the frequency division ratio to +1 in one clock. The ACC 62-2 in the second stage sets the division ratio to +1 by OVF2 generated as a result of accumulating the output a1 of the ACC 62-1 every clock, and -1 in the next clock. The ACC 62-3 in the third stage accumulates the output a2 of the ACC 62-2 and sets it to +1 at OVF3, -2 at the next clock, and +1 at the next clock. The ACC 62-4 in the fourth stage accumulates the output a3 of the ACC 62-3 and sets it to +1 by OVF4, -3 by the next clock, +3 by the next clock, and -1 by the next clock.

Upon receiving these signals, the adder 64 sets the sum of the frequency division ratio N and the frequency division ratio change to the frequency division ratio of the variable frequency divider 61. As a result, the frequency division ratio changes frequently, the frequency component due to the frequency division ratio change is diffused in the high frequency range, and the spurious in the low frequency range is reduced. Although the accumulator has four stages here, the spurious in the low frequency region can be reduced by connecting the accumulators in more stages. The relationship between the number of stages of the accumulator and the change in the division ratio is expressed by z ^k (0) when (1-z) ⁱ , i = (number of stages of accumulator−1) represented by a Pascal triangle in FIG. ≦ k ≦ i).
B. Razavi, "Design of analog CMOS integrated circuits", McGrow-Hill, pp.532-576, Aug.2001 Nobuo Iizuka, Jun Yamakawa, "Local Oscillator and Synthesizer", Transistor Technology SPECIAL, No.47, pp.36-53 Toshifumi Adachi, et al., "High-speed frequency switching synthesizer using fractional frequency division", IEICE Transactions C-1, Vol.J76-C-1, No.11, pp.445-452, 1993 11 Moon

  To summarize the above prior art, a PLL synthesizer using a fractional frequency divider can increase the output frequency of the reference frequency divider without increasing the variable frequency step width, thus shortening the pull-in time and starting up quickly. Can be realized. However, there is a problem that the output is spurious due to the periodicity of the control voltage of the voltage controlled oscillator. On the other hand, a circuit configuration using a phase error diffusion circuit to reduce spuriousness has a problem that although a spurious reduction effect can be expected, a large-scale circuit configuration is required and power consumption increases. As described above, there is no conventional PLL synthesizer that simultaneously satisfies the following three points: (1) high-speed startability, (2) low power consumption, and (3) low spurious property in a steady state.

The present invention aims quick start property, low power consumption, to provide a PLL synthesizer THE capable of satisfying low spurious simultaneously in a steady state.

In the PLL synthesizer according to the first aspect of the present invention, the variable frequency divider includes a variable integer frequency divider whose integer frequency division ratio is an integer, and a variable fractional number whose average frequency division ratio per clock is represented by a fraction. This is a switching type variable frequency divider that has a function as a frequency divider and includes means for switching the functions of the two frequency dividers according to an external switching signal. The reference frequency divider is divided by an external switching signal. A switchable reference frequency divider capable of switching the frequency ratio, making the switchable variable frequency divider function as a variable fractional frequency divider, and the frequency of the output signal of the switchable reference frequency divider being the output of the voltage controlled oscillator A fractional frequency division mode in which the frequency division ratio is set to be larger than the frequency channel interval of the signal, and the switchable variable frequency divider functions as a variable integer frequency divider, and the output signal of the switchable reference frequency divider The frequency of the output signal of the voltage controlled oscillator Switching between the fractional frequency division mode and the integral frequency division mode according to the input of the synchronization judgment signal of the lock detector, for the integer division mode that sets the division ratio to be equal to the wave number channel interval A switching control circuit is provided for sending a switching signal to be performed to the switching type variable frequency divider and the switching type reference frequency divider.

Lock detector, the control signal Vvco of the voltage controlled oscillator is always inputted to the input terminal, and the unit amplifier circuit which forces out by amplifying the variation ΔVvco control signal Vvco from the output terminal, the variation of the amplified control signal Vvco A unit for determining whether or not the amount ΔVvco is within a predetermined range and outputting a synchronization determination signal when the amount ΔVvco is smaller than the predetermined range , and the unit amplifier circuit has one end connected to the input terminal A capacitor, an input terminal connected to the other end of the capacitor, an output terminal connected to the output terminal, an amplifier connected in parallel between the amplifier input terminal and the output terminal, and the amplifier input terminal and output And a switch for turning on / off the connection between the terminals, and amplifying the fluctuation amount ΔVvco of the control signal Vvco in accordance with the on / off of the switch and outputting the amplified amount to the output terminal . Note that a configuration in which two or more unit amplifier circuits are connected in cascade is also possible.

The PLL synthesizer of the present invention can monitor the fluctuation amount ΔVvco of the control voltage Vvco of the voltage controlled oscillator with a lock detector, and detect that the synchronous pull-in is completed when it falls within a predetermined range.

  In addition, the PLL synthesizer of the present invention detects the completion of synchronous pull-in by the lock detector, and operates as a fractional frequency division type until the transition from the initial state to the steady state, and then operates as an integer frequency division type. Thus, it is possible to realize high-speed startability and low spurious performance in a steady state. In addition, since the switching control can be realized with a simple configuration, low power consumption can also be realized. As a result, the PLL synthesizer of the present invention can simultaneously satisfy high-speed startability, low power consumption, and low spurious performance in a steady state.

(Embodiment of PLL Synthesizer of the Present Invention)
FIG. 1 shows an embodiment of a PLL synthesizer of the present invention. 1, the PLL synthesizer of this embodiment includes a reference oscillator 1 that outputs a highly accurate reference frequency signal, a switchable reference frequency divider 11 that can switch a frequency division ratio, a phase comparator 3, a loop filter 4, Voltage controlled oscillator (VCO) 5, switchable variable frequency divider 12 capable of switching between variable fractional divider and variable integer frequency divider, and control of switching of switchable variable frequency divider 12, and corresponding to the switching Then, the switching control circuit 13 for switching the frequency dividing ratio of the switching type reference frequency divider 11 and the output signal of the loop filter 4 (control voltage Vvco of the voltage controlled oscillator 5) are monitored, and the completion of the synchronous pull-in is determined from the fluctuation. The lock detector 14 is supplied to the switching control circuit 13 as a synchronization determination signal. Note that a frequency divider 7 may be provided at the output stage of the voltage controlled oscillator 5, and the output signal of the voltage controlled oscillator 5 may be divided and extracted.

Here, the frequency of the output signal of the reference oscillator 1 is f _r , and the switching type reference in which the frequency division ratio is set corresponding to the setting of the variable fractional frequency divider or the variable integer frequency divider of the switching type variable frequency divider 12. Assume that the frequency of the output signal of the frequency divider 11 is f _f or f _i (f _f > f _i ), and the frequency of the output signal of the voltage controlled oscillator 5 is f _v .

The basic operation of the PLL synthesizer in this embodiment is the same as that of the conventional configuration. That is, the output signal (f _v ) of the voltage controlled oscillator 5 is branched and input to the switchable variable frequency divider 12, and frequency-divided and fed back as one input of the phase comparator 3. The output signal (reference frequency signal (f _r )) of the reference oscillator 1 is frequency-divided by the switchable reference frequency divider 11 and given as the other input (phase comparison signals (f _f , f _i )) of the phase comparator 3. It is done. The phase comparator 3 compares the phases of the two input signals, gives the output signal to the voltage controlled oscillator 5 via the loop filter 4, and controls it to have a predetermined oscillation frequency.

  A control procedure characteristic of the present embodiment will be described with reference to FIG. The PLL synthesizer according to the present embodiment is configured to operate in a fractional frequency division mode in an activated state until a transition from an initial state (resting state) to a steady state, and to switch to an integer frequency division mode after shifting to a steady state. The switching timing is when the lock detector 14 monitors the control voltage Vvco of the voltage controlled oscillator 5 which is the output signal of the loop filter 4 and the fluctuation amount ΔVvco becomes less than the threshold value Vth. The switching control circuit 13 switches from the fractional frequency division mode to the integer frequency division mode according to the synchronization determination signal that is regarded and output. This will be described in detail below.

First, in the fractional frequency dividing mode (S1 to S3) until the steady state is reached, the switching control circuit 13 sets the frequency dividing ratio of the switching type reference frequency divider 11 to f _r / f _f , and the reference frequency signal (f _A phase comparison signal (f _f ) is generated from _r ). The frequency f _f of the phase comparison signal is larger than the frequency channel interval of the output signal (f _v ) of the voltage controlled oscillator 5. Further, the switching control circuit 13 uses the switching type variable frequency divider 12 as a fractional frequency divider, and the frequency dividing ratio thereof is f _v / f _f = N _v + n / m.
Set to. N _v is an integer, and n / m <1.

  The phase and frequency synchronous pull-in operation is performed from the initial state by the above fractional frequency division mode, and the lock detector 14 monitors the control voltage Vvco of the voltage controlled oscillator 5 which is the output signal of the loop filter 4. Then, the fluctuation amount ΔVvco of the control voltage Vvco is compared with the threshold value Vth, and when ΔVvco <Vth, it is regarded that the synchronization pull-in is completed, and a synchronization determination signal is output, and the switching control circuit 13 starts from the fractional frequency division mode. Transition to frequency division mode.

In the integer frequency division mode (S2, S4, S5), the frequency division ratio of the switchable reference frequency divider 11 is switched to f _r / f _i to generate the phase comparison signal (f _i ) from the reference frequency signal (f _r ). To do. The frequency f _i of the phase comparison signal at this time is equal to the frequency channel interval of the output signal (f _v ) of the voltage controlled oscillator 5. That is, when the lock detection, switching the division ratio of the switching type reference frequency divider 11 to be frequency f _i is equal to the frequency channel spacing frequency is the frequency f _v of the phase comparison signal. Further, the switching control circuit 13 uses the switching variable frequency divider 12 as an integer frequency divider and switches the frequency dividing ratio to f _v / f _i to perform a phase and frequency synchronization operation.

  In the PLL synthesizer of the present invention, as described above, first, the synchronous pull-in operation is performed in the fractional frequency division mode, and the fluctuation amount ΔVvco of the control voltage Vvco of the voltage controlled oscillator 5 is monitored, and the oscillation frequency converges to a constant value. Switch to integer division mode when considered. In this way, the time for the frequency to converge to a constant value can be shortened by operating in the fractional frequency division mode from the initial state to the steady state, and spurious can be generated by operating in the integer frequency division mode in the steady state. Can be suppressed.

  Meanwhile, the lock detector 14 determines whether or not the fluctuation amount ΔVvco of the control voltage Vvco of the voltage controlled oscillator 5 has converged within a predetermined range. Therefore, it is necessary to detect the fluctuation amount ΔVvco of the control voltage Vvco of the voltage controlled oscillator 5 from the output of the loop filter 4 and to compare with the threshold value Vth with high accuracy. It is.

(Configuration example of lock detector 14)
FIG. 3 shows a configuration example of the lock detector 14. In the figure, the lock detector 14 has a configuration in which a plurality of unit amplifier circuits 21-1 to 21-n connected in n stages, a quantizer 22, and a determination circuit 23 are connected in series. The unit amplifier circuit 21 has a configuration in which a capacitor 211 and an amplifier 212 are connected in series between input and output terminals, and a switch 213 is connected in parallel to the amplifier 212. The switch 213 is turned on (closed) in response to the rising (or falling) of the clock φ, and turned off (opened) in response to the falling (or rising) of the clock φ. The generation source of this clock φ is omitted.

  FIG. 4 shows an operation example of the unit amplifier circuit 21 of the lock detector 14. The control voltage Vvco of the voltage controlled oscillator 5 is always input to the unit amplifier circuit 21 through the input terminal, and the difference voltage between the control voltage Vvco and the center voltage Vref of the amplifier 212 is applied to the capacitor 211 when the switch 213 is turned on. Stored. At the timing when the switch 213 is turned off, the difference between the control voltage Vvco when the switch 213 is turned on and the control voltage Vvco when the switch 213 is turned off (variation of the control voltage Vvco) ΔVvco The potential is pushed up, and the amplifier 212 amplifies this potential change and gives it to the unit amplifier circuit 21 in the next stage. Similarly, the control voltage fluctuation amount ΔVvco of the voltage controlled oscillator 5 is amplified and output from the final unit amplifier circuit 21 as a signal Vout.

  The signal Vout is quantized by the quantizer 22, and the value quantized by the determination circuit 23 at the next stage is compared with a predetermined threshold value Vth. The determination circuit 23 determines that synchronization pull-in is complete if the output value of the quantizer 22 is within a threshold value (the fluctuation amount ΔVvco of the control voltage Vvco is within a predetermined value), and determines that synchronization pull-in is not complete if the output value exceeds the threshold value. Then, the corresponding synchronization determination signals are output to the switching control circuit 13.

  The unit amplifier circuit 21 of the lock detector 14 can be configured with only one stage as shown in FIG.

  By using such a lock detector 14, highly accurate lock detection can be realized with a simple configuration. Further, the frequency division mode switching mechanism of the PLL synthesizer that performs switching between the switchable reference frequency divider 11 and the switchable variable frequency divider 12 can be realized with a simple configuration, so that low power consumption, high speed start-up, Low spuriousness in the state can be achieved at the same time.

  The lock detector 14 shown in FIG. 3 or FIG. 5 is not limited to the PLL synthesizer that switches between the fractional frequency division type and the integer frequency division type shown in FIG. 1, but for example, the conventional integer frequency division type PLL synthesizer shown in FIG. Or a conventional fractional frequency division type PLL synthesizer shown in FIG. 7 or the like, and can be used as a means for detecting a synchronous pull-in state of a more general phase locked loop (PLL).

The figure which shows embodiment of the PLL synthesizer of this invention. The flowchart which shows the control procedure characterized by the PLL synthesizer of this invention. The figure which shows the structural example of the lock | rock detector 14. FIG. The figure which shows the operation example of the lock | rock detector 14. FIG. The figure which shows the other structural example of the lock | rock detector. The figure which shows the structural example of the conventional integer frequency division type PLL synthesizer. The figure which shows the structural example of the conventional fractional frequency division type PLL synthesizer. The figure which shows the structural example of the PLL synthesizer which comprised the variable fractional frequency divider with the accumulator. The figure which shows the structural example of the variable fractional frequency divider using a phase error diffusion circuit. The figure which shows the change of the number of stages of an accumulator, and a frequency division ratio.

Explanation of symbols

1 Reference Oscillator 2 Reference Divider 3 Phase Comparator 4 Loop Filter 5 Voltage Controlled Oscillator (VCO)
6A Variable integer frequency divider 6B Variable fractional frequency divider 7 Frequency divider 11 Switchable reference frequency divider 12 Switchable variable frequency divider 13 Switching control circuit 14 Lock detector 21 Unit amplifier circuit 211 Capacitor 212 Amplifier 213 Switch 22 Quantum Generator 23 Judgment circuit 61 Variable frequency divider 62 Accumulator (ACC)
63 Delay element (τ)
64 adder

Claims (2)

A voltage-controlled oscillator that outputs a signal having an oscillation frequency corresponding to the input control signal;
A variable frequency divider for branching and inputting the output signal of the voltage controlled oscillator, dividing the output signal by a variable division ratio, and outputting it,
A reference oscillator that outputs a high-precision reference frequency signal;
A reference frequency divider for dividing and outputting the reference frequency signal by a predetermined frequency division ratio;
A phase comparator for inputting the output signal of the reference frequency divider and the output signal of the variable frequency divider to perform phase comparison, and outputting the phase difference signal;
A loop filter that smoothes the phase difference signal and provides the voltage controlled oscillator as the control signal;
An output signal of the voltage controlled oscillator with respect to an output signal of the reference frequency divider by a phase locked loop (PLL) configuration that feeds back an output signal of the voltage controlled oscillator to the phase comparator via the variable frequency divider In a PLL synthesizer that pulls in the frequency and phase of
The variable frequency divider has a function as a variable integer frequency divider whose integer frequency division ratio is an integer and a variable fraction frequency divider whose average frequency division ratio per clock is represented by a fraction. A switching type variable frequency divider including means for switching the functions of the two frequency dividers by a switching signal;
The reference frequency divider is a switching type reference frequency divider capable of switching a frequency division ratio by a switching signal from the outside,
The control signal Vvco of the voltage controlled oscillator is monitored to determine whether the variation ΔVvco is larger or smaller than a predetermined range, and is synchronized when the variation ΔVvco of the control signal becomes smaller than the predetermined range. A lock detector that outputs a determination signal;
The switchable variable frequency divider is made to function as the variable fractional frequency divider, and the frequency of the output signal of the switchable reference frequency divider is made larger than the frequency channel interval of the output signal of the voltage controlled oscillator. A fractional frequency dividing mode for setting a frequency ratio, the switching variable frequency divider functioning as the variable integer frequency divider, and the frequency of the output signal of the switching type reference frequency divider is an output signal of the voltage controlled oscillator Switching between the fractional frequency division mode and the integer frequency division mode according to the input of the synchronization determination signal for the integer frequency division mode in which the frequency division ratio is set to be equal to the frequency channel interval of Bei give a switching control circuit for delivering to the switching type variable frequency divider and the switching type reference divider switching signal,
The lock detector is
A unit amplifying circuit that constantly inputs a control signal Vvco of the voltage controlled oscillator to an input terminal and amplifies and outputs a fluctuation amount ΔVvco of the control signal Vvco from an output terminal;
Determination means for determining whether or not a fluctuation amount ΔVvco of the amplified control signal Vvco is within a predetermined range, and outputting the synchronization determination signal when the fluctuation amount is smaller than the predetermined range;
The unit amplifier circuit includes:
A capacitor having one end connected to the input terminal;
An amplifier having an input terminal connected to the other end of the capacitor and an output terminal connected to the output terminal;
A switch connected in parallel with the amplifier between an input end and an output end of the amplifier, and a switch for turning on and off a connection between the input end and the output end of the amplifier;
A PLL synthesizer having a configuration in which a fluctuation amount ΔVvco of the control signal Vvco is amplified and output to the output terminal in accordance with on / off of the switch . The PLL synthesizer of claim 1.
A PLL synthesizer having a configuration in which the unit amplifier circuits are cascaded in two or more stages.

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