JP4473293B2 - Semiconductor device input / output circuit - Google Patents

Description

  The present invention relates to an input / output circuit of a semiconductor device, and more particularly to an output portion of an input / output circuit including a tolerant circuit capable of handling an internal power supply voltage, for example, an external power supply voltage higher than a 3V power supply specification, for example, 5V input.

  The power supply voltage of the semiconductor integrated circuit is changing from 5V to 3V or 3.3V, but in the transition period, 5V drive elements and 3V drive elements are mixed. In such a case, even if the element itself is driven at 3V, a voltage of 5V may be applied from the outside, and in this case, the reliability of the MOS transistor constituting the output buffer circuit of the input / output circuit is increased. There is a problem that it is not secured.

  In order to solve such a problem, an input / output circuit (3V / 5V tolerant circuit) with a protection circuit as shown in FIGS. 1 and 2 is conventionally known.

  FIG. 1 shows the overall configuration of an output buffer circuit portion of an input / output circuit, and a control signal is applied to one input of a NAND circuit 1 via an inverter 3. An output signal I1 is given to the other input of the NAND circuit 1. A PI signal to be output from the NAND circuit 1 to an output P-channel MOS (PMOS) transistor constituting the high (Hi) side output circuit section of the output circuit 5 incorporating the tolerant is output.

  On the other hand, a control signal is given to one input of the NOR circuit 2. An output signal I1 is given to the other input of the NOR circuit 2. The NOR circuit 1 outputs an NI signal to be supplied to an output N-channel MOS (NMOS) transistor that constitutes a low-side output circuit section of the output buffer circuit 5 incorporating a tolerant. Then, an output from the output buffer circuit 5 is given to the output terminal unit 6.

  FIG. 2 shows a specific configuration example of the output buffer circuit 5 of the input / output circuit including the tolerant circuit. As shown in FIG. 2, a transistor constituting a tolerant is provided between the gate of the output PMOS transistor 52 and the PI node. That is, three PMOS transistors 51, 53, and one NMOS transistor 56 are provided between the PI node and the output PMOS transistor 52. An internal power supply voltage (intVCC) is applied to the gates of the NMOS transistor 56 and the PMOS transistor 54 and to the drain of the PMOS transistor 53. The gates of the PMOS transistors 51 and 53 are connected to the output node via an N-well resistor 58. The drain of the PMOS transistor 54 is connected to the output node. The PMOS transistor 51 functions as an analog switch.

  An NMOS transistor 55 is provided between the output PMOS transistor 52 and the output NMOS transistor 57, and an internal power supply voltage (intVCC) is applied to the gate of the NMOS transistor 55. An internal power supply voltage is applied to the source of the output PMOS transistor 52, and the source of the output NMOS transistor 57 is grounded. A connection node (output node) between the NMOS transistor 55 and the output PMOS transistor 52 is connected to the output terminal unit 6.

  Table 1 shows the relationship between the control signal of the input / output circuit shown in FIGS. 1 and 2 and the output of each node. The output terminal unit 6 is in a Hi-Z (high impedance) state in which the Hi, Low, and output buffer circuits are not used. In Table 1, Hi is 3V and Low is 0V.

  Next, the case where a high voltage of 5 V is applied from the output terminal section 6 in the output buffer circuit of FIG. Since the circuit of FIG. 2 is an output buffer circuit, when a signal is input from the output terminal unit 6, the output signal itself is not driven, so that the PI node is Hi (3V) and the NI node is Low (0V). It has become.

  First, since the NMOS transistor 55 is provided on the NMOS transistor side, the voltage between the source and drain of each NMOS transistor is lowered, and reliability is ensured.

  Next, on the PMOS transistor side, the PMOS transistor 53 is turned off, and current flows from the drains of the output PMOS transistor 52 and the PMOS transistor 54 to the back gate instead. As a result, the substrate potential (N-well potential) of the PMOS transistor becomes 5V, and the reliability of the PMOS transistors 51 and 53 is ensured. Further, since the PMOS transistor 54 is provided, the gate potential of the output PMOS transistor 52 becomes 5V, and the reliability of the PMOS transistor 52 is ensured. In addition, since the PMOS transistor 51 is in the OFF state, the potential of 5V is not transmitted to the PI node side (because it becomes 3V-Vth (threshold voltage) by the NMOS transistor 56), and the reliability of the circuit connected to the tip of the PI node. Is also secured.

  However, when the semiconductor device incorporating the output buffer circuit of FIG. 2 was mounted on an actual machine and evaluated, there was a problem in a configuration in which an external pull-down resistor was provided in the output terminal section 6. . That is, it has been found that there is a problem in the AC characteristics when the output terminal unit 6 is changed from the normal output (0 to 3V use) output H to Hi-Z that does not use the output buffer circuit 5, that is, the terminal floating. . In the end, the output terminal section 6 drops to Low (0 V) by a pull-down resistor.

  Specifically, as shown in FIG. 2, when the output terminal unit 6 changes from H to Hi-Z (when the terminal is floating), the PMOS transistor 51 as an analog switch is not completely turned on (ON). The gate potential of the PMOS transistor 52 becomes about 3V-Vth (transistor threshold voltage), and a leak current flows between the source and drain of the PMOS transistor 52. As a result, an incomplete OFF state of the PMOS transistor 52 exists as shown in FIG. For example, if the threshold voltage (Vth) of the transistor is about −0.6 V, the PMOS transistor 51 exceeds Vth (about −0.6 V) completely when the output terminal 6 changes from H to Hi-Z. The transition time until turning on (ON) is long. Further, during this period, the gate potential of the output PMOS transistor 52 becomes 3 V-Vth (about 2.4 V), and the leakage current flowing through the PMOS transistor 52 is also large. Therefore, there is a problem that the incomplete OFF time of the PMOS transistor 52 shown in FIG. Finally, the pull-down resistor connected to the output terminal unit 6 wins and becomes L (0 V), but its AC characteristic becomes a problem.

  This defect is a condition that a pull-down resistor is attached to the output terminal unit 6, but if the conventional circuit is used as it is, a serious defect in the system is caused.

  Various circuits have been proposed for an input circuit including a tolerant circuit. For example, a 5V tolerant input circuit that reduces the power consumption of the input buffer and improves the reliability has been proposed (see, for example, Patent Document 1).

However, in these input circuits, there is no mention of a problem when a pull-down resistor is attached to a terminal.
Japanese Patent Laid-Open No. 10-135818

  As described above, in the output buffer circuit including the conventional tolerant circuit, although a condition that the pull-down resistor is attached to the terminal is used, a serious result is caused on the system.

  The present invention has been made in view of the above-described problems, and it is an object of the present invention to improve the AC characteristics and suppress the occurrence of problems even when a pull-down resistor is provided in the output terminal portion. .

  The present invention comprises a terminal portion connected to an external signal line having a voltage higher than the semiconductor internal power supply voltage, a floating N well, a plurality of P-channel transistors and an analog switch, and outputs a semiconductor internal signal to the outside. The analog switch includes a high-side output circuit unit and a low-side output circuit unit in which a plurality of N-channel transistors are connected in series and outputs a semiconductor internal signal to the outside, and a gate is connected to the terminal unit. The threshold voltage of the P-channel transistor is set lower than the threshold voltages of other transistors.

  The threshold voltage of the P-channel transistor constituting the analog switch can be set by adjusting the implantation of the threshold control impurity.

  Further, the channel length of the P-channel transistor constituting the analog switch may be made shorter than the channel length of the other transistor, and the threshold voltage may be set lower than the threshold voltage of the other transistor.

  According to the configuration described above, since a transistor having a low threshold voltage (Vth) is used as a P-channel transistor as an analog switch, the transition time until the PMOS transistor as an analog switch exceeds the threshold voltage and is turned on is short. Become. As a result, the incomplete off (OFF) time of the output PMOS transistor can be shortened. Therefore, even when an external pull-down resistor is attached to the terminal, the voltage can be immediately dropped from the H level to the L level. Further, it can be configured by using only a P-channel transistor having a lower threshold voltage than usual, and the incomplete OFF time can be shortened without increasing the circuit scale.

  The present invention also includes a terminal portion connected to an external signal line having a voltage higher than the semiconductor internal power supply voltage, a floating N well, a plurality of P-channel transistors and an analog switch, and the semiconductor internal signal is transmitted to the outside. A high-side output circuit section for outputting, and a low-side output circuit section for connecting a plurality of N-channel transistors connected in series to output a semiconductor internal signal to the outside, and a gate of the P-channel transistor constituting the analog switch A dummy drive control circuit is provided between the node of the high-side output circuit unit and the gate of the output transistor of the low-side output circuit unit. The dummy drive control circuit is connected to the high-side output circuit unit and the low-side output circuit unit. When both of the side output circuit sections transition to the off state, they are driven for a certain time.

  Further, the dummy drive control circuit includes a one-shot pulse generation circuit that generates a one-shot pulse at the rise of the output of the node of the high-side output circuit unit, and an output from the one-shot pulse generation circuit and a low-side output circuit unit OR gates to which outputs from the output nodes are given.

  According to the configuration described above, when the terminal portion changes from Hi to Hi-Z, the AC characteristics are improved by performing dummy driving to the low side for a certain period of time using the low-side output circuit portion and the dummy drive control circuit. can do. Further, the leakage current flowing through the high-side output circuit portion in the incompletely off state can be reduced.

  As described above, according to the present invention, the incomplete OFF time of the output transistor can be shortened, and the AC characteristics can be improved as compared with the conventional circuit.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 4 is a circuit diagram showing an output buffer circuit according to the first embodiment of the present invention. In addition, the same code | symbol is attached | subjected to the same component as the structure of FIG.

  As shown in FIG. 4, the output buffer circuit 5 of the present invention is provided with a transistor constituting a tolerant between the gate of the output PMOS transistor 52 and the PI node. That is, three PMOS transistors 51a, 53, and 54 and one NMOS transistor 56 are provided between the PI node and the output PMOS transistor 52. An internal power supply voltage (intVCC) is applied to the gates of the NMOS transistor 56 and the PMOS transistor 54 and to the drain of the PMOS transistor 53. The gates of the PMOS transistors 51 a and 53 are connected to the output node via the N-well resistor 58. The drain of the PMOS transistor 54 is connected to the output node. The PMOS transistor 51a functions as an analog switch. In the present invention, the threshold voltage (Vth) of the PMOS transistor 51a is configured to be a transistor (Low (low) −Vth) lower than the threshold voltage (Vth) of another normal transistor. For example, if the threshold voltage (Vth) of a normal transistor is about -0.6V, the threshold voltage (Vth) of the PMOS transistor 51a is set to about -0.3V, which is lowered by -0.3V (ΔVth). Yes.

  An NMOS transistor 55 is provided between the output PMOS transistor 52 and the output NMOS transistor 57, and an internal power supply voltage (intVCC) is applied to the gate of the NMOS transistor 55. An internal power supply voltage is applied to the source of the output PMOS transistor 52, and the source of the output NMOS transistor 57 is grounded. A connection node (output node) between the NMOS transistor 55 and the output PMOS transistor 52 is connected to the output terminal unit 6.

  The above-described method of configuring the PMOS transistor 51a as a (Low-Vth) transistor can be realized by controlling the implantation of threshold control impurities in the process, that is, the Vth implantation. In general, in addition to the Vth injection of the normal transistor, the Vth injection dedicated to the Low-Vth transistor may be performed.

  As described above, since the Low-Vth transistor is used as the PMOS transistor 51a, the transition time until the PMOS transistor 51a exceeds the threshold voltage (about −0.3V) and is completely turned on (ON) is short. Become. Further, as shown in FIG. 5, the gate potential of the output PMOS transistor 52 is also 3 V-Vth (about 2.7 V) during this period, and the leakage current flowing between the source and drain of the output PMOS transistor 52 is small.

  In FIG. 6, a pull-down resistor is provided in the output terminal section 6, and the output PMOS transistor 52 in the conventional circuit when the output terminal section 6 changes from H to Hi-Z (when the terminal is floating) and the circuit of the present invention. Indicates an incomplete OFF state.

  As described above, the transition time until the PMOS transistor 51a exceeds the threshold voltage (about −0.3V) and is completely turned on (ON) is shortened. During this period, the gate potential of the output PMOS transistor 52 is also 3 V-Vth (about 2.7 V), and the leakage current flowing between the source and drain of the output PMOS transistor 52 is small. Therefore, as shown in FIG. 6, when the waveform B of the present invention is compared with the waveform A of the conventional circuit, the time (a, b) of the incomplete OFF state becomes shorter.

  FIG. 7 is a circuit diagram showing an output buffer circuit according to a second embodiment of the present invention. In addition, the same code | symbol is attached | subjected to the same component as the structure of FIG. 4, and a different structure is demonstrated here.

  In the embodiment shown in FIG. 4 described above, the PMOS transistor 51a is configured to be a Low-Vth transistor by controlling the Vth injection in the process. On the other hand, in the embodiment shown in FIG. 7, the actual threshold voltage (Vth) is lowered by intentionally setting the short channel state by shortening the transistor length of the PMOS transistor 51b. The short channel effect generally refers to a phenomenon in which the actual threshold voltage (Vth) decreases as the transistor length decreases. As shown in FIG. 8, when the channel length is shortened, the threshold voltage decreases. In the second embodiment, the PMOS transistor 51b is set to have a channel length in which the threshold voltage is lowered by ΔVth (about −0.3V) from the normal transistor.

  As a result, the same characteristics as in the first embodiment can be obtained without using the process option of the Low-Vth transistor.

  The third embodiment of the present invention will be described below. FIG. 9 is a circuit diagram showing an output buffer circuit according to a third embodiment of the present invention. In addition, the same code | symbol is attached | subjected to the same component as the structure of FIG.

  As shown in FIG. 9, the output buffer circuit 5 according to the third embodiment is provided with a transistor constituting a tolerant between the gate of the output PMOS transistor 52 constituting the high (Hi) side output section and the PI node. It has been. That is, three PMOS transistors 51, 53, and one NMOS transistor 56 are provided between the PI node and the output PMOS transistor 52. An internal power supply voltage (intVCC) is applied to the gates of the NMOS transistor 56 and the PMOS transistor 54 and to the drain of the PMOS transistor 53. The gates of the PMOS transistors 51 and 53 are connected to the output node via the N well resistor 58. The drain of the PMOS transistor 54 is connected to the output node. The PMOS transistor 51 functions as an analog switch.

  Also, the output NMOS transistor 57 constituting the low (Lo) side output unit is connected to the output PMOS transistor 52 via the NMOS transistor 55. An internal power supply voltage (intVCC) is applied to the gate of the NMOS transistor 55. An internal power supply voltage is applied to the source of the output PMOS transistor 52, and the source of the output NMOS transistor 57 is grounded. A connection node (output node) between the NMOS transistor 55 and the output PMOS transistor 52 is connected to the output terminal unit 6.

  The gate of the output NMOS transistor 57 of the low-side output circuit unit and the PI node of the high-side output circuit unit are connected via a dummy drive control circuit 60. The output of the NI node of the low-side output unit is also supplied to the gate of the output NMOS transistor 57 of the low-side output unit via the dummy drive control circuit 60.

  The dummy drive control circuit 60 controls the low-side output circuit unit having a drive capability stronger than the pull-down resistance to drive for a certain time when the terminal unit 6 changes from Hi to Hi-z. . That is, as shown in the waveform diagram of the circuit of FIG. 10, when the terminal unit 6 changes from Hi to a Hi-Z (high impedance) state in which the output buffer circuit is not used, the output of the PI node becomes Hi, Output remains low. The signal NE output from the dummy drive control circuit 60 generates a signal for driving the low-side output circuit unit for a certain period of time as surrounded by the broken line A in FIG. 10 due to the transition of the output of the PI node to Hi. This is applied to the gate of the output transistor 57. By this signal, the low-side output circuit section having a driving capability stronger than the pull-down resistance is driven for a certain time, and the potential of the terminal section 6 rapidly decreases. As a result, the PMOS transistor 51 constituting the analog switch exceeds Vth (about −0.6 V) and is completely turned on (ON) earlier than that shown in FIG. As shown in the waveform of FIG. 11, the incomplete off (OFF) time of the output PMOS transistor 52 can be shortened.

  Further, when the gate potential of the output PMOS transistor 52 becomes 3V and the PMOS transistor 52 is completely turned off (OFF), the gate potential of the PMOS transistor 52 becomes 3V-Vth (about 2.4V) during this period. Leakage current flowing between the source and drain of the transistor 52 can also be reduced.

  FIG. 12 shows a specific circuit example of the dummy drive control circuit 60 in the third embodiment. Since the configuration other than the specific configuration of the dummy drive control circuit 60 is the same as that shown in FIG. 9, the description thereof is omitted here.

  The dummy drive control circuit 60 includes a one-shot pulse generation circuit 61 that generates a one-shot pulse when the output of the PI node of the high-side output circuit section rises, and an output from the one-shot pulse generation circuit 61 and a low-side output circuit section. OR gate 64 to which an output from the NI node is provided. The one-shot pulse generation circuit 61 includes a NAND circuit 62 and odd-numbered inverters 62..., And supplies the output of the PI node and the output of the PI node supplied through the odd-numbered inverters 62. A one-shot pulse is generated when the PI output rises.

  The output signal of the one-shot pulse generation circuit 61 and the signal NI given to the NI node as a normal output signal are given to the OR gate 64, and the NMOS transistor 57 of the low-side output circuit unit is controlled by the output signal NE from the OR gate 64. .

  As an operation, at the time of normal low output, the NMOS transistor 57 of the low-side output circuit unit is operated by a signal from the NI node. When the terminal unit 6 transitions from Hi to a Hi-Z (high impedance) state in which the output buffer circuit is not used, the one-shot generated from the dummy drive control circuit 60 at the rise of the output signal of the PI node. The pulse causes the NMOS transistor 57 of the low-side output circuit section to be dummy-driven for a certain time.

  The dummy drive operation time is determined by the external pull-down resistance value and the drive capability of the low-side output circuit unit, and the time is adjusted by the number of odd-numbered inverters 62.

It is a block diagram which shows the whole structure of an input / output circuit. It is a circuit diagram which shows the output buffer circuit provided with the conventional tolerant. FIG. 3 is a characteristic diagram when the circuit shown in FIG. 2 changes from H to Hi-z when a pull-down resistor is attached to a terminal. 1 is a circuit diagram showing an output buffer circuit including a tolerant according to a first embodiment of the present invention. FIG. It is a characteristic view which shows the relationship between the gate-source voltage and drain current in the output buffer circuit of this invention and the conventional output buffer circuit. In the output buffer circuit of this invention and the conventional output buffer circuit, it is a characteristic view when it changes from H when a pull-down resistor is attached to the output terminal section to Hi-z. It is a circuit diagram which shows the output buffer circuit provided with the tolerant concerning 2nd Embodiment of this invention. It is a characteristic view which shows the relationship between channel length and a threshold voltage. It is a circuit diagram which shows the output buffer circuit provided with the tolerant concerning the 3rd Embodiment of this invention. It is a wave form diagram which shows the operation | movement of 3rd Embodiment of this invention. In the output buffer circuit of 3rd Embodiment of this invention, it is a characteristic view when it changes from H when a pull-down resistor is attached to an output terminal part to Hi-z. It is a circuit diagram which shows the specific example of the output buffer circuit provided with the tolerant concerning the 3rd Embodiment of this invention.

Explanation of symbols

6 terminals 51, 53, 54 PMOS transistor 52 PMOS transistor for output 55, 56 NMOS transistor 57 NMOS transistor for output 60 Dummy drive control circuit

Claims (2)

  A high-side output circuit configured to include a terminal connected to an external signal line having a higher voltage than the semiconductor internal power supply voltage, a floating N-well, a plurality of P-channel transistors and an analog switch, and output a semiconductor internal signal to the outside Part and a low-side output circuit part in which a plurality of N-channel transistors are connected in series and output a semiconductor internal signal to the outside, and a P-channel transistor constituting the analog switch having a gate connected to the terminal part The input / output circuit of the semiconductor device is characterized in that the threshold voltage is set lower than the threshold voltage of the other transistors.   A high-side output circuit configured to include a terminal connected to an external signal line having a higher voltage than the semiconductor internal power supply voltage, a floating N-well, a plurality of P-channel transistors and an analog switch, and output a semiconductor internal signal to the outside And a low-side output circuit unit that outputs a semiconductor internal signal to the outside by connecting a plurality of N-channel transistors in series, and a gate of a P-channel transistor that constitutes the analog switch is connected to the terminal unit A dummy drive control circuit is provided between a node of the high-side output circuit unit and a gate of the output transistor of the low-side output circuit unit, and the dummy drive control circuit includes both a high-side output circuit unit and a low-side output circuit unit. An input / output circuit of a semiconductor device, which is driven for a certain time when the device transits to an off state.

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