JP4503671B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to an insulated gate semiconductor device, and more particularly to a structure of a thin-film insulated gate field effect transistor (TFT) and a manufacturing method thereof.

In recent years, thin film insulated gate field effect transistors (TFTs) have been actively studied.
For example, in Japanese Patent Application Nos. 4-30220 and 4-38637 which are the inventions of the present inventors, aluminum, titanium, chromium, tantalum, and silicon are used as gate electrodes, and the periphery thereof is formed by an anodic oxidation method. A fabrication method and TFT are described that are covered with aluminum oxide, thus eliminating the overlap of the source / drain and gate electrodes, but rather in an offset state, and recrystallizing the source / drain regions by laser annealing.

Such TFTs have excellent characteristics compared to conventional TFTs having no offset and silicon gate TFTs or high melting point metals such as tantalum and chromium as gate electrodes and activated by thermal annealing. However, it has been difficult to obtain the characteristics with good reproducibility.

One of the causes was due to intrusion of mobile ions such as sodium from the outside. This is because there is a risk that sodium may intrude from the outside during the formation of a gate electrode made of a metal material such as aluminum (sputtering or electron beam evaporation is used) and the subsequent anodic oxidation. Especially in the sputtering method, the contamination of sodium was large. However, since the sputtering method is superior in mass productivity to the electron beam evaporation method, it has been desired to be used by all means for cost reduction.

Sodium has been known to be blocked and gettered by phosphor glass or the like. Therefore, the gate insulating film is generally formed of phosphorous glass. However, it has been difficult to produce phosphorous glass at the low temperature that is the object of the above patent. If phosphorous glass is to be produced at such a low temperature, if it is implanted into the gate insulating film of silicon oxide by, for example, ion doping, many defects are generated in the gate insulating film, which deteriorates the characteristics of the TFT. There was something that would let me.

Furthermore, anodic oxidation requires a high voltage of 100 to 300 V, and there is a concern about the breakdown of the gate insulating film. That is, in the technical range shown in the above patent, a gate insulating film is formed on a semiconductor film and a gate electrode is present on the semiconductor film. However, during anodization, a positively charged gate electrode and a floating state are present. As a voltage is generated between the semiconductor film, the anodic oxide film on the gate electrode becomes thicker, and the resistance between the gate electrode and the electrolytic solution increases, it flows from the gate electrode to the electrolytic solution through the gate insulating film and the semiconductor film. The current increases. The gate insulating film may be destroyed due to this current.

The present invention has been made in view of such a current situation. That is, it is an object of the present invention to improve the reliability by preventing the intrusion of mobile ions from the outside and further preventing the breakdown of the gate insulating film.

The insulated gate type semiconductor device of the present invention has at least a semiconductor layer, an insulating film layer, and a gate electrode made of aluminum, chromium, titanium, tantalum, silicon, an alloy thereof, or a multilayer thereof on an insulating substrate. , The insulating film layer is an aluminum oxide single layer,
Silicon oxide single layer, silicon nitride single layer, aluminum nitride single layer, two layers of aluminum oxide layer and silicon nitride layer, two layers of aluminum oxide layer and silicon oxide layer, two layers of silicon nitride layer and silicon oxide layer, or oxidation It consists of three layers, an aluminum layer, a silicon oxide layer, and a silicon nitride layer. For example, a silicon nitride film is interposed between an aluminum gate electrode and a gate insulating film. When the composition of silicon nitride is 1, the ratio of nitrogen is 1 to 4/3, more preferably 1.2 to 4/3.
Between is desirable. Of course, hydrogen or oxygen other than nitrogen and silicon may be added.

Since this silicon nitride film has the effect of blocking mobile ions such as sodium,
Not only has the effect of preventing mobile ions from entering the channel region from the gate electrode and others, but also has better conductivity than silicon oxide, which is a normal gate insulating film, so the gate electrode and the semiconductor region below it An excessive voltage is not applied to the (channel region), and the gate insulating film can be prevented from being broken.

Therefore, a semiconductor region and a gate insulating film are formed, after which the silicon nitride film is formed, and then an aluminum electrode for forming a gate electrode is formed. While the aluminum electrode is anodized, it is desirable that this silicon nitride film is present over the entire surface of the substrate because the anodic potential is maintained substantially constant over the entire surface of the substrate.
The method for manufacturing an insulated gate semiconductor device of the present invention includes a step of forming a semiconductor region on an insulating substrate, and an aluminum oxide single layer, a silicon oxide single layer, a silicon nitride single layer, and an aluminum nitride on the semiconductor region. Single layer, two layers of an aluminum oxide layer and a silicon nitride layer, two layers of an aluminum oxide layer and a silicon oxide layer, two layers of a silicon nitride layer and a silicon oxide layer, or three of an aluminum oxide layer, a silicon oxide layer, and a silicon nitride layer A step of forming an insulating film layer comprising a layer, and a step of forming a metal film mainly composed of aluminum, chromium, titanium, tantalum, silicon, an alloy thereof, or a multilayer thereof on the insulating film layer; And a step of forming an oxide layer on the surface of the metal film through an electric current in an electrolytic solution.
In the insulated gate semiconductor device and the manufacturing method thereof according to the present invention, when the gate electrode (the metal film) is made of an alloy of silicon and aluminum, the gate electrode (the metal film) is made of 0.5 to 3% of silicon. It consists of an added aluminum layer.

As described above, mobile ions can be prevented from entering by forming a silicon nitride film, silicon oxide film, aluminum oxide film, aluminum nitride film, or a multilayer film thereof between the gate electrode and the semiconductor layer (channel region). In addition, it was possible to prevent the gate insulating film from being broken during the anodic oxidation of the gate electrode.

  The following examples illustrate the invention in more detail.

FIG. 1 shows a cross-sectional view of a manufacturing process of this example. The detailed conditions of the present embodiment are almost the same as those of Japanese Patent Application No. 4-30220 or 4-38637 filed by the present inventors, and will not be specifically described in detail. First, N-0 glass manufactured by Nippon Electric Glass Co., Ltd. was used as the substrate 101. Although this glass has a high strain temperature, it contains a lot of lithium and there is also a significant amount of sodium. Therefore, the silicon nitride film 102 having a thickness of 10 to 50 nm is formed by the plasma CVD method or the low pressure CVD method for the purpose of preventing the entry of these movable ions from the substrate. Further, the underlying silicon oxide film 103 was formed by sputtering to a thickness of 100 to 800 nm. On top of that, an amorphous silicon film is applied by plasma CVD.
Only 0 to 100 nm was formed and annealed at 600 ° C. for 12 to 72 hours in a nitrogen atmosphere for crystallization. Furthermore, this is applied to photolithography and reactive ion etching (RIE).
) To form island-like semiconductor regions 104 (for N-channel TFTs) and 105 (for P-channel TFTs) as shown in FIG.

Further, a gate oxide film 106 having a thickness of 50 to 200 nm was deposited by sputtering in an oxygen atmosphere using silicon oxide as a target. Further, a silicon nitride film 107 was deposited by a thickness of 2 to 20 nm, preferably 8 to 11 nm, by plasma CVD or low pressure CVD.

Next, an aluminum film was formed by sputtering or electron beam evaporation, and this was patterned with a mixed acid (phosphoric acid solution to which 5% nitric acid was added) to form gate electrodes / wirings 108-111. In this way, the outer shape of the TFT was adjusted.

Furthermore, aluminum oxide films 112 to 115 were formed by passing an electric current through the gate electrodes / wirings 108 to 111 in an electrolytic solution by an anodic oxidation method. As the conditions for anodization, the method described in Japanese Patent Application No. 4-30220, which is the invention of the present inventors, was employed. The state up to this point is shown in FIG.

Next, an N-type impurity is implanted into the semiconductor region 104 and a P-type impurity is implanted into the semiconductor region 105 by a known ion implantation method, and the N-type impurity region (source, drain) 116 and the P-type impurity region 117 are implanted. Formed. This process used a known CMOS technology. Further, silicon nitride 1 other than that existing under the gate electrode / wiring portion is formed by reactive ion etching.
07 was removed. This process can be substituted by wet etching. In that case, the difference in etching rate between aluminum oxide, which is an anodic oxide film, and silicon nitride can be used to perform self-aligned etching using aluminum oxide as a mask.

In this way, a structure as shown in FIG. 1D was obtained. As a matter of course, the crystallinity of the portion into which the impurity has been implanted is significantly degraded by the previous ion implantation, and is substantially in an amorphous state (an amorphous state or a polycrystalline state close thereto). Therefore, crystallinity was recovered by laser annealing. This step may be performed by thermal annealing at 600 to 850 ° C. For example, the laser annealing conditions described in Japanese Patent Application No. 4-30220 were used. After laser annealing, a hydrogen atmosphere at 250 to 450 ° C. (1 to
Annealing was performed at 700 torr, preferably 500 to 700 torr for 30 minutes to 3 hours, and hydrogen was added to the semiconductor region to reduce lattice defects (such as dangling bonds).

In this way, the shape of the element was adjusted. Thereafter, as usual, an interlayer insulator 118 is formed by sputtering film formation of silicon oxide, an electrode hole is formed by a known photolithography technique, and the surface of the semiconductor region or the gate electrode / wiring is exposed, Finally, the second
A metal coating (aluminum or chromium) is selectively formed, and this is applied to the electrode / wiring 11.
9-121. Here, the second metal wiring 119, over the first metal wiring 108, 111,
121 crosses. As described above, NTFT 122 and PTFT 123 were formed.

FIG. 2 shows a cross-sectional view of a manufacturing process of this example. The detailed conditions of the present embodiment are almost the same as those of Japanese Patent Application No. 4-30220 filed by the present inventors, and will not be specifically described in detail. First, N-0 glass manufactured by Nippon Electric Glass Co., Ltd. was used as the substrate 201, and a silicon nitride film 202 having a thickness of 10 to 50 nm was formed by plasma CVD or low pressure CVD. Further, the underlying silicon oxide film 203 was formed by sputtering to a thickness of 100 to 800 nm. An amorphous silicon film having a thickness of 20 to 100 nm was formed thereon by plasma CVD, and annealed at 600 ° C. for 12 to 72 hours in a nitrogen atmosphere to cause crystallization. Further, this is patterned to form an island-shaped semiconductor region 204 (N channel T) as shown in FIG.
FT) and 205 (P channel TFT) were formed.

Further, a gate oxide film 206 having a thickness of 50 to 200 nm was deposited by sputtering. Further, a silicon nitride film 207 was deposited by a thickness of 2 to 20 nm, preferably 8 to 11 nm, by plasma CVD or low pressure CVD.

Next, an aluminum film was formed by sputtering or electron beam evaporation, and this was patterned to form gate electrodes / wirings 208-211. In this way, the outer shape of the TFT was adjusted as shown in FIG.

Further, aluminum oxide films 212 to 215 were formed by anodizing the current through the gate electrodes and wirings 208 to 211 in the electrolytic solution. As the conditions for anodization, the method described in Japanese Patent Application No. 3-30220 which is the invention of the present inventors was adopted. The state up to this point is shown in FIG.

Next, as shown in FIG. 2C, the silicon nitride 207 and the silicon oxide 206 other than those existing under the gate electrode / wiring portion are removed by reactive ion etching, and the semiconductor regions 204 and 205 are exposed. I let you. This process can be substituted by wet etching. In that case, the etching can be performed in a self-aligned manner using aluminum oxide as a mask by utilizing the difference in etching rate between aluminum oxide, which is an anodic oxide film, silicon nitride, and silicon oxide. Further, a laser doping technique (Japanese Patent Application No. 3-283981) which is an invention of the present inventors.
), The semiconductor region 204 is doped with an N-type impurity, and the semiconductor region 205 is doped with a P-type impurity, whereby an N-type impurity region (source and drain) 216 and a P-type impurity region 217 are formed. This process used CMOS technology as described in Japanese Patent Application No. 3-283981.

In this way, a structure as shown in FIG. 2D was obtained. In the laser doping method, since impurity implantation and annealing are performed simultaneously, the laser annealing and thermal annealing steps as in the first embodiment are unnecessary. After laser doping, 250-45
30 in a hydrogen atmosphere (1 to 700 torr, preferably 500 to 700 torr) at 0 ° C.
Annealing was performed for minutes to 3 hours, and hydrogen was added to the semiconductor region to reduce lattice defects (dangling bonds, etc.).

In this way, the shape of the element was adjusted. Thereafter, as usual, an interlayer insulator 218 is formed by sputtering film formation of silicon oxide, an electrode hole is formed by a known photolithography technique, and the surface of the semiconductor region or gate electrode / wiring is exposed, Finally, the second
A metal coating (aluminum or chromium) is selectively formed, and this is applied to the electrode / wiring 21.
9-221. As described above, NTFT 222 and PTFT 223 were formed.

FIG. 3 shows a cross-sectional view of the manufacturing process of this example. The detailed conditions of the present embodiment are almost the same as those of Japanese Patent Application No. 4-30220 filed by the present inventors, and will not be specifically described in detail. First, N-0 glass manufactured by Nippon Electric Glass Co., Ltd. was used as the substrate 301, and a silicon nitride film 302 having a thickness of 10 to 50 nm was formed by plasma CVD or low pressure CVD. Further, the underlying silicon oxide film 303 was formed by sputtering to a thickness of 100 to 800 nm. An amorphous silicon film having a thickness of 20 to 100 nm was formed thereon by plasma CVD, and annealed at 600 ° C. for 12 to 72 hours in a nitrogen atmosphere to cause crystallization. Further, this is patterned to form an island-shaped semiconductor region 304 (N channel T) as shown in FIG.
FT) and 305 (P channel TFT) were formed.

Further, a gate oxide film 306 having a thickness of 50 to 200 nm was deposited by sputtering. Further, a silicon nitride film 307 is deposited by a thickness of 2 to 20 nm, preferably 8 to 11 nm, by plasma CVD or low pressure CVD.

Next, an aluminum film was formed by sputtering or electron beam evaporation, and this was patterned to form gate electrodes / wirings 308 to 311. In this way, the outer shape of the TFT was adjusted as shown in FIG.

Furthermore, aluminum oxide films 312 to 315 were formed by anodizing the current through the gate electrodes / wirings 308 to 311 in the electrolytic solution. As the conditions for anodization, the method described in Japanese Patent Application No. 4-30220, which is the invention of the present inventors, was employed. The state up to this point is shown in FIG.

Next, an N-type impurity is implanted into the semiconductor region 304 and a P-type impurity is implanted into the semiconductor region 305 by a known plasma ion doping method, so that the N-type impurity region (source and drain) 316 and the P-type impurity region are implanted. 317 was formed. This process used a known CMOS technology. From the plasma, in addition to the impurity element, hydrogen used as a diluent for the gas source was also ionized and injected into the semiconductor region. Although this step can be performed by a known ion implantation method, it is required to implant hydrogen ions separately for the reason described later.

In this way, a structure as shown in FIG. 3D was obtained. As a matter of course, the crystallinity of the portion into which the impurity has been implanted is significantly degraded by the previous ion implantation, and is substantially in an amorphous state (an amorphous state or a polycrystalline state close thereto). Therefore, crystallinity was recovered by laser annealing. This step may be performed by thermal annealing at 600 to 850 ° C. For example, the laser annealing conditions described in Japanese Patent Application No. 4-30220 were used. However, since the silicon nitride film 307 does not transmit short-wavelength ultraviolet light having a wavelength of 250 nm or less, a XeCl laser (wavelength 308 nm) or a XeF laser (wavelength 3) is used.
51 nm) was used.

After laser annealing, annealing was performed in a hydrogen atmosphere at 250 to 450 ° C. (1 to 700 torr, preferably 500 to 700 torr) for 30 minutes to 3 hours to reduce lattice defects (dangling bonds, etc.) in the semiconductor. . Actually, since the silicon nitride film 307 exists, there is almost no exchange of hydrogen inside and outside the semiconductor region. Therefore, for example, in the plasma doping method, a large amount of hydrogen atoms are also implanted into the semiconductor region, but in the ion implantation method, a separate hydrogen ion implantation step is required. Also, with plasma doping method,
If the amount of hydrogen is insufficient, hydrogen must be doped separately.

In this way, the shape of the element was adjusted. Thereafter, as usual, an interlayer insulator 318 is formed by sputtering film formation of silicon oxide, an electrode hole is formed by a known photolithography technique, and the surface of the semiconductor region or gate electrode / wiring is exposed, Finally, the second
A metal coating (aluminum or chromium) is selectively formed, and this is applied to the electrode / wiring 31.
9-321. As described above, NTFT 322 and PTFT 323 were formed.

The invention of the present inventors, filed on Feb. 25, 1992, “Thin Film Insulated Gate Semiconductor Device and Method for Manufacturing the Same” (Applicant, Semiconductor Energy Laboratory Co., Ltd., Reference No. P0020)
FIG. 2 shows an example in which the present invention is applied to a TFT having a two-layer channel described in 42-01 to P002044-03, the above three).

4, 5, and 6, 401, 501, and 601 are N-channel TFTs,
Reference numerals 402, 402, and 402 denote P-channel TFTs. In each of the drawings, the first layers 408, 410, 508, 510, 508, and 510 in the channel region are substantially made of amorphous silicon. Its thickness was 20-200 nm.

Reference numerals 407, 409, 507, 509, 607, and 609 are substantially polycrystalline or semi-amorphous silicon and have a thickness of 20 to 200 nm. In addition, 404
, 406, 504, 506, 604, 606 are gate insulating films made of silicon oxide,
The thickness is 50 to 300 nm. And 403, 405, 503, 505, 603, 6
Reference numeral 05 denotes a silicon nitride film having a thickness of 2 to 20 nm formed in the same manner as in Examples 1 to 3. About these structures, it produced based on description of said patent application or Example 1. FIG.

A manufacturing process diagram (cross section) of a semiconductor device according to the present invention is shown. A manufacturing process diagram (cross section) of a semiconductor device according to the present invention is shown. A manufacturing process diagram (cross section) of a semiconductor device according to the present invention is shown. The structural example of the semiconductor device by a prior art example is shown. The structural example of the semiconductor device by a prior art example is shown. The structural example of the semiconductor device by a prior art example is shown.

Explanation of symbols

101 Insulating substrate 102 Blocking layer (silicon nitride)
103 Blocking layer (silicon oxide)
104 Semiconductor region (for N-channel TFT)
105 Semiconductor region (for P-channel TFT)
106 Gate insulating film 107 Silicon nitride film 108-111 Gate electrode / wiring (aluminum)
112-115 Anodic oxide layer 116 N-type impurity region 117 P-type impurity region 118 Interlayer insulators 119-121 Second layer metal wiring 122 NTFT
123 PTFT

Claims (3)

A first step of forming a gate insulating film on the semiconductor region;
A second step of forming a gate electrode on the gate insulating film;
A third step in which N-type or P-type impurities and hydrogen are ionized and simultaneously added to the source region and drain region of the semiconductor region;
A fourth step of recovering the crystallinity of the semiconductor region by performing a first annealing on the semiconductor region;
A fifth step of reducing dangling bonds in the semiconductor region by performing a second annealing on the semiconductor region to which the impurity and the hydrogen are added, and
The gate insulating film has an insulating film containing nitrogen,
The method for manufacturing a semiconductor device is characterized in that the third step is performed in a state where the insulating film containing nitrogen covers the semiconductor region. Oite to claim 1,
The method for manufacturing a semiconductor device, wherein the gate insulating film is a single layer of an insulating film containing nitrogen or a multilayer containing at least one insulating film containing nitrogen. Oite to claim 1 or claim 2,
The method for manufacturing a semiconductor device, wherein the insulating film containing nitrogen is a silicon film containing nitrogen.

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