JP4524867B2 - Driving method of liquid crystal display element - Google Patents

Description

【０１１３】
【表２】

【０１１４】
ここで、「駆動電圧波形１乃至３１」では、表示選択電圧波形Ｖ１＝＋７Ｖ、内部直流制御電圧波形Ｖ１／Ｖ２＝＋７Ｖ／−５Ｖである。「駆動電圧波形３２乃至３６」では、表示選択電圧波形Ｖ２＝−５Ｖ、内部直流制御電圧波形Ｖ１／Ｖ２＝＋７Ｖ／−５Ｖである。「駆動電圧波形３７乃至４０」では、表示選択電圧波形Ｖ１／Ｖ２＝＋７Ｖ／−５Ｖ、内部直流制御電圧波形Ｖ１／Ｖ２＝＋７Ｖ／−５Ｖである。「駆動電圧波形４１乃至４２」では、表示選択電圧波形Ｖ１＝＋７Ｖ、内部直流制御電圧波形Ｖ３／Ｖ４＝＋９Ｖ／−９Ｖ、＋３Ｖ／−３Ｖである。
【０１１５】
（９）本発明に用いた駆動電圧波形の単位時間当たりの電圧面積強度の非対称性パラメータについて
上述の（８）に示した「駆動電圧波形１乃至４２」について、単位時間当たりの電圧積分強度を駆動電圧の全波形中の印加電圧の絶対値の最大値で規格した値、すなわち、図２８に示す面積強度の非対称性パラメータＲを算出した。
【０１１６】
また、制御波形期間だけの面積強度の非対称性パラメータＲ′についても同様に算出できる。このＲ′値は、１．５周期分の矩形波（正極性期間２箇所、負極性期間１箇所）を挿入した「駆動電圧波形６，１０，１５，２１，２７，３２乃至３６」においては、０．４２９以下になるが、それ以外の「駆動電圧波形２乃至４０」では、０．１４２以下となる。また、「駆動電圧波形４１，４２」では０である。
【０１１７】
【実施例】
実施例として、液晶材料が「ＣＳ−１０３１」で配向膜が「ＡＬ１０５１」、液晶材料が「ＣＳ−１０２５」で配向膜が「ＡＬ１０５１」、及び、液晶材料が「ＣＳ−１０２８」で配向膜が「ＳｉＯ斜方蒸着膜」の３種類の液晶パネルを作成し、これら液晶パネルのそれぞれについて、「駆動電圧波形１乃至３１」（表示選択波形Ｖ１＝＋７Ｖ、内部直流制御波形Ｖ１／Ｖ２＝＋７Ｖ／−５Ｖ）、「駆動電圧波形３２乃至３６」（表示選択波形Ｖ２＝−５Ｖ、内部直流制御波形Ｖ１／Ｖ２＝＋７Ｖ／−５Ｖ）、「駆動電圧波形３７乃至４０」（表示選択波形Ｖ１／Ｖ２＝＋７Ｖ／−５Ｖ、内部直流制御波形Ｖ１／Ｖ２＝＋７Ｖ／−５Ｖ）及び「駆動電圧波形４１乃至４２」（表示選択波形Ｖ１＝＋７Ｖ、内部直流制御波形Ｖ３／Ｖ４＝＋９Ｖ／−９Ｖ、＋３Ｖ／−３Ｖ）を適用して、〔表１〕及び〔表２〕に示すように、「実施例１乃至１４０」を定義し、内部直流電圧値についての測定を行った。
【０１１８】
４０°Ｃで、２４時間に亘って駆動電圧波形を印加した後の内部直流電圧値（内部直流電圧の蓄積量）は、〔表１〕に示すとおりである。
【０１１９】
これら〔表１〕及び〔表２〕から明らかなように、「ＡＬ１０５１」を配向膜として用いた場合においては、駆動電圧波形の種類による内部直流電圧の蓄積量は、液晶材料によらずに、同様のプロファイルを示している。
【０１２０】
内部直流電圧制御波形を挿入しない「駆動電圧波形２」を用いた場合には、内部直流電圧は、２．５Ｖ程度まで蓄積される。
【０１２１】
そして、表示選択波形期間がすべて正電圧による波形で、内部直流電圧制御波形を挿入した場合、「駆動電圧波形５乃至８」のように、全体の５．６％程度の内部直流電圧制御波形期間を挿入すると、内部直流電圧は、１．６乃至２Ｖ程度まで低減し、さらに、「駆動電圧波形９乃至１３」のように、全体の１１．１％程度の内部直流電圧制御波形期間を挿入すると、内部直流電圧は、０．６乃至０．９Ｖと低減し、内部直流電圧制御の効果は大きくなる。また、さらに内部直流電圧制御波形期間の時間比率を増加していくと、それに伴って、内部直流電圧は、著しく減少する。
【０１２２】
１ビットプレーン内に内部直流電圧制御期間を５０％挿入した「駆動電圧波形１」では、１０８ビットプレーン中に内部直流電圧制御期間の時間比率を変えて挿入したものと比較すると、「駆動電圧波形９乃至１３」のように、１１．１％しか挿入していないものと同じである。内部直流電圧制御期間を挿入する時間比率は、表示特性としては小さい方が好ましいことから、１ビットプレーン単位（１５４．３μsec以下）の非常に速い領域で内部直流電圧制御波形を挿入するより、１０８ビットプレーン単位（１フレーム、１６．６ｍsec以下）で挿入した方が、より顕著に効果が見られることが確認された。これらは、パネル内のイオンの移動を伴う分極速度と緩和速度とに相関していると考えられ、速い周波数の波形に対しては、分極したイオンが内部直流電圧制御期間に応答しないためと考えられる。
【０１２３】
また、「駆動電圧波形４」のように、表示選択波形期間がすべて負電圧になる波形であっても、内部直流電圧制御波形を挿入することにより、表示選択波形期間に正電圧波形を挿入した「駆動電圧波形３」と同じように、問題なく内部直流電圧の蓄積を抑制することができることが確認された。
【０１２４】
表示選択波形期間が、すべて正電圧による波形から、正負電圧による波形が同数になるまでに亘って変えた「駆動電圧波形２４，３７乃至４０」では、表示期間の非対称性が緩和されることからも明らかなように、波形期間の偏りの減少に伴って内部直流電圧の蓄積量は減少することが確認された。
【０１２５】
表示選択波形期間が全て正電圧である「駆動電圧波形６，１０，１５，２１，２７」、ならびに、表示選択波形期間が全て負電圧である「駆動電圧波形３２乃至３６」においては、制御波形期間は、正電圧期間が１箇所、負電圧期間が２箇所となる１．５周期分の矩形波を挿入したものである。このため、制御期間の効果は、信号期間の極性が正のものより負のものの方が劣ることが予想がつく。各制御波形期間の時間幅のもので、実効的直流電圧に対する内部直流電圧の比で比較すると、制御波形期間の時間幅が短いときには、予想通りの結果となったが、時間幅が長くなるほど差が小さくなることがわかった。
【０１２６】
次に、制御波形期間の矩形波の振幅値が表示選択波形期間の電圧と同じ値の「駆動電圧波形２４」に対して、大きい値の「駆動電圧波形４１」と小さい値の「駆動電圧波形４２」とでは、大きい振幅値の「駆動電圧波形４１」を用いた方が、内部直流電圧の抑制には大きな効果が見られる。
【０１２７】
そして、ＳｉＯを配向膜として用いた場合においては、〔表１〕及び〔表２〕に示すように、ＰＩ系配向膜を使用したときに比較して、顕著に、内部直流電圧値が大きくなっている。特に、内部直流電圧制御期間を挿入してないもの、及び、挿入期間が少ないものについては、ほぼ印加した駆動電圧波形の実効的な直流電圧分まで内部直流電圧が蓄積されてしまっている。
【０１２８】
このような、ＰＩ系配向膜とＳｉＯ斜方蒸着膜での違いは、たとえ液晶材料が同じであっても、液晶パネルとして構成した後におけるパネル中のイオン量が、前者より後者の方が、１桁以上多いことに起因する。
【０１２９】
そして、駆動電圧波形中の内部直流電圧制御期間を挿入する比率を増加するにしたがって、内部直流電圧の蓄積量は、抑制される。特に、内部直流電圧制御期間が１２ビットプレーン以上、すなわち、駆動電圧波形全体の１１．１％であれば、全く挿入しない場合の約１／３まで抑制でき、さらに、１２ビットプレーン以上、すなわち、駆動電圧波形全体の３３．３％であれば、ほとんど内部直流電圧は蓄積しない。
【０１３０】
次に、図３１に示すように、温度４０°Ｃにおける駆動電圧波形の印加時間による内部直流電圧値の蓄積状況について考える。図３１は、実施例の液晶材料として「ＣＳ−１０３１」を用い、配向膜材料として「ＡＬ１０５１」を用いた各仕様のセルに、「駆動電圧波形２，５，１１，１６，２４，２５，３０，３１」を温度４０°Ｃにおいて印加し、印加時間を変えた場合のイオンによる内部直流電圧の蓄積量を示している。この図３１から明らかなように、内部直流電圧制御波形が挿入されていない「駆動電圧波形２」においては、印加時間に応じて、著しく内部直流電圧が蓄積されていることが確認できる。
【０１３１】
そして、所期駆動電圧波形の印加時間にともなって、内部直流電圧が蓄積されるが、内部直流電圧制御波形期間の時間比率が増加するほど内部直流電圧の蓄積が抑制される傾向は変わらない。ここで、内部直流電圧制御期間の時間比率が５．６％と最も少ない「駆動電圧波形５」では、１０００時間の連続印加に対して、内部直流電圧の蓄積は、２Ｖ程度以上まで達し、さほどの効果は見られない。さらに、内部直流電圧制御期間の時間比率が１１．１％まで大きくなった「駆動電圧波形１１」では、内部直流電圧の蓄積は、１Ｖ以下まで低下し、抑制の効果が大きくなっている。
【０１３２】
「駆動電圧波形１１」よりも内部直流電圧制御期間の時間比率が高い「駆動電圧波形１６，２４，２５，３０，３１」においては、内部直流電圧の抑制効果が顕著になり、１０００時間の連続印加をしても、内部直流電圧の蓄積は、０．３Ｖ以下である。
【０１３３】
次に、図３２に示すように、温度４０°Ｃにおける、駆動電圧波形の印加時のイオン電流挙動の結果について考える。図３２は、実施例として、液晶材料に「ＣＳ−１０３１」を用い、配向膜材料として「ＡＬ１０５１」を用いた液晶セルに、加熱短絡処理によって初期化した後に、「駆動電圧波形１１，１８，２５，３０」を温度４０°Ｃにおいて印加したときのイオン電流を測定した結果を示している。表示電圧波形期間の印加電圧は、７Ｖ、制御電圧波形期間の印加電圧は、＋７Ｖ及び−５Ｖである。
【０１３４】
さらに、図３３に示すように、単一周波数の矩形波を制御電圧波形期間の時間幅に応じて、以下の〔表３〕のように挿入したときの、単位波形内での正電圧と負電圧とによって流れた電流量（電荷量）の対称からのずれΔＱを算出し、その結果を図３４に示す。
【０１３５】
【表３】

【０１３６】
図３４から明らかなように、繰り返し波形内での電荷量の対称からのずれΔＱが電圧印加時間で累積され、内部直流電圧の蓄積を引き起こすと考えられる。これは、ΔＱが小さい方が、前述の２４時間後の内部直流電圧の結果が小さくなることからも実証できる。それぞれの制御電圧波形期間中に同じ周期数の矩形波を挿入したもので比較すると、制御電圧波形期間の時間幅が長い方が、電荷量の対称からのずれΔＱは小さくなる。制御電圧波形期間が短いものでは、挿入する矩形波の周期数が増加すると、ΔＱも増加する。一方、制御電圧波形期間が長いものでは、挿入矩形波の周期数が増加するに伴い、ΔＱは極小点をもつような変化をすることが分かる。これらから鑑みて、以下のことが分かる。
【０１３７】
すなわち、制御電圧波形期間に挿入する矩形波の周期数が大きいほど、ΔＱは小さくなり、内部直流電圧の蓄積も抑制できる。但し、挿入する矩形波の１／２周期時間幅が０．４ｍsec以上、さらに好ましくは、０．９ｍsec以上のもので、できるだけの多くの周期数を挿入することがΔＱを小さくさせ、内部直流電圧の蓄積も抑制できる。
【０１３８】
以上に説明した例及び結果から、本発明においては、オンまたはオフの二状態のうち一方の状態を選択する駆動をその選択期間内に実効的な内部直流電圧が生じる電圧信号によって行い、かつ、ある一定期間内に、実際上は液晶駆動に寄与しない、内部直流電圧の大きさを制御（低減）する交流波形、例えば矩形波を挿入することによって、内部直流電圧の蓄積を顕著に抑制することができる。
【０１３９】
このとき、たとえ、矩形波を印加する時間幅を長くしても、繰り返し波形内における電気的な中性は確保できないものの、比較的短いある範囲内で挿入することにより、不純物イオンが形成する内部直流電圧の発生を極めて効果的に抑制することができ、表示異常の防止及び長期間にわたる表示信頼性の確保ができる駆動条件を見出すことができた。
【０１４０】
内部直流電圧制御期間の駆動電圧波形全体に対する時間比率をできるだけ大きくすることによって、内部直流電圧の蓄積は抑制できる。ただし、内部直流電圧制御期間の時間比率を５０％とすると、二状態のうち一方の状態を選択する電圧波形の期間と、内部直流電圧を制御する電圧波形の期間とが１対１となるので、あえて、表示に関与しない交流波形制御期間を導入しなくても、従来通りの駆動電圧波形である図１９に示した波形の５０％／５０％の比率にした、いわゆる「バイポーラ型」の波形で置き換えることができる。また、内部直流電圧制御期間の時間比率を大きくすると、ビットプレーン時間を短くせざる得ず、輝度、階調などの表示特性を劣化させてしまう原因になる。
【０１４１】
これら、相反する結果において、輝度、階調などの表示特性を劣化させずに、内部直流電圧の大きさを制御（低減）する波形の条件として、内部直流電圧制御期間を、１フィールドの単位時間あたり、５％以上、５０％未満とすることが望ましく、さらに好ましくは、１０％以上３５％以下とすることにより、両者の条件を最適化することができる。さらに、内部直流電圧の制御のために挿入する矩形波に代表される交流波形は、割り当てられた時間内で、１／２周期時間幅が０．４ｍsec以上、さらに好ましくは０．９ｍsec以上のもので、できるだけ多くの周期数を挿入することが望ましい。また、挿入される矩形波は、単一の周波数のものに限られることはなく、複数の周波数の波形を組合せてもよいが、上述の条件の矩形波が一部にでも含まれていることが望ましい。
【０１４２】
このとき、内部直流電圧を制御する制御電圧波形の電気的な中性（制御電圧波形期間の非対称性パラメータＲ′＝０）は必ずしも必要ではなく、実施例に示すように、オフセット電圧がかかったような矩形波であってもよく、｜Ｒ′｜≦０．５の範囲であればよい。また、「駆動電圧波形２４」に対して、制御電圧波形期間の矩形波の振幅のみを変えた「駆動電圧波形４１」と「駆動電圧波形４２」とで比較すると、矩形波の振幅が大きいほど、内部直流電圧を抑制する効果が大きいことが確認できる。
【０１４３】
この駆動電圧波形中に挿入する内部直流電圧制御波形の極性は、表示波形期間で出力される正負電圧信号によらず、常に同じ内部直流電圧制御波形を挿入することができ、駆動回路ならびに波形出力ロジック回路を簡便にすることができる。
【０１４４】
ただし、できるだけ内部直流電圧制御波形の挿入期間を短くする場合にあっては、「駆動電圧波形６、１０」のように、内部直流電圧制御期間の電気的中性がとれていない波形、すなわち、１．５周期の矩形波を、内部電圧制御波形として発生させることにより、顕著な効果が得られる。この場合の内部電圧制御波形は、表示電圧波形期間の極性の偏りに応じて、すなわち、表示電圧波形期間が正極性の場合には、内部電圧制御波形期間においては正電圧期間が１箇所、負電圧期間が２箇所となるようにし、表示電圧波形期間が負極性の場合には、内部電圧制御波形期間においては正電圧期間が２箇所、負電圧期間が１箇所となるように印加する。ただし、このように、表示電圧波形期間の偏り極性を識別するために、駆動回路及び南部電圧制御波形の出力ロジック回路が複雑になることも予想される。
【０１４５】
上述のように、本発明は、表示電圧波形期間が実効的に内部直流電圧を生じさせるのに対して、これをある一定期間内に制御電圧波形期間を挿入することで、内部直流電圧を緩和させることに関するものである。すなわち、表示電圧波形期間での液晶パネル中のイオンの分極、配向膜への吸着などの内部直流電圧に起因する現象を、制御電圧波形期間の矩形波によって、効率的に緩和、脱着させることを目指したものである。特に緩和が遅く、内部直流電圧として長期間にわたって発生し、表示特性に致命的な打撃を与えるイオン種の配向膜への吸着を抑制し、かつ、脱着させる上で、先述の交流波形が必要であり、かつ、上述の条件に基づくことが必須となる。
【０１４６】
以上に説明した例から、本発明によれば、高精細、高コントラスト、画素内階調の表示が可能で、高信頼性、低消費電力、薄型軽量などの特徴を有する液晶表示素子を実現することができる。また、その製造に係る工程が短縮され、生産性の向上とコストの低減をもたらし、安価に製造でき、良好な表示特性を有する液晶素子、さらにはその応用である投射型ディスプレイ等を提供することができる。
【０１４７】
なお、以上に述べた本発明の実施例は本発明の技術的思想に基づいて、さらに変形が可能である。例えば、上述した駆動電圧波形をはじめとする駆動条件は、本発明の目的を達成できる範囲内で様々に変化させてもよい。また、上述の実施例では、入射光の反射及び非反射の二つの状態のいずれか、または、入射光の透過及び非透過の二つの状態のいずれかを選択するようにしているが、これ以外にも、入射光の偏光及び非偏光状態のいずれか、または、入射光の旋光及び非旋光状態のいずれかなど、実質的にオンとオフの二つの状態のいずれかを選択するように駆動することとしてもよい。
【０１４８】
【発明の効果】
上述のように、本発明に係る液晶表示素子の駆動方法においては、第１の電極が設けられた第１の基板と第２の電極が設けられた第２の基板とが、該第１の電極及び該第２の電極が設けられた側を相対向させて所定の間隔を隔てて配置され、これら各基板間に液晶が封入されて構成された液晶表示素子を駆動するにあたって、該第１の電極及び該第２の電極間に印加する電圧信号によって、入射光の反射状態及び非反射状態、または、入射光の透過状態及び非透過状態、あるいは、入射光の偏光状態及び非偏光状態、もしくは、入射光の旋光状態及び非旋光状態、すなわち、オンまたはオフの二状態を切替えることにより、画像表示を行う液晶表示素子、例えば、液晶光変調型表示素子、液晶光変調器などの駆動方法において、一定時間内、あるいは、複数のフレーム期間内、もしくは、一のフレーム期間内において、表示信号期間と、表示には関与しない制御信号期間とからなる駆動電圧波形を用い、該制御信号期間に印加する電圧信号を、正極性及び負極性の電圧信号が、割当時間内で交互に、連続的、または、非連続的に変化する電圧信号、もしくは、途中に０Ｖの電圧信号域を含む正負交互の電圧信号とすることにより、内部直流電圧の発生を極めて効果的に抑制することができる
すなわち、本発明は、十分なビットプレーン時間を確保しつつ、簡単で、かつ、不純物イオンによる表示画像の質の劣化が生じないようになされた液晶表示素子の駆動方法を提供することができるものである。
【図面の簡単な説明】
【図１】本発明に係る液晶表示素子の駆動方法が適用される強誘電性液晶表示素子における液晶分子の構成を示す斜視図である。
【図２】上記液晶表示素子における印加電圧と透過率との関係を示すグラフである。
【図３】上記液晶表示素子の構成を示す縦断面図である。
【図４】上記液晶表示素子の反射型の動作状態を示す斜視図である。
【図５】上記液晶表示素子の透過型の動作状態を示す斜視図である。
【図６】上記液晶表示素子における１フレーム時間内におけるビットプレーンと光強度との関係を示すグラフである。
【図７】上記液晶表示素子における各ビットプレーンにおける電圧印加と透過率（反射率）との関係を示すタイムチャートである。
【図８】上記液晶表示素子において非対称な駆動電圧波形を印加した場合の短絡操作後の開回路モニター時間と開回路電圧との関係を示すグラフである。
【図９】上記液晶表示素子において内部直流電圧値を算出するための短絡操作後の開回路モニター時間と開回路電圧との関係を示すグラフである。
【図１０】上記液晶表示素子における種々の条件下における短絡操作後の開回路モニター時間と開回路電圧との関係を示すグラフである。
【図１１】「ＳＳＦＬＣ」モードのパネルにおけるＰｓ（自発分極）反転に伴うＰｓ反転電流を示すグラフである。
【図１２】「ＳＳＦＬＣ」モードのパネルにおけるＰｓ（自発分極）反転に伴うＰｓ反転電流を示すグラフであって、上記図１１よりも観測時間を長くしたものである。
【図１３】上記液晶表示素子におけるビットプレーン波形の例（波形Ａ）を示すタイムチャートである。
【図１４】上記液晶表示素子におけるビットプレーン波形の例（波形Ｂ）を示すタイムチャートである。
【図１５】上記液晶表示素子におけるビットプレーン波形の例（波形Ｃ）を示すタイムチャートである。
【図１６】上記液晶表示素子におけるビットプレーン波形の例（波形Ｄ）を示すタイムチャートである。
【図１７】上記液晶表示素子におけるビットプレーン波形の例（波形Ｅ）を示すタイムチャートである。
【図１８】上記液晶表示素子における内部直流電圧制御波形を示すタイムチャートである。
【図１９】上記液晶表示素子において１ビットプレーンを構成する電圧波形中に内部直流電圧制御波形を挿入した「駆動波形１」であって、正極性電圧によって表示をさせる１ビットプレーン波形及び負極性電圧によって表示をさせる１ビットプレーン波形を示すタイムチャートである。
【図２０】上記液晶表示素子において使用される１フレームが１０８ビットプレーンから構成され、内部直流電圧の内部直流電圧制御波形を挿入していない「駆動電圧波形２」を示すタイムチャートである。
【図２１】上記液晶表示素子において使用される１フレームが１０８ビットプレーンから構成され、３６ビットプレーンごとに４ビットプレーン分、計１２ビットプレーンの内部直流電圧の内部直流電圧制御波形を挿入した「駆動電圧波形３」を示すタイムチャートである。
【図２２】上記液晶表示素子において使用される１フレームが１０８ビットプレーンから構成され、３６ビットプレーンごとに４ビットプレーン分、計１２ビットプレーンの内部直流電圧の内部直流電圧制御波形を挿入した「駆動電圧波形４」を示すタイムチャートである。
【図２３】上記液晶表示素子において使用される１フレームが１０８ビットプレーンから構成される波形であり、挿入する内部直流電圧制御波形のビットプレーン数が６ビットプレーンであって、１周期（図中（Ａ））、１．５周期（図中（Ｂ））、２周期（図中（Ｃ））、３周期（図中（Ｄ））とした「駆動電圧波形５乃至８」を示すタイムチャートである。
【図２４】上記液晶表示素子において使用される１フレームが１０８ビットプレーンから構成される波形であり、挿入する内部直流電圧制御波形を１２ビットプレーンであって、１周期（図中（Ａ））、１．５周期（図中（Ｂ））、２周期（図中（Ｃ））、３周期（図中（Ｄ））、６周期（図中（Ｅ））とした「駆動電圧波形９乃至１３」を示すタイムチャートである。
【図２５】上記液晶表示素子において使用される１フレームが１０８ビットプレーンから構成される波形であり、挿入する内部直流電圧制御波形を２４ビットプレーンであって、１周期（図中（Ａ））、１．５周期（図中（Ｂ））、２周期（図中（Ｃ））、２周期（図中（Ｄ））、６周期（図中（Ｅ））、１２周期（図中（Ｆ））とした「駆動電圧波形１４乃至１９」を示すタイムチャートである。
【図２６】上記液晶表示素子において使用される１フレームが１０８ビットプレーンから構成される波形であり、挿入する内部直流電圧制御波形を３６ビットプレーンであって、１周期（図中（Ａ））、１．５周期（図中（Ｂ））、２周期（図中（Ｃ））、２周期（図中（Ｄ））、２周期（図中（Ｅ））、３周期（図中（Ｆ））とした「駆動電圧波形２０乃至２５」を示すタイムチャートである。
【図２７】上記液晶表示素子において使用される１フレームが１０８ビットプレーンから構成される波形であり、挿入する内部直流電圧制御波形を４８ビットプレーンであって、１周期（図中（Ａ））、１．５周期（図中（Ｂ））、２周期（図中（Ｃ））、２周期（図中（Ｄ））、２周期（図中（Ｅ））、４周期（図中（Ｆ））とした「駆動電圧波形２６乃至３１」を示すタイムチャートである。
【図２８】上記液晶表示素子において使用される１フレームが１０８ビットプレーンから構成される波形であり、挿入する内部直流電圧制御波形がそれぞれ１．５周期の矩形波であって、６ビットプレーン（図中（Ａ））、１２ビットプレーン（図中（Ｂ））、２４ビットプレーン（図中（Ｃ））、３６ビットプレーン（図中（Ｄ））、４８ビットプレーン（図中（Ｅ））とした「駆動電圧波形３２乃至３６」を示すタイムチャートである。
【図２９】上記液晶表示素子において使用される１フレームが１０８ビットプレーンから構成される波形であり、３６ビットプレーン分の２周期の矩形波である内部直流電圧制御波形が挿入され、表示電圧波形区間の負極性部を９ビットプレーン（図中（Ａ））、１８ビットプレーン（図中（Ｂ））、２７ビットプレーン（図中（Ｃ））、３６ビットプレーン（図中（Ｄ））とした「駆動電圧波形３７乃至４０」を示すタイムチャートである。
【図３０】上記液晶表示素子において使用される１フレームが１０８ビットプレーンから構成される波形であり、３６ビットプレーン分の２周期の矩形波である内部直流電圧制御波形が挿入され、内部直流電圧制御波形の電圧値（絶対値）が表示電圧波形の電圧値と等しい場合（図中（Ａ））、内部直流電圧制御波形の電圧値（絶対値）が表示電圧波形の電圧値より大きき場合（図中（Ｂ））、内部直流電圧制御波形の電圧値（絶対値）が表示電圧波形の電圧値より小さい場合（図中（Ｃ））の「駆動電圧波形２４、４１、４２」を示すタイムチャートである。
【図３１】上記液晶表示素子において「駆動電圧波形２、５、１１、１６、２４、２５，３０、３１」を印加した場合の時間経過に対する内部直流電圧の蓄積量を示すグラフである。
【図３２】実施例１１（図中（Ａ））、実施例１８（図中（Ｂ））、実施例２５（図中（Ｃ））、実施例４８（図中（Ｄ））についての、経過時間と電流との関係を示すグラフである。
【図３３】上記液晶表示素子において、単一周波数の矩形波を制御電圧波形期間の時間幅に応じて挿入したときの、単位波形内での正電圧と負電圧とによって流れた電流量（電荷量）の対称からのずれΔＱを示すグラフである。
【図３４】上記液晶表示素子において、内部直流電圧制御波形が６ビットプレーン、１２ビットプレーン、２４ビットプレーン、３６ビットプレーン、４８ビットプレーンである場合の挿入周期数と内部直流電圧の蓄積量との関係を示すグラフである。
【符号の説明】
１ａ ガラス基板、１ｂ ＩＴＯ、１ｃ，２ｃ 液晶配向膜、２ａ 回路基板、２ｂ アルミニウム、３ スペーサ、４ 強誘電性液晶、１１ 強誘電性液晶変調型表示素子[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for driving a liquid crystal display element such as a liquid crystal light modulation display element or a liquid crystal light modulator.
[0002]
[Prior art]
In recent years, the development of small information terminals such as mobile phones and so-called “PDA” (Personal Digital Assistance), the spread of the Internet such as e-mail and World Wide Web (WWW), etc. As the information transmission / reception environment is improved, it is desired to improve the performance of a portable display element (display) for displaying information obtained through the environment. In addition, for indoor use, a so-called “large display for a personal theater”, “a thin display for a personal computer”, etc., it is desired to improve the performance of a projection display element.
[0003]
Liquid crystal display elements have been studied as one of display elements that satisfy these requirements in an integrated manner. This liquid crystal display element is characterized in that it can be thin and lightweight, and can display high-quality images while having low power consumption.
[0004]
As liquid crystal display elements, those using a birefringence mode of “STN” (Supper Twisted Nematic) or an optical rotation mode of “TN” (Twisted Nematic) are currently in practical use. In addition, ferroelectric liquid crystals and antiferroelectric liquid crystals using birefringence mode, which are positioned as next-generation liquid crystal display elements, have been studied and are expected to be practically used. Along with the “STN” display currently in practical use, a surface-stable ferroelectric liquid crystal mode (“SSFLC”) is obtained by using a ferroelectric liquid crystal (“FLC”), which is a representative example of a birefringence mode display element. : Surface Stabilizied Ferroelectric Liquid Crystal) has been actively researched.
[0005]
Normally, in the ferroelectric liquid crystal, as shown in FIG. 1, in the chiral smectic C phase, the orientation direction of the liquid crystal molecules M is in the state 1 and the state 2 with respect to the externally applied electric field E (Ps is spontaneous polarization). Switch between two states. When the element is viewed from directly above, the central axis of the cone virtually shown in FIG. 1 coincides with the direction of the alignment film (rubbing direction for the rubbing film, vapor deposition direction for the SiO oblique deposition film). This change in the alignment direction of the liquid crystal molecules M appears as a change in light transmittance by disposing the liquid crystal element between the orthogonal polarizing plates. As shown in FIG. Thus, it changes steeply from 0% to 100%.
[0006]
A display element using the “SSFLC” display mode has a high response speed (response speed about 1000 times that of a conventional nematic liquid crystal display element), and has a memory property. Therefore, a cathode ray tube (CRT) or “ Manufactured by eliminating active elements such as TFTs (Thin Film Transistors) that can be driven by more than 1000 scan lines even with simple XY matrix driving, which eliminates flicker that is a problem with TN displays It has the characteristics that the yield can be improved. In addition, the current mainstream nematic liquid crystal has a wide viewing angle because the molecular arrangement is uniform and the panel-to-substrate gap is less than half that of the nematic liquid crystal panel. It has the characteristics.
[0007]
Thus, attempts have been made to apply such ferroelectric liquid crystal to a reflective display. For example, `` IEEE Journal of Quantum Electronics, vol. 29, no. 2 (1993) 699, Journal of the Society for Infomation Display, vol. 5 (1997) 1, SPIE, vol. 3013 (1977) 174 '' It is disclosed. In either case, a ferroelectric liquid crystal cell is formed on a semiconductor memory and driven by a memory voltage.
[0008]
By the way, the present applicants have already proposed a reflective display in which a semiconductor memory and a ferroelectric liquid crystal are combined. This is a display technology that enables gradation expression by combining the field sequential method and the luminance modulation of the light source, and in principle, it is possible to display up to transfer gradations as human visual characteristics.
[0009]
Such a reflective ferroelectric liquid crystal display element has, for example, a structure in which a ferroelectric liquid crystal 4 is sealed between a transparent substrate 1a and a silicon substrate (silicon VLSI circuit substrate) 2a as shown in FIG. is doing. That is, the reflective ferroelectric liquid crystal display element is obtained by firing a transparent electrode 1b such as ITO and a SiO oblique vapor deposition film or a polymer thin film typified by polyimide on the inner surface of a transparent substrate 1a such as glass, In the same manner, a laminated body in which the liquid crystal alignment film 1c is sequentially laminated is formed by rubbing, and the reflective film / electrode 2b and the SiO oblique deposition film are formed on the inner surface of the silicon substrate 2a in which the drive circuit is formed in the pixel. Alternatively, a polymer thin film typified by polyimide is baked and then rubbed to form a liquid crystal alignment film 2c, and the laminates formed by sequentially laminating the transparent substrate 1a and the silicon substrate 2a face each other. The liquid crystal cell is configured by securing a predetermined cell gap by sandwiching the granular spacer 3, and the ferroelectric liquid crystal 4 is injected into the cell gap, and the periphery is coated with an adhesive. It is constituted by Jill.
[0010]
The pixels of the ferroelectric liquid crystal light modulation display element 11 shown in FIG. 3 are two-dimensionally configured (this may be linear). As shown in FIG. 4, the incident light 5 to the ferroelectric liquid crystal light modulation display element 11 is reflected by the reflective film / electrode 2 b and is reflected as reflected light 6 from the ferroelectric liquid crystal light modulation display element 11. It is injected. The light transmittance of the ferroelectric liquid crystal 4 on the optical paths of the incident light 5 and the reflected light 6 varies depending on the electric field between the electrode 1b and the reflective film / electrode 2b as shown in FIG. That is, since the intensity of the reflected light 6 is modulated by the electric field intensity between the electrode 1b and the reflective film / electrode 2b, an image is displayed by switching the reflection state and non-reflection state of incident light for each pixel. be able to.
[0011]
The voltage application to the reflective film and electrode 2b is controlled for each pixel by the control circuit 7 outside the ferroelectric liquid crystal light modulation display element 11, but is controlled by a circuit incorporated on the silicon substrate 2a. It's also good. The application of voltage may be performed by scanning every pixel, every plurality of pixels, or all pixels may be performed simultaneously.
[0012]
FIG. 5 shows a light transmission type liquid crystal element 21. In the case of the light transmission type liquid crystal element 21, the fundamental difference from the reflection type liquid crystal element shown in FIGS. 3 and 4 is that the drive electrode is made of transparent ITO 12b provided on the glass substrate 12a. Is driven for each pixel by the control gate element 18 made of TFT, and the incident light 15 is transmitted or blocked as the transmitted light 16 by turning on / off the signal voltage. Note that an auxiliary capacitor may be connected to the control gate element 18. In the case of a mode having a memory effect such as the “SSFLC” mode, simple matrix driving without using an active element as described above is possible.
[0013]
In the “TN” mode, it is possible to continuously change between the bright state and the dark state according to the effective electric field strength, whereas in the “SSFLC” mode, as described above, the threshold value of the applied voltage is changed. Has a feature of bistability (or memory property) in which the transmittance (or reflectance) changes sharply, so only two states, a bright state and a dark state, can be selected, and the intermediate gradation of those can be controlled Has been considered difficult.
[0014]
Conventional display methods for intermediate gray scale display include an area gray scale method in which subpixels are provided and adjusted according to their integrated areas, or a small inversion domain by controlling the amount of injected charge in one pixel. A multi-domain method for controlling has been proposed. The former has a problem that the number of pixels substantially increases, the drive circuit becomes complicated, and it is difficult to increase the resolution. In the latter case, there is a problem that it is difficult to realize equivalent gradation characteristics in all pixels due to variations in temperature distribution and performance of active elements. Therefore, these methods cannot perform sufficient halftone control.
[0015]
Therefore, the present applicants use a spatial modulation element that selects either the on / off of reflected light or transmitted light, such as a ferroelectric liquid crystal element, and uses the field sequential method and the light of the light source. The invention of a driving method of a liquid crystal display element that realizes a digital gradation display capable of displaying up to continuous gradation as a human visual characteristic in combination with intensity modulation is disclosed in Japanese Patent Application No. 5-347576 and This is proposed in Japanese Patent Application No. 7-212686.
[0016]
In this liquid crystal display element driving method, one frame is divided into a plurality of sub-frames (which are defined as bit planes) according to the number of gradation bits, and each bit brain is weighted by luminance modulation of the light source. Then, gradation display is performed.
[0017]
That is, when using a light source having the same light intensity, to display 8-bit gradation (256 gradations), one frame of 16.7 msec is simply time-divided with 8 bits (0 to 256 gradations). For this purpose, the ferroelectric liquid crystal must be able to be driven completely in about 65.5 μsec. In 10-bit display, the driving time of the ferroelectric liquid crystal is 16.3 μsec. This is a severe value in view of the response speed of the current ferroelectric liquid crystal, and the applied electric field has to be set high in order to realize it.
[0018]
Therefore, by using a light source capable of modulating the light intensity, the driving time of the ferroelectric liquid crystal determined by time-sharing one frame can be dramatically increased. That is, in the case of displaying 8-bit gradation, if the light intensity of the light source can be modulated with 8-bit, the ferroelectric liquid crystal only needs to be driven at about 2.08 msec. When displaying a 10-bit gradation, the driving time of the ferroelectric liquid crystal is about 1.67 msec. Thus, this liquid crystal display element driving method is a practical driving method in accordance with the response speed of the ferroelectric liquid crystal.
[0019]
Here, an image made up of one gradation bit is called a “bit plane”, and its display time is called a “bit plane time”. For example, as shown in FIG. 6, when displaying an 8-bit gray scale, the number of bit planes is 8, and the total time of 8 bit planes is 1 frame.
[0020]
By the way, in recent years, digital display elements such as so-called “plasma display panels” have been developed, and further improvement in image quality of display images is desired. In digital gradation display, 8-bit display is said to be sufficient as a minimum gradation display but insufficient in terms of improving image quality.
[0021]
On the other hand, in the digital gradation display, a problem of false contour occurs. This is because the time-divided bit plane time is long when performing field sequential driving, and when the displayed light-emitting point is followed with the eye, the temporal shift of the light-emitting pattern is a spatial shift. It is a phenomenon that occurs by being converted to. Therefore, this problem can be reduced by shortening the bit plane time.
[0022]
However, in practice, the lower limit of the 1-bit plane time is determined by problems such as the response time of driving the ferroelectric liquid crystal, device structure, power consumption, and data transfer speed. In addition to the problem of false contours, the upper limit of 1-bit plane time is determined by color breakup, the number of gradations, and the like. Considering that the frame frequency is usually 60 Hz, the 1-bit plane time should be set to 100 μs to several hundreds μs. That is, the bit plane time is uniquely determined according to specifications such as the number of pixels and the number of gradations.
[0023]
For example, in the display element proposed by the present applicants, 256 gradations are provided for each color of R (red), G (green), and B (blue), and one frame is 36 bit planes × 3 colors = 108. Each bit plane is approximately 150 μsec (more precisely, 1 sec / 30 Hz / 2 frames / 108 bit plane, up to 154.3 μsec). In this case, the ferroelectric liquid crystal is designed to always switch once per bit plane.
[0024]
As described above, in the driving method for refreshing the memory state for each bit plane, the next driving voltage waveform is applied before the transmittance (reflectance) decreases, so that the material having insufficient memory characteristics, for example, bistability is not satisfactory. There is an advantage that even a material that is sufficient and the memory cone angle falls within the bit plane time and the transmission (reflection) rate decreases can be used. In this case, the frequency to be refreshed is mainly determined by the bit plane time.
[0025]
As described above, the driving voltage waveform of the ferroelectric liquid crystal in the field sequential gradation display method has to be used in 1 bit plane time, and there is a problem that only a simple driving voltage waveform can be used. In addition, when the display image has a high definition, the unit pixel area is reduced, so that the driving circuit to be configured must be accommodated in the pixel area. In order to reduce the burden on the driving circuit, A simpler driving voltage waveform is further required.
[0026]
[Problems to be solved by the invention]
By the way, in the manufacturing process of a liquid crystal display element, impurity ions generated and mixed are included in the liquid crystal in various processes such as liquid crystal synthesis, alignment film preparation, liquid crystal injection, and the like, which deteriorates the display image quality. It is known to cause.
[0027]
At present, it can be said that it is impossible to completely remove the impurity ions in the liquid crystal panel. Furthermore, even if it can be removed, a phenomenon occurs in which impurity ions are generated by voltage application during driving. The following is considered as the behavior of the impurity ions in the liquid crystal panel.
[0028]
(1) Ion dissociation is promoted in the liquid crystal due to temperature rise and voltage application.
(2) Charged ions move along the electric field in the liquid crystal generated by voltage application.
(3) Ions reaching the alignment film are physically or chemically adsorbed.
(4) If the waveform applied to the cell is alternating, ions repeatedly perform adsorption and desorption.
(5) A part of the dissociated ions returns to neutral molecules by recombination or the like.
[0029]
In the case of such ion behavior, if the following asymmetry occurs on the two electrode substrates facing each other and driving, the ion behavior is also asymmetric at the interface between the liquid crystal and the alignment film. Sex occurs.
(1) Structural asymmetry between two opposing electrode substrates (between the TFT substrate side and the ITO substrate side, between the reflection side substrate and the transmission side substrate in a reflective cell or the like).
(2) Various conditions of the alignment film on the two opposing electrode substrates (film thickness, firing conditions, rubbing strength, etc.).
(3) Asymmetry of voltage application waveform (when a general drive voltage waveform uses an AC waveform such as a rectangular wave, but has an asymmetry with respect to GND (ground level)).
[0030]
These asymmetries create a non-equivalent situation between two electrode substrates in which the adsorption / desorption equilibrium of the cation and anion alignment film interface and the polarization state of the ionic species in the liquid crystal face each other. In this way, the state in which ions are polarized is difficult to relax, and is in a state almost similar to that when a DC component (V ′) having a certain polarity is applied between liquid crystal cells.
[0031]
That is, even if the voltage application is stopped thereafter, the state in which the voltage V ′ is applied, that is, the state in which the voltage is applied to the liquid crystal molecules, is maintained inside the liquid crystal cell. That is, even if a symmetrical rectangular waveform voltage (amplitude V) is applied to the liquid crystal cell, the effective voltage applied to the inside of the liquid crystal is (V + V ′) on the positive side and (−V + V ′) on the negative side. The effective voltage applied to the liquid crystal is not symmetrical. Due to such asymmetry, in a liquid crystal display element in which the effective voltage is reflected in the light transmittance, such as the “TN” system, the liquid crystal molecules are observed to fluctuate and decrease as flicker. It will cause quality degradation.
[0032]
On the other hand, in the “SSFLC” mode, the voltage signal for selecting one of the two states of ON or OFF is the positive voltage signal (V), and the voltage signal for selecting the other state is the negative voltage signal. In the case of (−V), when V ′ is a positive value, (−V−V ′) is effectively converted to a positive voltage signal when a negative voltage signal is applied in a reverse polarity state. At the time of application, (V−V ′) is applied. Therefore, the response speed to the state selected by the negative voltage signal is increased by the increase of the effective voltage, and conversely, the response speed to the state selected by the positive voltage signal is the decrease of the effective voltage. If it becomes slow and V ′ becomes large, (V−V ′) does not reach the threshold value and does not respond.
[0033]
Further, under such a situation where the internal direct current voltage (DC) component becomes large, the liquid crystal molecules themselves may even undergo electrolysis. In recent years, the stability of liquid crystal materials has improved, and although there is almost no possibility of electrolysis in the range of general driving voltage, the possibility of deterioration of display image quality due to the effective DC component of the driving voltage waveform is wiped away. Absent.
[0034]
Therefore, it is natural that the driving voltage waveform of the conventional liquid crystal display element is electrically neutral, and positive and negative voltages such as a rectangular wave, sine wave, cosine wave, and triangular wave with an offset voltage of 0 V are present. A so-called alternating current drive is performed in which the positive and negative voltages are symmetrical with respect to 0 V alternately.
[0035]
For example, in the case of a liquid crystal display element such as the “TN” mode, driving by a rectangular wave with an offset voltage of 0 V and driving by a gate element of a TFT with a rectangular wave are used. It is set to keep the sex.
[0036]
In addition, when applying a pulse voltage that selects one of the on and off states, as in the “SSFLC” mode liquid crystal display element, a reverse polarity voltage waveform that cancels this is combined, and a DC voltage is selected within one selection time. Drive methods have been used, such as canceling the components, or inserting reverse polarity voltage pulses to cancel the direct current component for a longer time, eg, as an average over multiple frames.
[0037]
However, in such a “SSFLC” mode liquid crystal display element, in order to maintain electrical neutrality, a voltage waveform that does not actually contribute to driving of the liquid crystal is equivalent to a voltage waveform for selecting a state for a time equivalent to that. Therefore, the bit plane time must be shortened by that amount, and the characteristics such as luminance and gradation are deteriorated. In addition, the time given for the response of the liquid crystal is shortened, and the burden on the liquid crystal material is increased.
[0038]
Accordingly, the present invention is intended to provide a driving method of a liquid crystal display element that is simple and prevents deterioration of display image quality due to impurity ions while ensuring a sufficient bit plane time. is there.
[0039]
[Means for Solving the Problems]
As a result of proactively examining a driving method that has an effective direct current component with a simple driving voltage waveform without being constrained by the driving voltage waveform maintaining the electrical neutrality as described above. In addition to preventing deterioration of the liquid crystal, the generation of internal DC voltage or electric field formed by impurity ions is extremely effectively suppressed, thereby preventing abnormal display and improving display reliability over a long period of time. A driving method that can be secured has been found and the present invention has been achieved.
[0040]
In this driving method, as in the “TN” mode, an internal DC voltage is not generated ideally, and driving with a rectangular wave voltage with an offset voltage of 0 V that maintains electrical neutrality, so-called AC driving, Deviation from electrical neutrality may occur due to variations in element characteristics, which is effective in that the effect of suppressing internal DC voltage formed by impurity ions can be obtained.
[0041]
That is, in the driving method of the liquid crystal display element according to the present invention, the first electrode is Formed on the first side A first substrate; On the second surface facing the first surface, so as to face the first electrode The second electrode Been formed Second substrate And a liquid crystal display device including a liquid crystal layer provided between the first surface and the second surface. Driving method of liquid crystal display element Because Within a certain time Involved in the display of Display signal period; A voltage signal having an amplitude larger than the amplitude of the voltage signal applied between the first electrode and the second electrode during the display signal period, wherein the positive polarity and the negative polarity change with time. Including Drive voltage waveform consisting of control signal period not related to display Is applied between the first electrode and the second electrode so that the time ratio of the control signal period to the entire driving voltage waveform is 5% or more and less than 50%. Including a voltage application step for suppressing an internal DC voltage generated in the liquid crystal display element Thus, the generation of the internal DC voltage can be suppressed extremely effectively.
[0042]
In order to clearly demonstrate the effect of the present invention, the voltage signal for selecting one of the two states of ON or OFF is a combination of only positive voltage signals and the voltage signal for selecting the other state Is a combination of only negative voltage signals. Alternatively, the voltage signal for selecting at least one of the two states, ON or OFF, is a combination of a positive voltage signal and a negative voltage, and the absolute value or time width of these voltages is made different so that one state You may make it produce the direct current | flow component of an internal voltage effectively within a selection period.
[0043]
That is, when selecting one of the on and off states, electrical neutrality is not maintained, and a potential due to the polarization of impurity ions, that is, an internal DC voltage is always generated between both electrodes. For example, when displaying an image over an arbitrary period of time, the number of on and off times is not necessarily the same, so the number of times one of the selected waveforms is applied increases, and within a certain period, between the electrodes. Will cause an internal DC voltage.
[0044]
FIG. 7 shows the relationship between the drive voltage waveform supplied to the liquid crystal display element and the reflected light intensity corresponding to this drive voltage. As shown in FIG. 7, when selecting an on (bright) state between 1 bit planes of about 154.3 μsec, a positive pulse (50 μsec width) is selected, and when selecting an off (dark) state, A negative pulse (50 μsec width) is applied. While the GND voltage is applied, the reflected light intensity is maintained substantially constant due to the bistability (memory property) of “SSFLC”.
[0045]
In the “SSFLC” mode, the memory property is generally used, but the memory property is not used, and a cone angle unique to the ferroelectric liquid crystal material can be used by a simple rectangular wave or the like. In this case, the actual luminance is not reflected, but since the cone angle unique to the ferroelectric liquid crystal material is used, the reflectance in each bit plane can be increased.
[0046]
As described above, when a drive voltage waveform that effectively generates an internal DC voltage within a selection period within a certain period is used, within a certain period of time, within a plurality of frames, or within one frame The generation of the internal DC voltage can be suppressed by inserting a voltage waveform having a polarity opposite to that of the internal DC voltage generated therebetween in a part of the inside.
[0047]
That is, in the present invention, driving for selecting one of the two states, on or off, is performed by a voltage signal that generates an effective internal DC voltage within the selection period, and is actually applied within a certain period. Inserts a waveform that controls (reduces) the magnitude of the internal DC voltage that does not contribute to driving the liquid crystal, for example, a reverse polarity voltage waveform.
[0048]
The time for applying the reverse polarity voltage waveform is ideally electrically neutralized by inserting it for the same time as the application time of the drive voltage waveform (applied voltage) for selecting the liquid crystal state. However, in practice, if a reverse-polarity voltage waveform that does not contribute to liquid crystal drive is inserted for the same amount of time as the selected waveform, the bit plane time must be shortened by that amount, and characteristics such as the brightness and gradation of the displayed image Cause deterioration. Therefore, in order not to deteriorate the characteristics such as the luminance and gradation of the display image, the application time of the voltage waveform for controlling (reducing) the magnitude of the internal DC voltage is preferably as short as possible.
[0049]
The present inventors do not contribute to the liquid crystal drive, and do not insert a voltage waveform that controls (reduces) the magnitude of the internal DC voltage for the same time as the drive time for selecting the liquid crystal state, but a shorter time. By inserting within the range, the generation of internal DC voltage formed by impurity ions can be extremely effectively suppressed, and a drive method that can prevent display abnormality and ensure display reliability over a long period of time has been found. This has led to the present invention.
[0050]
The internal DC voltage of the liquid crystal display element is defined by the voltage between the electrodes remaining after applying a certain drive voltage waveform. This is considered to be caused by the impurity ions existing in the liquid crystal cell being polarized by an effective direct current component of the driving voltage waveform and the like, and the polarized impurity ions forming an electric field.
[0051]
Actually, when an asymmetrical drive voltage waveform is applied, as shown in FIG. 8, the voltage of the DC component remaining between both electrodes is measured. In contrast, when the cell structure is also symmetrical between the opposing electrodes and a symmetrical drive voltage waveform is applied, the internal DC voltage becomes zero within the error range. As shown in FIG. 9 and FIG. 10, the internal DC voltage value is calculated by setting the time when the circuit is opened during measurement to 0, plotting the monitored voltage value logarithmically, and plotting the flat portion with a straight line. The value when extrapolated at time 0 was defined as the internal DC voltage value.
[0052]
Since this internal DC voltage exists regardless of the drive voltage waveform within a certain period, a phenomenon occurs in which the ground potential (GND) of the drive voltage waveform is offset by the electric field formed by the internal DC voltage. It is expected that.
[0053]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
(1) Manufacturing process of liquid crystal display element
Hereinafter, a manufacturing process of a liquid crystal display element to which the liquid crystal display element driving method according to the present invention is applied will be described.
[0054]
Since the manufacturing process of the liquid crystal panel and the response measurement of transmitted light are simple, the liquid crystal panels used for the following measurements are all transmissive panels in which the upper and lower substrates each have a transparent electrode as shown in FIG. . Further, as shown in FIG. 3, in the reflective panel in which one substrate is covered with an Al reflective film, both the panel manufacturing process and the reflected light response measurement are basically the same as those in the transmissive panel. . However, in the reflection type panel, since the incident light passes through the liquid crystal portion twice, the effective retardation is twice that of the transmission type panel having the same cell gap.
[0055]
A method for manufacturing a liquid crystal display element will be described below. All processes up to the end of liquid crystal injection are performed in a clean room.
[0056]
[Formation of transparent electrode]
First, a transparent electrode material layer made of ITO is formed on one surface of a glass substrate by sputtering, and a transparent electrode having a predetermined pattern is formed by photolithography. The general procedure for this patterning is as follows.
[0057]
(1) ITO sputtering
(2) Spin coating of resist
(3) Pre-baking and main baking of resist film
(4) Exposure of resist film
(5) Resist film etching
(6) Etching of ITO
(7) Cleaning
(8) Stripping of resist film
(9) Cleaning
[0058]
[Washing the substrate]
In the clean room, the glass substrate is cleaned and dried. This cleaning and drying treatment is performed as follows using, for example, a “three-tank ultrasonic cleaner” (manufactured by Sun Electronics Co., Ltd.).
[0059]
For the first layer, ultrasonic cleaning is performed for 3 minutes using an alkali cleaning (Scat × 20) and shaking the substrate at a bath temperature of 45 ° C.
For the second layer, the substrate is swung while taking a pure water shower, and ultrasonic rinsing for 3 minutes is performed three times to wash off the alkaline detergent.
For the third layer, the substrate is immersed in pure water at a bath temperature of 80 ° C. for 1 minute, and then the substrate is gradually lifted from the pure water by an elevator mechanism and left to dry.
[0060]
Furthermore, UV ozone cleaning is performed at room temperature for 10 minutes using, for example, “UV dry stepper cleaner” (manufactured by Samco International Laboratory Co., Ltd.).
[0061]
(Preparation of alignment film)
There are roughly two types of liquid crystal alignment methods. One is an organic thin film rubbing method, and the other is an oblique deposition method of an inorganic material such as SiO (silicon oxide). When a rubbing film is used as an alignment film, productivity is good and the area can be easily increased. Therefore, many liquid crystal display elements are now industrially produced using the rubbing film as an alignment film. On the other hand, when a SiO obliquely deposited film is used as the alignment film, good memory properties can be realized although there is a problem in productivity.
[0062]
Therefore, the difference in the alignment characteristics of the liquid crystal depending on the alignment film material of the liquid crystal display element is examined. Here, as the alignment film material, for example, a SiO oblique deposition film, a polyimide (hereinafter abbreviated as PI) “AL0656” manufactured by JSR Corporation, or the like can be used.
[0063]
[SiO obliquely deposited film]
The SiO oblique vapor deposition film is produced by the following method. The deposition source SiO (deposition material) is accommodated in a deposition boat having a hole serving as a point source. Vapor deposition is performed by setting an angle θ between a line connecting SiO and a deposition position and a normal line of a deposition surface of the glass substrate to, for example, 85 °. In order to make the film structure uniform, the angle θ needs to be accurate within several degrees. Moreover, since the distance between the vapor deposition source and the vapor deposition location also affects the shape and film thickness distribution of the SiO pillar, for example, it is separated by 40 cm or more.
[0064]
[Rubbing film]
The polyimide rubbing alignment film is formed by the following method. First, the substrate is rotated at a predetermined rotation speed (for example, 3500 rpm) and, for example, a PI alignment film “AL0656” manufactured by JSR is applied by spin coating. Then, after baking at 180 ° C. for 4 hours, rubbing is performed under the conditions of a roller rotation speed of 300 rpm, a stage speed of 2 mm / sec, and an indentation amount of 0.200 mm.
[0065]
[Assembly of the cell]
Two glass substrates with the alignment film and ITO described above are prepared, the alignment surfaces are opposed to each other, and the alignment processing direction is incorporated in parallel. An ultraviolet curable resin in which a gap material is dispersed is applied on one alignment film of these two glass substrates by seal printing so as to be outside the display region. As the gap material, for example, a 1.0 μm-diameter true ball manufactured by Catalyst Kasei Co., Ltd. can be used. Examples of the ultraviolet curable resin in which such a gap material is dispersed include “PHOTOREC” (trade name: manufactured by Toray Fine Chemical Co., Ltd.). Then, the two glass substrates are combined, and the resin is cured by irradiating with ultraviolet rays to produce a cell having a gap of 1.0 μm.
[0066]
[Injection of liquid crystal]
Next, the liquid crystal element is left in a constant temperature bath, and after raising the temperature to a temperature at which the liquid crystal becomes isotropic, an injection port provided in a part of the cell is immersed in the ferroelectric liquid crystal. As the ferroelectric liquid crystal, for example, “CS-1031”, “CS-1025”, “CS-1028”, etc. manufactured by Chisso Corporation are used. Thereafter, the cell is cooled to room temperature at a rate of 1 ° C./min and taken out of the thermostatic bath. Then, the assembly of the liquid crystal panel is completed by sealing (sealing) the inlet.
[0067]
(2) Liquid crystal materials and panel components used in the practice of the present invention
The ferroelectric liquid crystal that can be used in the liquid crystal display device for carrying out the method for driving the liquid crystal display device according to the present invention may actually be a liquid crystal formed by mixing a chiral compound and a non-chiral compound. It may be composed of only one type or a mixture of plural types.
[0068]
Here, as the chiral compound, there are a pyrimidine series, a biphenyl series, a phenylbenzoate series, and the like (however, these ferroelectric liquid crystals may exhibit a chiral nematic phase, a smectic phase, etc. depending on a change in temperature). Non-chiral compounds include biphenyl, terphenyl, tricyclic cyclohexyl, cyclohexyl, biphenylcyclohexane, cyclohexylethane, ester, pyrimidine, pyridazine, ethane, and dioxane.
[0069]
Further, instead of the above-described ferroelectric liquid crystal, an antiferroelectric liquid crystal can also be used. Further, in place of the above-described ferroelectric liquid crystal, nematic liquid crystal that can be applied to the “TN” mode and the “STN” mode can also be used.
[0070]
Also for the constituent members of the liquid crystal element, a transparent glass substrate can be used as the substrate, ITO or aluminum can be used as the electrode layer, and a polyimide film or SiO oblique vapor deposition film that has been rubbed as the liquid crystal alignment film can be used. As the electrode layer, a transparent electrode such as tin oxide or indium oxide can be used in addition to ITO. Various conventionally known materials can be used as constituent materials of the liquid crystal element such as a transparent substrate, a spacer, and a sealing material. Further, when the liquid crystal display element is used as a reflection type, a material having high reflectivity such as aluminum or silver can be used as the reflection film.
[0071]
In addition to the optical modulator, the liquid crystal element described above can be used as an optical shutter, an optical switch, an optical blind, and the like. Further, if an electro-optical element is combined, it can be used as an A / D converter or an optical logic circuit. Can also be applied.
[0072]
(3) Measurement of electro-optical characteristics
A liquid crystal panel is placed under a microscope under crossed Nicols, and an intended drive voltage waveform is applied to the liquid crystal panel using, for example, “arbitrary waveform generator AWG-2021” manufactured by Sony Tecrotonics. Then, the transmitted light intensity in a state corresponding to each drive voltage waveform is detected by a photomultiplier tube. The output of this photomultiplier tube is taken into a control circuit (computer) via, for example, a digital oscilloscope manufactured by Sony Tecrotonics.
[0073]
(4) Measurement of internal DC voltage
For internal DC voltage measurement, for example, using “Arbitrary Waveform Generator BIOMATION Pragmatic 2202A” manufactured by Toyo Technica Co., Ltd., first, the drive voltage waveform output from this waveform generator is used, for example, “High Voltage Sample Hold” The voltage is applied to the liquid crystal panel in the shield box via the amplifier VHR-AMP01 ”.
[0074]
When the control voltage waveform output in synchronization with the waveform generator is turned off, the “high voltage sample and hold amplifier VHR-AMP01” uses the “VG terminal” − “OUT terminal” as an open circuit voltage between the electrodes of the liquid crystal panel. ”Is detected. This detection output is addressed to a control circuit (computer) via an A / D (analog / digital) converter or an oscilloscope.
[0075]
The shield box is placed in a thermostat and can be measured while maintaining an arbitrary temperature (usually 40 ° C.). Immediately before the open circuit operation is performed, when a voltage waveform other than 0 V is applied, electrostatic (electronic) injected charges from the liquid crystal panel may affect the measurement. Therefore, by short-circuiting (0V) between the electrodes for a short time (for example, 100μsec) and removing such components, the internal DC voltage due to ion polarization, which is the original measurement object, is observed later than the relaxation of electrons. can do.
[0076]
The internal DC voltage immediately before short-circuiting in this way cannot be directly measured because of an electrostatic (electronic) injected charge component. Thus, the internal DC voltage value is obtained as shown in FIG. 8 by plotting the change of the voltage between both electrodes after the short circuit with time by plotting the voltage on a log scale and extrapolating the time immediately after the short circuit. be able to. In addition, when an arbitrary voltage waveform is continuously applied and measured, if the internal DC voltage accumulated by applying the voltage is small, the measurement target is induced by spontaneous polarization (hereinafter referred to as Ps). Need to be separated from voltage.
[0077]
Therefore, the result (Va) measured in the normal state is combined with the result (Vb) in the case of applying a reverse polarity voltage waveform of 50 μsec that reverses Ps from the previous state immediately before the short circuit operation, and {(Va + Vb) / 2} is the internal DC voltage value due to the polarization of ions, whereby the voltage component induced by Ps can be removed.
[0078]
Here, in order to unify the initial state in each measurement, the temperature is raised to an isotropic phase in a short-circuited state for 10 minutes immediately before the measurement, and after being held, cooled to room temperature, Results with good reproducibility can be obtained.
[0079]
(5) Transient current measurement
For the transient current measurement, for example, using an “arbitrary waveform generator BIOMATION Pragmatic 2202A” manufactured by Toyo Technica Co., Ltd., the drive voltage waveform output from the waveform generator is first converted into, for example, “Current-voltage conversion amplifier Model 6250” manufactured by the same company. The voltage is applied to the liquid crystal panel in the shield box.
[0080]
The “current-voltage conversion amplifier Model 6250” pauses the current detection operation when the control voltage waveform output in synchronization with the waveform generator is turned on, and performs the current detection operation again when the control voltage waveform is turned off. Resume. By utilizing such characteristics, the on-state of the control voltage waveform is synchronized with the region where the voltage of the drive voltage waveform applied to the liquid crystal panel changes sharply (typically when it changes stepwise) Is 10 μsec before and 50 μsec after, 60 μsec in total), and as a value, a large inrush current (electrostatic (electronic) injection current component) can be removed. Only a small current component can be observed with high accuracy as a value associated with the displacement of the impurity ions to be measured.
[0081]
Further, in the “SSFLC” mode panel, as shown in FIG. 11, a Ps inversion current generated along with the Ps inversion can be observed, and a change in the alignment of the liquid crystal can be observed as a current. In this “SSFLC” mode, the Ps reversal current also takes a relatively large value. Therefore, in order to observe the current associated with the displacement of ions, as shown in FIG. It is necessary to lengthen the area.
[0082]
(6) Waveform shape constituting one bit plane used in the present invention
Next, the shape of the driving voltage waveform of the 1-bit plane for selecting the two states used in the liquid crystal element driving method according to the present invention will be sequentially described as shown in FIGS. FIGS. 13 to 17 show various examples (waveforms A to E) of drive voltage waveforms, taking as an example one bit plane corresponding to 154.3 μsec.
[0083]
[1-bit plane waveform A]
As shown in FIG. 13, the waveform A is a combination of a positive voltage V1 (t1) and 0 V (t2) as a voltage waveform for selecting one of the two states, on and off, and the other state. In this example, the voltage waveform to be selected is a combination of the negative voltage V2 (t1) and 0 V (t2).
[0084]
[1-bit plane waveform B]
As shown in FIG. 14, the waveform B has only a positive voltage V1 as a voltage waveform for selecting one of two states, on and off, and a negative voltage waveform for selecting the other state. This is an example in which only the constant voltage V2 is selected.
[0085]
[1-bit plane waveform C]
As shown in FIG. 15, the waveform C is a combination (t1, t2) of the positive voltages V1, V3, and the other state is selected as a voltage waveform for selecting one of the two states of ON or OFF. This is an example in which the voltage waveform to be used is a combination (t1, t2) of the negative voltage V2, V4.
[0086]
[1-bit plane waveform D]
As shown in FIG. 16, the waveform D is a combination of positive voltage V1, V3 and negative voltage V5 (t1, t2, t3), which is a voltage waveform for selecting one of the two ON or OFF states. In addition, the voltage waveform for selecting the other state is a combination (t1, t2, t3) of the negative voltage V2, V4 and the positive voltage V6, the absolute values or time widths of these voltages are not equal, and within the selection period of one state This is an example of a driving method that effectively generates an internal DC voltage.
[0087]
[1-bit plane waveform E]
As shown in FIG. 17, the waveform E is a combination of positive voltage V1, V3, negative voltage V5 and 0V (t1, t2, t3, t4). ) And the voltage waveform for selecting the other state is a combination (t1, t2, t3, t4) of the negative voltage V2, V4, the positive voltage V6 and 0V, and the absolute value or time width of the positive and negative voltages is This is an example of a driving method in which an internal DC voltage is effectively generated within a selection period of one state.
[0088]
As shown in FIG. 18, the voltage waveform of the 1-bit plane for controlling the internal DC voltage used in the liquid crystal display element driving method according to the present invention has one of two states, on and off. Used when the drive to be selected uses a drive voltage waveform that generates an effective internal DC voltage within the selection period, and controls the magnitude of the internal DC voltage that does not contribute to liquid crystal drive within a certain period of time. A waveform having a reverse polarity for the purpose of (reduction) is inserted. The voltage waveform shown in FIG. 18 is an example of the control voltage waveform of the internal DC voltage in the driving method of the liquid crystal display element according to the present invention, and corresponds to the reverse polarity of the waveform B shown in FIG. .
[0089]
The voltage waveform for controlling the internal DC voltage is not limited to the example shown in FIG. 18, and is a voltage for selecting one of the waveforms A and C to E shown in FIGS. 13, 15 to 17. It is possible to use a voltage waveform that has a waveform shape and exhibits an opposite polarity to an effective internal DC voltage generated within a selection period of one state. In this case, it is only necessary to combine two types of 1-bit plane waveforms through all the waveforms, and the load on the waveform generation circuit and element characteristics can be reduced.
[0090]
In other words, although the load on the waveform generation circuit and the element characteristics increases, in order to more effectively suppress the internal DC voltage, the 1-bit plane waveform of the waveforms A to E shown in FIGS. They can be used in different combinations or in combination.
[0091]
In the present invention, the control voltage waveform of the internal DC voltage constituted by continuing one bit plane or a plurality of bit planes is an effective internal DC voltage generated within one state selection period. Is a DC voltage waveform with a reverse polarity, or in the case of the waveforms A, D, and E shown in FIGS. This is the biggest feature.
[0092]
(7) Example of inserting an internal DC voltage control waveform in the present invention
Even if the voltage waveform of the 1-bit plane is the waveform C to the waveform E shown in FIGS. 15 to 17, it can be regarded as the waveform B shown in FIG. 14 by taking the time average. The internal DC voltage can be controlled by inserting the waveform B and the voltage waveform for controlling the internal DC voltage shown in FIGS. During the application of the control voltage waveform, display is not performed by not irradiating illumination light from an LED or the like.
[0093]
[Drive voltage waveform 1]
In this example, as shown in FIG. 19, a control voltage waveform is inserted into a voltage waveform constituting a 1-bit plane.
[0094]
When the parameters of the waveform E shown in FIG. 17 are V2 = V4, V1 = V3, t1 = t2 = 37.5 μsec, t3 = 112.5 μsec, the internal DC voltage is set to the first 25% in one bit plane. Can be regarded as a waveform having a waveform period for controlling the state, and then a waveform period for selecting one state of the liquid crystal.
[0095]
Here, a waveform in which a waveform period for selecting a liquid crystal state is a positive voltage and a 1-bit plane waveform in which a control voltage waveform period is a negative voltage is a 108-bit plane continuous waveform is a drive voltage waveform 1.
[0096]
[Drive voltage waveform 2]
In this example, as shown in FIG. 20, one frame is composed of 108 bit planes, and the control voltage waveform of the internal DC voltage is not inserted.
[0097]
[Drive voltage waveforms 3 and 4]
In this example, as shown in FIGS. 21 and 22, one frame is composed of 108 bit planes, and a rectangular wave of one cycle of 4 bit planes for each 36 bit plane is used as an internal DC voltage control waveform for a total of 12 bit planes. This is an example of insertion. Of these, the polarity of the display waveform period is positive as “driving voltage waveform 3” as shown in FIG. 21, and the negative polarity is “driving voltage waveform 4” as shown in FIG.
[0098]
[Drive voltage waveforms 5 to 8]
In this example, as shown in (A) to (D) of FIG. 23, one frame is composed of 108 bit planes, and continuous internal DC voltage control waveforms for 6 bit planes are inserted, and the control waveform period This is an example in which the shape (frequency) of the rectangular wave is changed. The control waveform period is about 0.93 msec, and the time ratio of the entire drive voltage waveform is 5.6%.
[0099]
[Drive voltage waveforms 9 to 13]
In this example, as shown in (A) to (E) of FIG. 24, one frame is composed of 108 bit planes, and continuous internal DC voltage control waveforms for 12 bit planes are inserted, and the control waveform period This is an example in which the shape (frequency) of the rectangular wave is changed. The control waveform period is about 1.85 msec, and the time ratio of the entire drive voltage waveform is 11.1%. These “drive voltage waveforms 9 to 13” have the same time ratio as the above-mentioned “drive voltage waveform 3” in the entire drive voltage waveform of the internal DC voltage control waveform.
[0100]
[Drive voltage waveforms 14 to 19]
In this example, as shown in (A) to (F) of FIG. 25, one frame is composed of 108 bit planes, continuous DC voltage control waveforms for 24 bit planes are inserted, and the control waveform period This is an example in which the shape (frequency) of the rectangular wave is changed. This control waveform period is about 3.70 msec and occupies the entire drive voltage waveform, but the ratio is 22.2%.
[0101]
[Drive voltage waveforms 20 to 25]
In this example, as shown in (A) to (F) of FIG. 26, one frame is composed of 108 bit planes, and a continuous internal DC voltage control waveform for 36 bit planes is inserted, and the control waveform period This is an example in which the shape (frequency) of the rectangular wave is changed. This control waveform period is about 5.55 msec, and the ratio to the entire drive voltage waveform is 33.3%.
[0102]
[Drive voltage waveforms 26 to 31]
In this example, as shown in (A) to (F) of FIG. 27, one frame is composed of 108 bit planes, and a continuous internal DC voltage control waveform for 48 bit planes is inserted, and the control waveform period This is an example in which the shape (frequency) of the rectangular wave is changed. This control waveform period is about 7.41 msec, and the ratio of the entire control voltage waveform is 44.4%.
[0103]
[Drive voltage waveforms 32 to 36]
In this example, as shown in (A) to (E) of FIG. 28, the display waveform period is a negative voltage in the aforementioned “drive voltage waveforms 6, 10, 15, 21, 27”. . In these drive voltage waveforms, 1.5 cycles of rectangular waves are inserted in the control waveform period, and there are one positive voltage period and two negative voltage periods.
[0104]
These drive voltage waveforms are intended to be confirmed because the effect of the control waveform period is expected to differ depending on the polarity of the voltage in the display waveform period.
[0105]
[Drive voltage waveforms 37 to 40]
As in the above-mentioned “drive voltage waveforms 1 to 36”, in the display waveform period related to display, only the state selected by the positive voltage of the two states of the liquid crystal is always selected, or the state selected by the negative voltage It can be easily predicted that the internal DC voltage will be accumulated most when a voltage having a waveform of only is applied.
[0106]
For confirmation, during the display waveform period involved in the display, from the case where only the state selected by the application of the positive voltage is applied to the case where the internal DC voltage is not accumulated due to electrical neutralization by the application of the voltage waveform. A case where the ratio between the voltage waveform and the negative voltage waveform is changed will be described.
[0107]
That is, as shown in (A) to (D) of FIG. 29, in the waveform in which one frame is made up of 108 bit planes as in the aforementioned “drive voltage waveform 7”, the control voltage waveform is changed to the 36 bit plane. When the minute (5.55 msec, 33%) is inserted, the voltage waveform used for display is 72 bit planes. In the drive voltage waveforms 37 to 40, the ratio of the positive voltage waveform in the time range in which the voltage waveform period for the 72-bit plane related to the display is allocated is 63/72 (87.5%) and 54/72 (75 %), 45/72 (62.5%), 36/72 (50%), and a rectangular wave is inserted as a control voltage waveform for 36 bit planes.
[0108]
[Drive voltage waveforms 41 and 42]
In this example, as shown in FIGS. 30B and 30C, the rectangular wave voltage values (V3, V4) in the control waveform period of the “drive voltage waveform 24” described above are expressed as voltages in the display waveform period. In this example, the value is different from (V1, V2). In actual driving, it is expected that the signal voltage in the display waveform period and the signal voltage in the control waveform period are different, so that the driving circuit, the substrate, and the like are expected to be complicated.
[0109]
In the “driving voltage waveform 41”, | V1 | <| V3 | and | V2 | <| V4 |. In the “driving voltage waveform 42”, | V1 |> | V3 |, | V2 |> | V4 |.
[0110]
(8) Regarding the effective DC voltage per unit time of the drive voltage waveform used in the present invention, the symmetry of the positive voltage and the negative voltage of the applied waveform is positive for the above-mentioned “drive voltage waveforms 1 to 42”. Therefore, it can be said that it is pseudo direct current (DC) drive.
[0111]
As shown in FIG. 27, these effective DC voltage components per unit time were calculated as shown in [Table 1] and [Table 2] based on the driving voltage shown below.
[0112]
[Table 1]

[0113]
[Table 2]

[0114]
Here, in the “drive voltage waveforms 1 to 31”, the display selection voltage waveform V1 = + 7V and the internal DC control voltage waveform V1 / V2 = + 7V / −5V. In the “drive voltage waveforms 32 to 36”, the display selection voltage waveform V2 = −5V and the internal DC control voltage waveform V1 / V2 = + 7V / −5V. In the “drive voltage waveforms 37 to 40”, the display selection voltage waveform V1 / V2 = + 7V / −5V and the internal DC control voltage waveform V1 / V2 = + 7V / −5V. In the “drive voltage waveforms 41 to 42”, the display selection voltage waveform V1 = + 7V, the internal DC control voltage waveform V3 / V4 = + 9V / −9V, and + 3V / −3V.
[0115]
(9) Asymmetry parameter of voltage area intensity per unit time of drive voltage waveform used in the present invention
With respect to the “drive voltage waveforms 1 to 42” shown in (8) above, the value obtained by standardizing the voltage integral intensity per unit time with the maximum absolute value of the applied voltage in all the waveforms of the drive voltage, that is, FIG. The area strength asymmetry parameter R shown in FIG.
[0116]
Further, the asymmetry parameter R ′ of the area intensity only for the control waveform period can be calculated in the same manner. This R ′ value is obtained in the case of “driving voltage waveforms 6, 10, 15, 21, 27, 32 to 36” in which rectangular waves of 1.5 cycles (two positive polarity periods and one negative polarity period) are inserted. 0.429 or less, but in other “driving voltage waveforms 2 to 40”, it is 0.142 or less. Further, it is 0 in the “driving voltage waveforms 41 and 42”.
[0117]
【Example】
As an example, the liquid crystal material is “CS-1031” and the alignment film is “AL1051”, the liquid crystal material is “CS-1025” and the alignment film is “AL1051”, and the liquid crystal material is “CS-1028” and the alignment film is Three types of liquid crystal panels of “SiO obliquely deposited film” were prepared, and for each of these liquid crystal panels, “drive voltage waveforms 1 to 31” (display selection waveform V1 = + 7 V, internal DC control waveform V1 / V2 = + 7 V / −5V), “drive voltage waveforms 32 to 36” (display selection waveform V2 = −5V, internal DC control waveform V1 / V2 = + 7V / −5V), “drive voltage waveforms 37 to 40” (display selection waveform V1 / V2) = + 7V / -5V, internal DC control waveform V1 / V2 = + 7V / -5V) and "drive voltage waveform 41 to 42" (display selection waveform V1 = + 7V, internal DC control waveform V3 / V4 = + 9V) -9 V, by applying the + 3V / -3 V), as shown in Table 1 and Table 2, to define the "Examples 1 to 140", were measured for the internal DC voltage.
[0118]
The internal DC voltage value (accumulated amount of internal DC voltage) after applying the drive voltage waveform for 24 hours at 40 ° C. is as shown in [Table 1].
[0119]
As is clear from these [Table 1] and [Table 2], when “AL1051” is used as the alignment film, the amount of internal DC voltage accumulated depending on the type of drive voltage waveform is not dependent on the liquid crystal material. Similar profiles are shown.
[0120]
When the “driving voltage waveform 2” that does not insert the internal DC voltage control waveform is used, the internal DC voltage is accumulated up to about 2.5V.
[0121]
When the display selection waveform period is a positive voltage waveform and an internal DC voltage control waveform is inserted, an internal DC voltage control waveform period of about 5.6% of the entire drive voltage waveform 5 to 8 is obtained. Is inserted, the internal DC voltage is reduced to about 1.6 to 2 V, and when an internal DC voltage control waveform period of about 11.1% of the whole is inserted as shown in “drive voltage waveforms 9 to 13”. The internal DC voltage is reduced to 0.6 to 0.9 V, and the effect of the internal DC voltage control is increased. Further, when the time ratio of the internal DC voltage control waveform period is further increased, the internal DC voltage is remarkably decreased accordingly.
[0122]
“Drive voltage waveform 1” in which 50% of the internal DC voltage control period is inserted in the 1-bit plane is compared with the “drive voltage waveform 1” that is inserted in the 108-bit plane by changing the time ratio of the internal DC voltage control period. It is the same as that which inserted only 11.1% like 9 thru | or 13 ". Since the time ratio for inserting the internal DC voltage control period is preferably small as display characteristics, it is 108 rather than inserting the internal DC voltage control waveform in a very fast region of 1 bit plane unit (154.3 μsec or less). It was confirmed that the effect was more noticeable when inserted in bit plane units (1 frame, 16.6 msec or less). These are considered to correlate with the polarization rate and relaxation rate accompanying the movement of ions in the panel, and because the polarized ions do not respond to the internal DC voltage control period for the high-frequency waveform. It is done.
[0123]
In addition, even if the display selection waveform period is a waveform having a negative voltage as in “drive voltage waveform 4”, a positive voltage waveform is inserted into the display selection waveform period by inserting the internal DC voltage control waveform. As in “Drive voltage waveform 3”, it was confirmed that accumulation of internal DC voltage can be suppressed without problems.
[0124]
In the “drive voltage waveforms 24, 37 to 40” in which the display selection waveform period is changed from the waveform of the positive voltage to the same number of waveforms of the positive and negative voltages, the asymmetry of the display period is alleviated. As can be seen, it was confirmed that the amount of internal DC voltage accumulated decreased as the bias in the waveform period decreased.
[0125]
In “drive voltage waveforms 6, 10, 15, 21, 27” in which the display selection waveform periods are all positive voltages, and in “drive voltage waveforms 32 to 36” in which the display selection waveform periods are all negative voltages, the control waveforms The period is obtained by inserting a rectangular wave of 1.5 periods in which one positive voltage period and two negative voltage periods are inserted. For this reason, it can be expected that the effect of the control period is inferior when the polarity of the signal period is negative than when it is positive. Compared with the ratio of the internal DC voltage to the effective DC voltage with the time width of each control waveform period, the result was as expected when the time width of the control waveform period was short. Was found to be smaller.
[0126]
Next, the “drive voltage waveform 41” having a large value and the “drive voltage waveform” having a small value are compared with the “drive voltage waveform 24” having the same amplitude value of the rectangular wave in the control waveform period as the voltage in the display selection waveform period. In the case of “42”, the use of the “drive voltage waveform 41” having a large amplitude value is more effective in suppressing the internal DC voltage.
[0127]
When SiO is used as the alignment film, as shown in [Table 1] and [Table 2], the internal DC voltage value is remarkably increased as compared with the case where the PI-based alignment film is used. ing. In particular, in the case where the internal DC voltage control period is not inserted and the case where the insertion period is short, the internal DC voltage is accumulated up to the effective DC voltage of the applied drive voltage waveform.
[0128]
Such a difference between the PI-based alignment film and the SiO oblique deposition film is that even if the liquid crystal material is the same, the amount of ions in the panel after being configured as a liquid crystal panel is greater in the latter than in the former. It is caused by more than one digit.
[0129]
Then, as the ratio of inserting the internal DC voltage control period in the drive voltage waveform is increased, the accumulated amount of the internal DC voltage is suppressed. In particular, if the internal DC voltage control period is 12 bit planes or more, that is, 11.1% of the entire drive voltage waveform, it can be suppressed to about 1/3 of the case where no insertion is made at all. If it is 33.3% of the entire driving voltage waveform, the internal DC voltage hardly accumulates.
[0130]
Next, as shown in FIG. 31, the accumulation state of the internal DC voltage value according to the application time of the drive voltage waveform at a temperature of 40 ° C. will be considered. FIG. 31 shows a cell with each specification using “CS-1031” as the liquid crystal material of the example and “AL1051” as the alignment film material, and “drive voltage waveforms 2, 5, 11, 16, 24, 25, 30 and 31 ”are applied at a temperature of 40 ° C., and the amount of internal DC voltage accumulated by ions when the application time is changed is shown. As can be seen from FIG. 31, in the “driving voltage waveform 2” in which the internal DC voltage control waveform is not inserted, it can be confirmed that the internal DC voltage is remarkably accumulated according to the application time.
[0131]
The internal DC voltage is accumulated with the application time of the desired drive voltage waveform, but the tendency of the internal DC voltage accumulation to be suppressed does not change as the time ratio of the internal DC voltage control waveform period increases. Here, in the “driving voltage waveform 5” having the smallest time ratio of the internal DC voltage control period of 5.6%, the accumulation of the internal DC voltage reaches about 2V or more with respect to continuous application for 1000 hours. The effect of is not seen. Furthermore, in the “driving voltage waveform 11” in which the time ratio of the internal DC voltage control period is increased to 11.1%, the accumulation of the internal DC voltage is decreased to 1 V or less, and the suppression effect is increased.
[0132]
In the “driving voltage waveforms 16, 24, 25, 30, 31” having a higher time ratio of the internal DC voltage control period than the “driving voltage waveform 11”, the effect of suppressing the internal DC voltage becomes remarkable, and the continuous DC voltage is 1000 hours. Even when applied, the internal DC voltage is 0.3 V or less.
[0133]
Next, as shown in FIG. 32, the result of the ionic current behavior at the time of applying the drive voltage waveform at a temperature of 40 ° C. will be considered. FIG. 32 shows an example in which a liquid crystal cell using “CS-1031” as the liquid crystal material and “AL1051” as the alignment film material is initialized by the heating short circuit process, and then the “drive voltage waveforms 11, 18,. 25, 30 "shows the result of measuring the ionic current when applied at a temperature of 40 ° C. The applied voltage in the display voltage waveform period is 7V, and the applied voltage in the control voltage waveform period is + 7V and −5V.
[0134]
Further, as shown in FIG. 33, when a rectangular wave of a single frequency is inserted as shown in [Table 3] below according to the time width of the control voltage waveform period, the positive voltage and the negative voltage in the unit waveform are shown. A deviation ΔQ from the symmetry of the amount of current (charge amount) that flows depending on the voltage is calculated, and the result is shown in FIG.
[0135]
[Table 3]

[0136]
As is clear from FIG. 34, it is considered that the deviation ΔQ from the symmetry of the charge amount in the repetitive waveform is accumulated over the voltage application time, causing the accumulation of the internal DC voltage. This can be verified from the fact that the result of the internal DC voltage after 24 hours is smaller when ΔQ is smaller. Compared with the case where rectangular waves having the same cycle number are inserted in each control voltage waveform period, the longer the time width of the control voltage waveform period, the smaller the deviation ΔQ from the symmetry of the charge amount. When the control voltage waveform period is short, ΔQ increases as the number of periods of the inserted rectangular wave increases. On the other hand, when the control voltage waveform period is long, ΔQ changes so as to have a minimum point as the number of periods of the inserted rectangular wave increases. In view of these, the following can be understood.
[0137]
That is, as the number of periods of the rectangular wave inserted in the control voltage waveform period is larger, ΔQ is smaller, and accumulation of internal DC voltage can be suppressed. However, a half-cycle time width of the rectangular wave to be inserted is 0.4 msec or more, more preferably 0.9 msec or more. Inserting as many cycles as possible reduces ΔQ and reduces the internal DC voltage. Can also be suppressed.
[0138]
From the examples and results described above, in the present invention, driving to select one of the two states of ON or OFF is performed by a voltage signal that generates an effective internal DC voltage within the selection period, and Accumulation of internal DC voltage is significantly suppressed by inserting an AC waveform that controls (reduces) the magnitude of the internal DC voltage, for example, a rectangular wave, which does not actually contribute to liquid crystal drive within a certain period of time. Can do.
[0139]
At this time, even if the time width for applying the rectangular wave is increased, the electrical neutrality in the repetitive waveform cannot be ensured, but by inserting it within a relatively short range, the inside formed by impurity ions It was possible to find a driving condition that can extremely effectively suppress the generation of a DC voltage, prevent display abnormality, and ensure display reliability over a long period of time.
[0140]
By increasing the time ratio of the internal DC voltage control period to the entire drive voltage waveform as much as possible, accumulation of internal DC voltage can be suppressed. However, if the time ratio of the internal DC voltage control period is 50%, the voltage waveform period for selecting one of the two states and the voltage waveform period for controlling the internal DC voltage are 1: 1. The so-called “bipolar type” waveform having a ratio of 50% / 50% of the waveform shown in FIG. 19 which is a conventional drive voltage waveform without introducing an AC waveform control period not related to display. Can be replaced. In addition, if the time ratio of the internal DC voltage control period is increased, the bit plane time must be shortened, and the display characteristics such as luminance and gradation are deteriorated.
[0141]
In these contradictory results, the internal DC voltage control period is set to one field unit time as a waveform condition for controlling (reducing) the magnitude of the internal DC voltage without deteriorating display characteristics such as luminance and gradation. It is desirable that the content be 5% or more and less than 50%, more preferably 10% or more and 35% or less, so that both conditions can be optimized. Furthermore, an AC waveform represented by a rectangular wave inserted for controlling the internal DC voltage has a 1/2 cycle time width of 0.4 msec or more, more preferably 0.9 msec or more, within the allocated time. Therefore, it is desirable to insert as many cycles as possible. In addition, the rectangular wave to be inserted is not limited to a single frequency, and may be a combination of waveforms of a plurality of frequencies. Is desirable.
[0142]
At this time, the electrical neutrality of the control voltage waveform for controlling the internal DC voltage (the asymmetry parameter R ′ = 0 in the control voltage waveform period) is not necessarily required, and an offset voltage is applied as shown in the embodiment. Such a rectangular wave may be used as long as | R ′ | ≦ 0.5. Further, when comparing the “drive voltage waveform 41” and the “drive voltage waveform 42” in which only the amplitude of the rectangular wave in the control voltage waveform period is changed with respect to the “drive voltage waveform 24”, the larger the amplitude of the rectangular wave is, It can be confirmed that the effect of suppressing the internal DC voltage is great.
[0143]
The polarity of the internal DC voltage control waveform inserted into this drive voltage waveform can always be inserted regardless of the positive / negative voltage signal output during the display waveform period. The logic circuit can be simplified.
[0144]
However, when the insertion period of the internal DC voltage control waveform is shortened as much as possible, a waveform in which the electrical neutrality of the internal DC voltage control period is not taken, such as “drive voltage waveforms 6 and 10”, that is, By generating a 1.5-cycle rectangular wave as an internal voltage control waveform, a remarkable effect can be obtained. The internal voltage control waveform in this case corresponds to the polarity deviation of the display voltage waveform period, that is, when the display voltage waveform period is positive, the internal voltage control waveform period has one positive voltage period and a negative voltage period. When the display voltage waveform period is negative, the voltage period is set at two places, and the positive voltage period is applied at two places and the negative voltage period is applied at one place in the internal voltage control waveform period. However, it is expected that the drive circuit and the output logic circuit of the southern voltage control waveform become complicated in order to identify the bias polarity of the display voltage waveform period.
[0145]
As described above, the present invention effectively reduces the internal DC voltage by inserting the control voltage waveform period within a certain period while the display voltage waveform period effectively generates the internal DC voltage. It is about making it. That is, the phenomenon caused by internal DC voltage such as the polarization of ions in the liquid crystal panel during the display voltage waveform period and the adsorption to the alignment film can be efficiently relaxed and desorbed by the rectangular wave during the control voltage waveform period. Aimed. In particular, the above-mentioned AC waveform is required to suppress adsorption and desorption of ionic species that are slow to relax and that occur over a long period of time as internal DC voltage and that can cause a fatal impact on display characteristics. It is essential to be based on the above-mentioned conditions.
[0146]
From the examples described above, according to the present invention, a liquid crystal display element capable of displaying high definition, high contrast, in-pixel gradation, and having characteristics such as high reliability, low power consumption, thin and light weight is realized. be able to. In addition, the manufacturing process is shortened, the productivity is improved and the cost is reduced, the liquid crystal element can be manufactured at a low cost and has good display characteristics, and the projection display that is an application thereof is provided. Can do.
[0147]
The embodiments of the present invention described above can be further modified based on the technical idea of the present invention. For example, the drive conditions including the drive voltage waveform described above may be changed in various ways within a range in which the object of the present invention can be achieved. In the above-described embodiments, either one of the two states of reflection and non-reflection of incident light or the two states of transmission and non-transmission of incident light is selected. In addition, it is driven so as to select one of two states, substantially on and off, such as either the polarization or non-polarization state of incident light or the rotation or non-rotation state of incident light. It is good as well.
[0148]
【The invention's effect】
As described above, in the method for driving a liquid crystal display element according to the present invention, the first substrate provided with the first electrode and the second substrate provided with the second electrode are the first substrate. In driving a liquid crystal display element that is arranged with a predetermined interval between the electrodes and the side on which the second electrode is provided, with the liquid crystal sealed between these substrates, the first Depending on the voltage signal applied between the second electrode and the second electrode, the incident light is reflected and non-reflected, the incident light is transmitted and non-transmitted, or the incident light is polarized and unpolarized. Alternatively, a driving method for a liquid crystal display element that displays an image by switching between an optical rotation state and a non-optical rotation state of incident light, that is, an ON state or an OFF state, for example, a liquid crystal light modulation display element, a liquid crystal light modulator, etc. In a certain time, Alternatively, within a plurality of frame periods, or within one frame period, a drive voltage waveform consisting of a display signal period and a control signal period not involved in display is used, and a voltage signal applied to the control signal period is The positive and negative voltage signals change alternately, continuously or discontinuously within the allotted time, or positive and negative alternating voltage signals including a voltage signal range of 0 V in the middle. Therefore, the generation of internal DC voltage can be extremely effectively suppressed.
That is, the present invention can provide a driving method of a liquid crystal display element that is simple and prevents deterioration of display image quality due to impurity ions while ensuring a sufficient bit plane time. It is.
[Brief description of the drawings]
FIG. 1 is a perspective view showing a configuration of liquid crystal molecules in a ferroelectric liquid crystal display element to which a liquid crystal display element driving method according to the present invention is applied.
FIG. 2 is a graph showing the relationship between applied voltage and transmittance in the liquid crystal display element.
FIG. 3 is a longitudinal sectional view showing a configuration of the liquid crystal display element.
FIG. 4 is a perspective view showing a reflective operation state of the liquid crystal display element.
FIG. 5 is a perspective view showing a transmissive operation state of the liquid crystal display element.
FIG. 6 is a graph showing the relationship between the bit plane and the light intensity within one frame time in the liquid crystal display element.
FIG. 7 is a time chart showing the relationship between voltage application and transmittance (reflectance) in each bit plane in the liquid crystal display element.
FIG. 8 is a graph showing the relationship between the open circuit monitoring time after a short circuit operation and the open circuit voltage when an asymmetric drive voltage waveform is applied to the liquid crystal display element.
FIG. 9 is a graph showing a relationship between an open circuit voltage and an open circuit monitoring time after a short circuit operation for calculating an internal DC voltage value in the liquid crystal display element.
FIG. 10 is a graph showing a relationship between an open circuit monitoring time and an open circuit voltage after a short circuit operation under various conditions in the liquid crystal display element.
FIG. 11 is a graph showing a Ps reversal current associated with Ps (spontaneous polarization) reversal in the “SSFLC” mode panel.
12 is a graph showing a Ps reversal current associated with Ps (spontaneous polarization) reversal in the “SSFLC” mode panel, in which the observation time is longer than that in FIG.
FIG. 13 is a time chart showing an example (waveform A) of a bit plane waveform in the liquid crystal display element.
FIG. 14 is a time chart showing an example (waveform B) of a bit plane waveform in the liquid crystal display element.
FIG. 15 is a time chart showing an example (waveform C) of a bit plane waveform in the liquid crystal display element.
FIG. 16 is a time chart showing an example (waveform D) of a bit plane waveform in the liquid crystal display element.
FIG. 17 is a time chart showing an example (waveform E) of a bit plane waveform in the liquid crystal display element.
FIG. 18 is a time chart showing an internal DC voltage control waveform in the liquid crystal display element.
FIG. 19 is a “drive waveform 1” in which an internal DC voltage control waveform is inserted into a voltage waveform constituting a 1-bit plane in the liquid crystal display element, and a 1-bit plane waveform and a negative polarity that are displayed by a positive voltage. It is a time chart which shows the 1 bit plane waveform displayed by a voltage.
FIG. 20 is a time chart showing a “driving voltage waveform 2” in which one frame used in the liquid crystal display element is composed of a 108-bit plane and the internal DC voltage control waveform of the internal DC voltage is not inserted.
FIG. 21 shows that one frame used in the liquid crystal display element is composed of 108 bit planes, and an internal DC voltage control waveform of the internal DC voltage of a total of 12 bit planes is inserted for every 36 bit planes. It is a time chart which shows a drive voltage waveform 3 ".
FIG. 22 shows that one frame used in the liquid crystal display element is composed of 108-bit planes, and an internal DC voltage control waveform of the internal DC voltage of a total of 12-bit planes is inserted for every 36-bit planes. It is a time chart which shows the drive voltage waveform 4 ".
FIG. 23 is a waveform in which one frame used in the liquid crystal display element is composed of 108 bit planes, and the number of bit planes of an internal DC voltage control waveform to be inserted is 6 bit planes, and one cycle (in the figure) (A)), 1.5 cycles (in the figure (B)), 2 periods (in the figure (C)), 3 times (in the figure (D)) "drive voltage waveforms 5 to 8" showing a time chart It is.
FIG. 24 is a waveform in which one frame used in the liquid crystal display element is composed of a 108-bit plane, and an internal DC voltage control waveform to be inserted is a 12-bit plane in one cycle ((A) in the figure). , 1.5 periods ((B) in the figure), 2 periods ((C) in the figure), 3 periods ((D) in the figure), and 6 periods ((E) in the figure) “drive voltage waveform 9 to 13 "is a time chart.
FIG. 25 is a waveform in which one frame used in the liquid crystal display element is composed of a 108-bit plane, and an internal DC voltage control waveform to be inserted is a 24-bit plane having one cycle ((A) in the figure). , 1.5 periods ((B) in the figure), 2 periods ((C) in the figure), 2 periods ((D) in the figure), 6 periods ((E) in the figure), 12 periods (in the figure (F) 19 is a time chart showing “driving voltage waveforms 14 to 19”.
FIG. 26 is a waveform in which one frame used in the liquid crystal display element is composed of a 108-bit plane, and an internal DC voltage control waveform to be inserted is a 36-bit plane, and one cycle ((A) in the figure) , 1.5 periods ((B) in the figure), 2 periods ((C) in the figure), 2 periods ((D) in the figure), 2 periods ((E) in the figure), 3 periods (in the figure (F) It is a time chart showing “driving voltage waveforms 20 to 25”.
FIG. 27 shows a waveform in which one frame used in the liquid crystal display element is composed of a 108-bit plane, and an internal DC voltage control waveform to be inserted is a 48-bit plane in one cycle ((A) in the figure). , 1.5 periods ((B) in the figure), 2 periods ((C) in the figure), 2 periods ((D) in the figure), 2 periods ((E) in the figure), 4 periods (in the figure (F) 3) is a time chart showing “driving voltage waveforms 26 to 31”.
FIG. 28 is a waveform in which one frame used in the liquid crystal display element is composed of 108 bit planes, and the internal DC voltage control waveform to be inserted is a rectangular wave of 1.5 periods each, (A)), 12-bit plane (B), 24-bit plane (C), 36-bit plane (D), 48-bit plane (E) 6 is a time chart showing “driving voltage waveforms 32 to 36”.
FIG. 29 is a waveform in which one frame used in the liquid crystal display element is composed of a 108-bit plane, and an internal DC voltage control waveform that is a rectangular wave of two cycles for 36-bit plane is inserted, and the display voltage waveform The negative polarity part of the section is 9-bit plane ((A) in the figure), 18-bit plane ((B) in the figure), 27-bit plane ((C) in the figure), 36-bit plane ((D) in the figure). 4 is a time chart showing “driving voltage waveforms 37 to 40”.
FIG. 30 is a waveform in which one frame used in the liquid crystal display element is composed of a 108-bit plane, and an internal DC voltage control waveform that is a rectangular wave of two cycles for 36-bit planes is inserted, When the voltage value (absolute value) of the control waveform is equal to the voltage value of the display voltage waveform ((A) in the figure), or when the voltage value (absolute value) of the internal DC voltage control waveform is greater than the voltage value of the display voltage waveform ((B) in the figure) shows “drive voltage waveforms 24, 41, 42” when the voltage value (absolute value) of the internal DC voltage control waveform is smaller than the voltage value of the display voltage waveform ((C) in the figure). It is a time chart.
FIG. 31 is a graph showing the amount of internal DC voltage accumulated over time when “driving voltage waveforms 2, 5, 11, 16, 24, 25, 30, 31” are applied to the liquid crystal display element.
32 shows the results for Example 11 ((A) in the figure), Example 18 ((B) in the figure), Example 25 ((C) in the figure), and Example 48 ((D) in the figure). It is a graph which shows the relationship between elapsed time and an electric current.
FIG. 33 shows the amount of current (charge) that flows due to a positive voltage and a negative voltage in a unit waveform when a rectangular wave having a single frequency is inserted according to the time width of the control voltage waveform period in the liquid crystal display element. It is a graph showing a deviation ΔQ from the symmetry of (quantity).
FIG. 34 shows the number of insertion periods and the amount of internal DC voltage stored when the internal DC voltage control waveform is a 6-bit plane, 12-bit plane, 24-bit plane, 36-bit plane, or 48-bit plane in the liquid crystal display device. It is a graph which shows the relationship.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1a Glass substrate, 1b ITO, 1c, 2c Liquid crystal aligning film, 2a Circuit board, 2b Aluminum, 3 Spacer, 4 Ferroelectric liquid crystal, 11 Ferroelectric liquid crystal modulation type display element

Claims (23)

The first electrode is formed on the first surface, and the second electrode is formed on the second surface opposite to the first surface so as to face the first electrode . a second substrate, a method of driving a liquid crystal display device for driving a liquid crystal display element having a liquid crystal layer provided between the first and second surfaces,
A display signal period involved in display included within a certain time, and an amplitude larger than the amplitude of the voltage signal applied between the first electrode and the second electrode in the display signal period; A voltage signal having a drive voltage waveform including a control signal period in which the positive polarity and the negative polarity change according to time and including a control signal period not involved in display is generated between the first electrode and the second electrode. In the meantime, a liquid crystal including a voltage application step for suppressing an internal DC voltage generated inside the liquid crystal display element by applying the control signal period so that a time ratio with respect to the entire drive voltage waveform is 5% or more and less than 50%. A display element driving method. 2. The liquid crystal display element driving device according to claim 1, wherein, when a voltage signal including a rectangular wave is inserted in the control signal period, the voltage signal includes a rectangular wave having a ½ cycle time width of 0.4 msec or more. Way . 3. The liquid crystal display element driving device according to claim 2, wherein when a voltage signal including a rectangular wave is inserted in the control signal period, the voltage signal includes a rectangular wave having a ½ cycle time width of 0.9 msec or more. Way . The voltage signal applied during the control signal period is an asymmetry in which the absolute value of the voltage of the positive polarity voltage signal and the negative polarity voltage signal, or the signal width is different from each other, and the charges of the positive polarity and the negative polarity are unbalanced. method of driving a liquid crystal display device of 請 Motomeko 1 wherein Ru voltage waveform der with. In the drive voltage waveform composed of the display signal period and the control signal period, the area strength asymmetry parameter R obtained by standardizing the voltage integrated intensity averaged over the unit time by the maximum absolute value of the applied voltage in the entire drive voltage waveform. R | | is 0.91 der Ru請 Motomeko 4 driving method of a liquid crystal display device according below the absolute value of. In the control signal period, the absolute value | R | of the area intensity asymmetry parameter R obtained by standardizing the voltage integrated intensity averaged over the unit time with the maximum absolute value of the applied voltage in the entire drive voltage waveform is 0.5 or less. der Ru請 Motomeko 4 driving method of a liquid crystal display device according. The selection of the incident light state is one of two states of on and off, and one of the two states of on and off is maintained for a time sufficiently longer than the response time of the liquid crystal. in the case of after application of the voltage signals, desired transmittance, or, while the reflectance is maintained, the driving method of the liquid crystal element 請 Motomeko 4 wherein apply the next selection signal. In order to determine the polarity and magnitude of the voltage during the control signal period, a detection circuit that detects the bias of the charge generated within a certain time period, within a plurality of frame periods, or within one frame period is used. the method of driving a liquid crystal display element in the DC voltage generating to that請 Motomeko 4, wherein the suppression of generated by the polarization of ions in the liquid crystal. Time ratio of the control signal period, Ru less than 35% der least 10% of the total drive voltage waveform 請 Motomeko 1 driving method for a liquid crystal device according. Selection of the state of the incident light, on a method of driving a liquid crystal display device of any of the liquid crystal display driving method der Ru請 Motomeko 1, wherein the element is the choice of two states and off. In the case where one of the two ON / OFF states is maintained for a time sufficiently longer than the response time of the liquid crystal, the desired transmittance or reflectance is maintained after the voltage signal is applied. during driving method of the liquid crystal element 請 Motomeko 10 wherein you apply the next selection signal. Liquid crystal, ferroelectric liquid crystal or antiferroelectric method of driving a liquid crystal element of the dielectric 請 Motomeko 10 wherein ing from the liquid crystal. The liquid crystal display device, method of driving a liquid crystal element of Ah Ru請 Motomeko 10, wherein the reflection type liquid crystal display device comprising a silicone backplane and a ferroelectric liquid crystal. In the display signal period, as a voltage signal that can select the state of the incident light is one of two states of on and off, the positive voltage, Ru using the drive voltage waveform comprising a combination of a negative voltage and 0V signal 請 Motomeko 10 driving method of a liquid crystal display device according. In the display signal period, the driving voltage waveform in the period for selecting the incident light state is any combination of a positive voltage signal, a negative voltage signal, and a 0 V signal, and the absolute value of these voltages, or , different signal width, the positive polarity and charges of the negative polarity as the applied voltage waveform is Ru waveform der having asymmetry has become unbalanced 請 Motomeko 14 method of driving a liquid crystal display device according. In the control signal period, a signal that is a pulsed or continuous DC voltage having a polarity opposite to the polarity of the drive voltage waveform in the display signal period and is generated by the polarization of ions in the liquid crystal method of driving a liquid crystal display device of 請 Motomeko 15 wherein you apply a suppress reset voltage generation of the DC voltage. Time ratio of the control signal period, Ru less than 35% der least 10% of the total drive voltage waveform 請 Motomeko 16 driving method of a liquid crystal device according. In order to determine the polarity and magnitude of the voltage during the control signal period, a detection circuit that detects the bias of the charge generated within a certain time period, within a plurality of frame periods, or within one frame period is used. the method of driving a liquid crystal display device of the internal DC voltage 請 Motomeko 16 wherein you suppress the occurrence of generated by the polarization of ions in the liquid crystal. In the display signal period, as a voltage signal that can select the state of incident light that is one of two states of on and off, a voltage signal that selects one of the two states of on or off is: a combination of only positive voltage and the other state a voltage signal for selecting is a liquid crystal display element 請 Motomeko 10 wherein Ru using the driving voltage waveform which is a combination of only the negative polarity voltage Driving method. In the display signal period, the driving voltage waveform in the period for selecting the state of the incident light is a combination of either a positive voltage signal or a negative voltage signal, and the absolute value or signal width of those voltages. different method for driving a liquid crystal display device of the waveform der Ru請 Motomeko 19, further comprising an asymmetry charge becomes unbalanced between positive and negative polarities as the applied voltage waveform in the selection period of one state . In the control signal period, a signal that is a pulsed or continuous DC voltage having a polarity opposite to the polarity of the drive voltage waveform in the display signal period and is generated by the polarization of ions in the liquid crystal method of driving a liquid crystal display device of 請 Motomeko 20 wherein you apply a suppress reset voltage generation of the DC voltage. Time ratio of the control signal period, Ru less than 35% der least 10% of the total drive voltage waveform 請 Motomeko 21 driving method of a liquid crystal device according. In order to determine the polarity and magnitude of the voltage during the control signal period, a detection circuit that detects the bias of the charge generated within a certain time period, within a plurality of frame periods, or within one frame period is used. the method of driving a liquid crystal display device of the internal DC voltage 請 Motomeko 21 wherein you suppress the occurrence of generated by the polarization of ions in the liquid crystal.

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