JP4569207B2 - Method for manufacturing field effect transistor - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  2. Description of the Related Art A field effect transistor (FET) including a thin film transistor (TFT) currently used in many electronic devices is, for example, a gate electrode formed on a support, and a support including the gate electrode. And a channel formation region and a source / drain region formed on the gate insulation layer. Here, the channel formation region is composed of a silicon semiconductor layer. For manufacturing field effect transistors having these structures, very expensive semiconductor manufacturing apparatuses are used, and reduction of manufacturing costs is strongly demanded.

  Thus, in recent years, attention has been focused on research and development of FETs using organic semiconductor materials that can be manufactured at low cost.

  By the way, since it is required to be incorporated into many electronic devices including a display device, the FET is required to operate at high speed. For example, there is a need for an FET that can convert a video signal into necessary data at any time and can perform an on / off switching operation at high speed.

  For example, FIG. 9 shows a schematic partial cross-sectional view of a conventional bottom gate / bottom contact type FET (TFT) disclosed in Japanese Patent Application Laid-Open No. 2004-63975. The bottom gate / bottom contact type TFT includes a gate electrode 12 formed on the support 11, a gate insulating layer 13 formed on the support 11 and the gate electrode 12, a source / drain electrode 15, and a source / drain electrode. The gate insulating layer 13 is located between the drain electrode 15 and the source / drain electrode 15 and the semiconductor layer 16 is formed on the source / drain electrode 15. A portion of the semiconductor layer 16 formed on the portion of the gate insulating layer 13 located between the source / drain electrode 15 and the source / drain electrode 15 corresponds to the channel formation region 17. The semiconductor layer 16 is made of an organic semiconductor material.

JP2004-63975

  By the way, in the conventional bottom gate / bottom contact type FET having such a structure, a step portion (indicated by an arrow “A” in FIG. 9) exists in the source / drain electrode 15. Therefore, the crystallinity of the semiconductor layer 16 becomes discontinuous at the stepped portion, which causes deterioration of TFT characteristics such as a decrease in mobility and a decrease in on / off ratio in the channel formation region 17.

  Accordingly, an object of the present invention is to provide a bottom-gate / bottom-contact field effect transistor having excellent characteristics and a method for manufacturing the same.

In order to achieve the above object, the field effect transistor of the present invention provides:
(A) a gate electrode formed on a support;
(B) a gate insulating layer formed on the support and the gate electrode;
(C) source / drain electrodes, and
(D) a semiconductor layer formed on the portion of the gate insulating layer located between the source / drain electrode and the source / drain electrode and on the source / drain electrode;
A field effect transistor comprising:
The source / drain electrodes are embedded in the gate insulating layer.

  In the field effect transistor of the present invention, it is preferable that the level of the top surface of the source / drain electrode and the level of the top surface of the gate insulating layer are substantially the same.

  In the field effect transistor of the present invention or the method for producing the field effect transistor of the present invention described later, the level of the top surface of the source / drain electrode and the level of the top surface of the gate insulating layer are substantially the same. Alternatively, the level of the top surface of the source / drain electrode and the level of the top surface of the gate insulating layer are substantially matched, but the level of the top surface of the source / drain electrode is matched with the level of the top surface of the gate insulating layer. The level of the top surface of the source / drain electrode and the level of the top surface of the gate insulating layer may be slightly inconsistent due to process variations in the process (for example, chemical mechanical polishing process). For this reason, expressions such as “substantially match” and “substantially match” are used.

In order to achieve the above object, a method for producing a field effect transistor of the present invention comprises:
(A) After forming the gate electrode on the support,
(B) forming a gate insulating layer on the support and the gate electrode and forming a source / drain electrode embedded in the gate insulating layer;
(C) forming a semiconductor layer on the portion of the gate insulating layer located between the source / drain electrode and the source / drain electrode and on the source / drain electrode;
It is characterized by that.

In the method for producing a field effect transistor of the present invention, the step (b) includes:
After forming the gate insulating layer on the support and the gate electrode,
Providing a recess in the gate insulating layer;
Forming a source / drain electrode in the recess, thereby obtaining a source / drain electrode embedded in the gate insulating layer;
It can be made into the form which consists of a process. In addition, such a form is called the manufacturing method of the field effect transistor which concerns on the 1st aspect of this invention for convenience.

  In the method of manufacturing the field effect transistor according to the first aspect of the present invention, it is preferable that the level of the top surface of the source / drain electrode and the level of the top surface of the gate insulating layer are substantially matched.

Moreover, in the manufacturing method of the field effect transistor according to the first aspect of the present invention, the step (b) includes:
After forming the gate insulating layer on the support and the gate electrode,
On the gate insulating layer, a resist material layer having an opening formed in a portion where a recess is to be formed is formed, and then
By etching the gate insulating layer using the resist material layer as an etching mask, a recess is provided in the portion of the gate insulating layer where the source / drain electrodes are to be formed.
After the conductive material layer is formed over the entire surface, the resist material layer and the conductive material layer thereon are removed, so that the source / drain electrodes are formed in the recesses provided in the gate insulating layer. That is, it is preferable to form the source / drain electrodes based on a so-called lift-off method. In this case, after removing the resist material layer and the conductive material layer thereabove, the level of the top surface of the source / drain electrode and the level of the top surface of the gate insulating layer are roughly set based on the chemical mechanical polishing method. It is desirable to match.

Alternatively, in the method for producing a field effect transistor of the present invention,
The gate insulating layer is composed of a first gate insulating layer and a second gate insulating layer from below,
The step (b)
After forming the first gate insulating layer on the support and the gate electrode,
A conductive material layer is formed over the first gate insulating layer, a patterned resist material layer is formed over the conductive material layer, and then the conductive material layer is etched using the resist material layer as an etching mask. After forming the drain electrode and then removing the resist material layer,
Forming a second gate insulating layer on the exposed portion of the first gate insulating layer;
It can be made into the form which consists of a process. In addition, such a form is called the manufacturing method of the field effect transistor which concerns on the 2nd aspect of this invention for convenience.

  In the method of manufacturing the field effect transistor according to the second aspect of the present invention, the level of the top surface is on the top surface of the source / drain electrode on the exposed portion of the first gate insulating layer. It is preferable to form a second gate insulating layer that substantially matches the above level. In this case, it is desirable that the level of the top surface of the source / drain electrode and the level of the top surface of the second gate insulating layer are substantially matched based on the chemical mechanical polishing method.

Alternatively, in the method for producing a field effect transistor of the present invention,
The gate insulating layer is composed of a first gate insulating layer and a second gate insulating layer from below,
The step (b)
After forming the first gate insulating layer on the support and the gate electrode,
A conductive material layer is formed over the first gate insulating layer, a patterned resist material layer is formed over the conductive material layer, and then the conductive material layer is etched using the resist material layer as an etching mask. After forming the drain electrode,
A second gate insulating layer is formed on the exposed portion of the first gate insulating layer and on the resist material layer, and then the resist material layer and the second gate insulating layer thereon are formed. Remove parts,
It preferably consists of steps. That is, it is preferable to form the second gate insulating layer based on a so-called lift-off method. In this case, a second gate insulating layer having a top surface level substantially equal to that of the top surface of the source / drain electrode is formed on the exposed portion of the first gate insulating layer. Is preferred. Furthermore, it is desirable that the level of the top surface of the source / drain electrode and the level of the top surface of the second gate insulating layer are substantially matched based on a chemical mechanical polishing method.

  In the field-effect transistor of the present invention or a method for manufacturing the same (hereinafter, these may be collectively referred to simply as the present invention), the semiconductor layer is preferably made of an organic semiconductor material.

Specifically, as a semiconductor material constituting the semiconductor layer, 2,3,6,7-dibenzoanthracene (also referred to as pentacene), C ₉ S ₉ (benzo [1,2-c; 3,4-c ′; 5,6-c ″] tris [1,2] dithiol-1,4,7-trithione), C ₂₄ H ₁₄ S ₆ (alpha-sexithiophene), phthalocyanine represented by copper phthalocyanine, fullerene (C ₆₀ ), tetrathiotetracene _{(C 18 H 8 S 4)} , tetraselenotetracene _{(C 18 H 8 Se 4)} , tetra-tellurium tetracene _{(C 18 H 8 Te 4)} , poly (3-hexylthiophene), poly (3, 4-Ethylenedioxythiophene) / polystyrene sulfonic acid [PEDOT / PSS] can be mentioned, wherein structural formula (1) of poly (3,4-ethylenedioxythiophene), police The structural formula (2) of tylenesulfonic acid is shown in FIG.

Alternatively, for example, a heterocyclic conjugated conductive polymer and a heteroatom conjugated conductive polymer exemplified below can be used as the semiconductor layer for forming the channel formation region. In the structural formula, “R” and “R ′” mean an alkyl group (C _n H _{2n + 1} ).

[Heterocyclic conjugated conductive polymer]
Polypyrrole [see structural formula (3) in FIG. 6]
Polyfuran [see structural formula (4) in FIG. 6]
Polythiophene [see structural formula (5) in FIG. 6]
Polyselenophene [see structural formula (6) in FIG. 6]
Polytellophene [see structural formula (7) in FIG. 6]
Poly (3-alkylthiophene) [see structural formula (8) in FIG. 6]
Poly (3-thiophene-β-ethanesulfonic acid) [see structural formula (9) in FIG. 6]
Poly (N-alkylpyrrole) [see structural formula (10) in FIG. 7]
Poly (3-alkylpyrrole) [see structural formula (11) in FIG. 7]
Poly (3,4-dialkylpyrrole) [see structural formula (12) in FIG. 7]
Poly (2,2′-thienylpyrrole) [see structural formula (13) in FIG. 7]

[Containing heteroatom-containing conductive polymer]
Polyaniline [see structural formula (14) in FIG. 7]
Poly (dibenzothiophene sulfide) [see structural formula (15) in FIG. 7]

Alternatively, the organic semiconductor molecule constituting the semiconductor layer for forming the channel formation region is an organic semiconductor molecule having a conjugated bond, and a thiol group (SH), an amino group (—NH ₂ ) at both ends of the molecule, It is desirable to have an isocyano group (—NC), a thioacetyl group (—SCOCH ₃ ), or a carboxy group (—COOH). More specifically, examples of organic semiconductor molecules include the following materials.

4,4′-biphenyldithiol [see the structural formula (16) in FIG. 8]
4,4′-Diisocyanobiphenyl [see the structural formula (17) in FIG. 8]
4,4′-Diisocyano-p-terphenyl [see structural formula (18) in FIG. 8]
2,5-bis (5′- thioacetyl- 2′-thiophenyl) thiophene [see the structural formula (19) in FIG. 8]

  Although the semiconductor layer formation method depends on the material constituting the semiconductor layer, physical vapor deposition method (PVD method) exemplified by vacuum deposition method and sputtering method; various chemical vapor deposition methods (CVD method) ); Spin coating method; various printing methods such as screen printing method, inkjet printing method, offset printing method, gravure printing method; air doctor coater method, blade coater method, rod coater method, knife coater method, squeeze coater method, reverse roll coater , Transfer roll coater method, gravure coater method, kiss coater method, cast coater method, spray coater method, slit orifice coater method, calender coater method, dipping method, and any of the spray methods. it can.

  In addition, as materials constituting the gate electrode and the source / drain electrode, platinum (Pt), gold (Au), palladium (Pd), chromium (Cr), nickel (Ni), molybdenum (Mo), niobium (Nb), Neodymium (Nd), Rubidium (Rb), Rhodium (Rh), Aluminum (Al), Silver (Ag), Tantalum (Ta), Tungsten (W), Titanium (Ti), Copper (Cu), Indium (In), Metals such as tin (Sn) or alloys containing these metal elements, conductive particles made of these metals, conductive particles of alloys containing these metals, polysilicon, amorphous silicon, tin oxide, indium oxide Indium tin oxide (ITO) can be used, and a layered structure of layers containing these elements can also be used. Furthermore, an organic material such as poly (3,4-ethylenedioxythiophene) / polystyrene sulfonic acid [PEDOT / PSS] can also be used as a material constituting the gate electrode and the source / drain electrode.

  As a method for forming the gate electrode and the source / drain electrode, although depending on the material constituting the gate electrode and the source / drain electrode, PVD method exemplified by vacuum deposition method and sputtering method; various CVD methods including MOCVD method; Spin coating method; various printing methods described above using various conductive pastes and various conductive polymer solutions; various coating methods described above; lift-off method; shadow mask method; electrolytic plating method, electroless plating method, or combinations thereof Any one of a plating method and a spray method, or further, a combination with a patterning technique can be given as necessary. Examples of the patterning technique include a dry etching technique such as an RIE technique, a wet etching technique, and an ashing technique, depending on the material constituting the gate electrode and the source / drain electrode. In addition, as the PVD method, (a) various vacuum deposition methods such as electron beam heating method, resistance heating method, flash deposition, (b) plasma deposition method, (c) bipolar sputtering method, direct current sputtering method, direct current magnetron sputtering method Various sputtering methods such as high-frequency sputtering method, magnetron sputtering method, ion beam sputtering method, bias sputtering method, (d) DC (direct current) method, RF method, multi-cathode method, activation reaction method, electric field evaporation method, high-frequency method Various ion plating methods such as an ion plating method and a reactive ion plating method can be given.

As a material constituting the gate insulating layer, not only a silicon oxide material, silicon nitride (SiN _Y ), Al ₂ O ₃ , HfO ₂ , a metal oxide high dielectric insulating film, but also an inorganic insulating material can be used. Illustrated with methyl methacrylate (PMMA), polyvinyl phenol (PVP), polyvinyl alcohol (PVA), polyethylene terephthalate (PET), polyoxymethylene (POM), polyvinyl chloride, polyvinylidene fluoride, polysulfone, polycarbonate (PC), polyimide An organic insulating material can be used, or a combination of these can also be used. As silicon oxide materials, silicon dioxide (SiO _x ), BPSG, PSG, BSG, AsSG, PbSG, silicon oxynitride (SiON), SOG (spin on glass), low dielectric constant SiO ₂ materials (for example, polyaryl) And ether, cycloperfluorocarbon polymer and benzocyclobutene, cyclic fluororesin, polytetrafluoroethylene, fluorinated aryl ether, fluorinated polyimide, amorphous carbon, and organic SOG). As a method for forming the gate insulating layer, PVD method exemplified by vacuum deposition method and sputtering method; various CVD methods; spin coating method; various printing methods as described above; various coating methods as described above; immersion method; Any of the laws can be mentioned.

  Examples of the support include various glass substrates, various glass substrates having an insulating layer formed on the surface, a quartz substrate, a quartz substrate having an insulating layer formed on the surface, and a silicon substrate having an insulating layer formed on the surface. it can. Furthermore, as a support, polyethersulfone (PES), polyimide, polycarbonate (PC), polyethylene terephthalate (PET), polymethyl methacrylate (polymethyl methacrylate, PMMA), polyvinyl alcohol (PVA), polyvinylphenol (PVP) And a plastic film, a plastic sheet, and a plastic substrate made of a polymer material exemplified in the above. If a support made of such a flexible polymer material is used, for example, A field effect transistor can be incorporated or integrated into a display device or electronic device having a curved surface. Other examples of the support include a conductive substrate (a substrate made of a metal such as gold or highly oriented graphite). In the present invention, depending on the configuration and structure of the semiconductor device, the semiconductor device is provided on the support member, but this support member can also be made of the above-described materials. An electronic device or a semiconductor device may be sealed with resin.

  When the field effect transistor of the present invention is applied to and used in a display device or various electronic devices, it may be a monolithic integrated circuit in which a number of field effect transistors are integrated on a support, or each field effect transistor may be cut. It may be individualized and used as a discrete part. Further, the field effect transistor may be sealed with resin.

  In the present invention, since the source / drain electrodes are embedded in the gate insulating layer, the crystallinity of the semiconductor layer is not discontinuous, the mobility in the channel formation region is improved, and the on / off ratio is increased. Can be improved.

  Hereinafter, the present invention will be described based on examples with reference to the drawings.

  Example 1 relates to the field effect transistor of the present invention and the method of manufacturing the same, and more particularly to the method of manufacturing the field effect transistor according to the first aspect of the present invention.

As shown in a schematic partial cross-sectional view of FIG. 2C, the field effect transistor of Example 1 is a bottom-gate / bottom-contact TFT,
(A) a gate electrode 12 formed on the support 11;
(B) a gate insulating layer 13 formed on the support 11 and the gate electrode 12;
(C) source / drain electrode 15, and
(D) a semiconductor layer 16 formed on the portion of the gate insulating layer 13 located between the source / drain electrode 15 and the source / drain electrode 15 and on the source / drain electrode 15;
Consists of. A portion of the semiconductor layer 16 located between the source / drain electrode 15 and the source / drain electrode 15 corresponds to the channel formation region 17.

  The source / drain electrode 15 is embedded in the gate insulating layer 13. More specifically, the level of the top surface 15a of the source / drain electrode 15 and the level of the top surface 13a of the gate insulating layer 13 are substantially the same.

In Example 1, the support 11 is made of a glass substrate having a SiO ₂ layer (not shown) formed on the surface. The gate electrode 12 and the source / drain electrode 15 are made of gold (Au), the gate insulating layer 13 is made of SiO ₂ , and the semiconductor layer 16 is made of an organic semiconductor material, more specifically, pentacene.

  Hereinafter, with reference to FIGS. 1A to 1D and FIGS. 2A to 2C which are schematic partial sectional views of the support 11 and the like, the field effect transistor of Example 1 will be described below. The manufacturing method will be described.

[Step-100]
First, the gate electrode 12 is formed on the support 11. Specifically, a resist layer (not shown) from which a portion where the gate electrode 12 is to be formed is formed on the support 11 based on a lithography technique. Thereafter, a titanium (Ti) layer (not shown) as an adhesion layer and a gold (Au) layer as a gate electrode 12 are sequentially formed on the entire surface by vacuum deposition, and then the resist layer is removed. To do. Thus, the gate electrode 12 can be obtained based on a so-called lift-off method.

  Next, the gate insulating layer 13 is formed on the support 11 and the gate electrode 12, and the source / drain electrodes 15 embedded in the gate insulating layer 13 are formed. Specifically, the following steps are executed.

[Step-110]
That is, first, the gate insulating layer 13 is formed on the support 11 including the gate electrode 12. Specifically, the gate insulating layer 13 made of SiO ₂ is formed on the gate electrode 12 and the support 11 based on the sputtering method. When forming the gate insulating layer 13, by covering a part of the gate electrode 12 with a hard mask, an extraction portion (not shown) of the gate electrode 12 can be formed without a photolithography process. Thus, the structure shown in FIG. 1A can be obtained.

[Step-120]
Next, based on the photolithography technique, a resist material layer 18 in which an opening 19 is formed in a portion where a recess is to be formed is formed on the gate insulating layer 13 (see FIG. 1B).

[Step-130]
Thereafter, the gate insulating layer 13 is etched based on the RIE method using the resist material layer 18 as an etching mask, thereby providing a recess 13B in the portion of the gate insulating layer 13 where the source / drain electrode 15 is to be formed (FIG. C)). Etching of the gate insulating layer 13 depends on the material constituting the gate insulating layer 13, but can also be performed based on a wet etching method or an ashing method using oxygen gas.

[Step-140]
Next, a titanium (Ti) layer (not shown) as an adhesion layer and a gold (Au) layer as a conductive material layer 14 are sequentially formed on the entire surface by vacuum evaporation (see FIG. D)), and thereafter, the resist material layer 18 and the adhesion layer and the conductive material layer 14 thereon are removed, thereby forming the source / drain electrodes 15 in the recesses 13B provided in the gate insulating layer 13. Thus, the source / drain electrode 15 embedded in the gate insulating layer 13 is obtained (see FIG. 2A).

[Step-150]
Next, it is preferable that the level of the top surface 15a of the source / drain electrode 15 and the level of the top surface 13a of the gate insulating layer 13 are substantially matched based on a chemical mechanical polishing method (CMP method) (FIG. 2). (See (B)). 2A shows a state in which the source / drain electrode 15 protrudes from the gate insulating layer 13, but the top surface 15a of the source / drain electrode 15 is more than the top surface 13a of the gate insulating layer 13. FIG. May be indented.

[Step-160]
Thereafter, a semiconductor layer 16 is formed on the portion of the gate insulating layer 13 located between the source / drain electrode 15 and the source / drain electrode 15 and on the source / drain electrode 15. Specifically, the semiconductor layer 16 made of pentacene is formed by a vacuum deposition method. When the semiconductor layer 16 is formed, the semiconductor layer 16 can be formed without a photolithography process by covering a part of the gate insulating layer 13 with a hard mask. In this way, the field effect transistor shown in FIG. 2C can be obtained.

Example 2 is a modification of Example 1 and relates to a method of manufacturing a field effect transistor according to the second aspect of the present invention. The field effect transistor obtained in Example 2 is
(1) The gate insulating layer has a laminated structure of a first gate insulating layer 23A and a second gate insulating layer 23B from the bottom.
(2) The periphery of the source / drain electrode 15 is filled with the second gate insulating layer 23B.
This is different from the field effect transistor described in the first embodiment, and the other points are the same as the field effect transistor described in the first embodiment, and thus detailed description of the field effect transistor is omitted. To do.

  Hereinafter, with reference to FIGS. 3A to 3C and FIGS. 4A to 4B which are schematic partial sectional views of the support 11 and the like, the field effect transistor of Example 2 will be described below. The manufacturing method will be described.

[Step-200]
First, the same process as [Process-100] of Example 1 is performed to form the gate electrode 12 on the support 11.

  Next, the gate insulating layer 13 is formed on the support 11 and the gate electrode 12, and the source / drain electrodes 15 embedded in the gate insulating layer 13 are formed. Specifically, the following steps are executed.

[Step-210]
That is, first, the same step as [Step-110] in Example 1 is performed to form the first gate insulating layer 23A on the support 11 including the gate electrode 12. Specifically, a first gate insulating layer 23A made of SiO ₂ is formed on the gate electrode 12 and the support 11 based on a sputtering method. Thus, the structure shown in FIG. 3A can be obtained.

[Step-220]
Next, the conductive material layer 24 is formed over the first gate insulating layer 23A. Specifically, a titanium (Ti) layer (not shown) as the adhesion layer and a gold (Au) layer as the conductive material layer 24 are sequentially formed on the entire surface by vacuum deposition, Based on the photolithography technique, a patterned resist material layer 28 is formed on the conductive material layer 24 (see FIG. 3B).

[Step-230]
Thereafter, the conductive material layer 24 and the adhesion layer are etched using the resist material layer 28 as an etching mask to form the source / drain electrodes 15, and then the ashing is performed to remove the resist material layer 28 (FIG. 3 (C)).

[Step-240]
Next, on the exposed portion of the first gate insulating layer 23A, a second gate insulating layer 23B in which the level of the top surface 23b substantially matches the level of the top surface 15a of the source / drain electrode 15 is formed. Form. Specifically, the second gate insulating layer 23B is formed on the exposed portion of the first gate insulating layer 23A. More specifically, the second gate insulating layer 23B made of SiO ₂ is formed on the entire surface based on the sputtering method. After that, it is preferable that the level of the top surface 15a of the source / drain electrode 15 and the level of the top surface 23b of the second gate insulating layer 23B are substantially matched based on the CMP method. Thus, the structure shown in FIG. 4A can be obtained.

[Step-250]
Thereafter, the same process as [Process-160] of Example 1 is performed, and the source / drain electrode and the source / drain electrode on the portion of the gate insulating layer 13 located between the source / drain electrode 15 and the source / drain electrode 15 are executed. A semiconductor layer 16 is formed on 15. Thus, the field effect transistor shown in FIG. 4B can be obtained.

Example 3 is also a modification of Example 1, and relates to a method of manufacturing a field effect transistor according to the third aspect of the present invention. The field effect transistor obtained in Example 3 is similar to the field effect transistor in Example 2,
(1) The gate insulating layer has a laminated structure of a first gate insulating layer 23A and a second gate insulating layer 23B from the bottom.
(2) The periphery of the source / drain electrode 15 is filled with the second gate insulating layer 23B.
This is different from the field-effect transistor described in the first embodiment, and the other points are the same as the field-effect transistor described in the first embodiment. To do.

  Hereinafter, (A) to (B) in FIG. 3, (A) to (C) in FIG. 5, and (A) to (B) in FIG. 4, which are schematic partial sectional views of the support 11 and the like. A method for manufacturing the field-effect transistor of Example 3 will be described with reference to FIG.

[Step-300]
First, the same process as [Process-100] of Example 1 is performed to form the gate electrode 12 on the support 11.

  Next, the gate insulating layer 13 is formed on the support 11 and the gate electrode 12, and the source / drain electrodes 15 embedded in the gate insulating layer 13 are formed. Specifically, the following steps are executed.

[Step-310]
That is, first, the same step as [Step-110] in Example 1 is performed to form the first gate insulating layer 23A on the support 11 including the gate electrode 12. Specifically, a first gate insulating layer 23A made of SiO ₂ is formed on the gate electrode 12 and the support 11 based on a sputtering method. Thus, the structure shown in FIG. 3A can be obtained.

[Step-320]
Next, the conductive material layer 24 is formed over the first gate insulating layer 23A. Specifically, a titanium (Ti) layer (not shown) as an adhesion layer and a gold (Au) layer as a conductive material layer 24 are sequentially formed on the entire surface by vacuum deposition, Based on the photolithography technique, a patterned resist material layer 28 is formed on the conductive material layer 24 (see FIG. 3B).

[Step-330]
Thereafter, the source / drain electrode 15 is formed by etching the conductive material layer 24 and the adhesion layer using the resist material layer 28 as an etching mask. Thus, the structure shown in FIG. 5A can be obtained. In the third embodiment, unlike the second embodiment, the resist material layer 28 is not removed at this point.

[Step-340]
Next, a second gate insulating layer 23B is formed on the exposed portion of the first gate insulating layer 23A and on the resist material layer 28. Next, the resist material layer 28 and the resist material layer 28 are formed thereon. The portion of the second gate insulating layer 23B is removed. Specifically, a second gate insulating layer 23B made of SiO ₂ is formed on the entire surface by a sputtering method (see FIG. 5B). Thereafter, the resist material layer 28 and the portion of the second gate insulating layer 23B thereon are removed (see FIG. 5C).

[Step-350]
Next, it is preferable that the level of the top surface 15a of the source / drain electrode 15 and the level of the top surface 23b of the second gate insulating layer 23B are substantially matched based on the CMP method. Thus, as shown in FIG. 4A, the level of the top surface 23b is substantially the same as the level of the top surface 15a of the source / drain electrode 15 on the exposed portion of the first gate insulating layer 23A. The matching second gate insulating layer 23B can be formed.

[Step-360]
Thereafter, the same process as [Process-160] of Example 1 is performed, and the source / drain electrode and the source / drain electrode on the portion of the gate insulating layer 13 located between the source / drain electrode 15 and the source / drain electrode 15 are executed. A semiconductor layer 16 is formed on 15. Thus, the field effect transistor shown in FIG. 4B can be obtained.

  As mentioned above, although this invention was demonstrated based on the preferable Example, this invention is not limited to these Examples. The structure and configuration of the semiconductor device, the manufacturing conditions, and the materials used are examples, and can be changed as appropriate. When the field effect transistor (TFT) obtained by the present invention is applied to and used in a display device or various electronic devices, a monolithic integrated circuit in which a large number of TFTs are integrated on a support or a support member may be used. The TFT may be cut and individualized and used as a discrete component.

1A, 1 </ b> B, 1 </ b> C, and 1 </ b> D are schematic partial cross-sectional views of a support and the like for describing the method for manufacturing the field-effect transistor of Example 1. FIG. 2A, 2B, and 2C are schematic partial views of a support and the like for explaining the method of manufacturing the field effect transistor of Example 1 following FIG. 1D. It is sectional drawing. 3A, 3 </ b> B, and 3 </ b> C are schematic partial cross-sectional views of a support and the like for explaining the method for manufacturing the field-effect transistor of Example 2. FIG. 4A and 4B are schematic partial cross-sectional views of a support and the like for explaining the method for manufacturing the field-effect transistor of Example 2 following FIG. 3C. . 5A, 5 </ b> B, and 5 </ b> C are schematic partial cross-sectional views of a support and the like for describing the method for manufacturing the field-effect transistor of Example 3. FIG. FIG. 6 illustrates the structural formula of an organic semiconductor material suitable for use in the present invention. FIG. 7 illustrates the structural formula of an organic semiconductor material suitable for use in the present invention. FIG. 8 illustrates the structural formula of an organic semiconductor material suitable for use in the present invention. FIG. 9 is a schematic partial sectional view of a conventional bottom gate / bottom contact field effect transistor.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 ... Support body, 12 ... Gate electrode, 13 ... Gate insulating layer, 13a, 23b ... Top surface of gate insulating layer, 13B ... Recessed part, 14, 24 ... Conductive material layer 15 ... source / drain electrodes, 15a ... top surfaces of the source / drain electrodes, 16 ... semiconductor layer, 17 ... channel formation region, 18, 28 ... resist material layer, 19 ... Opening of resist material layer, 23A: first gate insulating layer, 23B: second gate insulating layer

Claims (8)

(A) After forming the gate electrode on the support,
(B) forming a gate insulating layer on the support and the gate electrode and forming a source / drain electrode embedded in the gate insulating layer;
(C) forming a semiconductor layer on the portion of the gate insulating layer located between the source / drain electrode and the source / drain electrode and on the source / drain electrode;
With each process,
The step (b)
After forming the gate insulating layer on the support and the gate electrode,
Providing a recess in the gate insulating layer;
A method of manufacturing a field effect transistor comprising a step of forming a source / drain electrode in a recess, thereby obtaining a source / drain electrode embedded in a gate insulating layer . 2. The method of manufacturing a field effect transistor according to claim 1 , wherein the level of the top surface of the source / drain electrode and the level of the top surface of the gate insulating layer are substantially matched. The step (b)
After forming the gate insulating layer on the support and the gate electrode,
On the gate insulating layer, a resist material layer having an opening formed in a portion where a recess is to be formed is formed, and then
By etching the gate insulating layer using the resist material layer as an etching mask, a recess is provided in the portion of the gate insulating layer where the source / drain electrodes are to be formed.
2. The electric field according to claim 1 , wherein after forming the conductive material layer on the entire surface, the resist material layer and the conductive material layer thereon are removed to form source / drain electrodes in the recesses provided in the gate insulating layer. Method for producing effect transistor. After removing the resist material layer and the conductive material layer thereon, chemical mechanical Based on polishing, claim to the level of the top surface level as the gate insulating layer of the top surface of the source / drain electrodes substantially coincide 3 A method for producing the field effect transistor according to 1. (A) After forming the gate electrode on the support,
(B) forming a gate insulating layer on the support and the gate electrode and forming a source / drain electrode embedded in the gate insulating layer;
(C) forming a semiconductor layer on the gate insulating layer located between the source / drain electrode and the source / drain electrode and on the source / drain electrode;
With each process,
The gate insulating layer is composed of a first gate insulating layer and a second gate insulating layer from below,
The step (b)
After forming the first gate insulating layer on the support and the gate electrode,
A conductive material layer is formed over the first gate insulating layer, a patterned resist material layer is formed over the conductive material layer, and then the conductive material layer is etched using the resist material layer as an etching mask. After forming the drain electrode and then removing the resist material layer,
Forming a second gate insulating layer on the exposed portion of the first gate insulating layer;
A method of manufacturing a field effect transistor comprising steps. 6. The second gate insulating layer according to claim 5 , wherein a second gate insulating layer having a top surface level substantially matching the level of the top surface of the source / drain electrode is formed on the exposed portion of the first gate insulating layer. A method of manufacturing a field effect transistor. 7. The method of manufacturing a field effect transistor according to claim 6 , wherein the level of the top surface of the source / drain electrode and the level of the top surface of the second gate insulating layer are substantially matched based on a chemical mechanical polishing method. The method of manufacturing a field effect transistor according to claim 1 , wherein the semiconductor layer is made of an organic semiconductor material.

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