JP4575013B2 - Method for manufacturing optoelectronic integrated device - Google Patents

Description

The present invention relates to a manufacturing method of the opto-electronic integrated equipment, and more particularly, to a silicon substrate on which an integrated circuit is formed, an optoelectronic integrated incorporating the compound semiconductor light emitting device electrically connected to the integrated circuit together and to provide a method for manufacturing equipment.

  The technology for forming an integrated circuit on a silicon substrate has been developed while greatly increasing the degree of integration, and has supported today's IT society. However, silicon is not a suitable semiconductor as a light-emitting element in the visible light region, and compound semiconductors such as GaN are widely used for visible light-emitting elements. Many devices have been proposed so far in which a compound semiconductor used as a light-emitting portion is integrated and integrated into a silicon substrate on which the integrated circuit is formed.

  For example, a method is disclosed in which a laser oscillation portion made of an epitaxial film is formed on a compound semiconductor substrate, and the remaining portion after the compound semiconductor substrate is partially removed is attached to a silicon substrate (Patent Document 1). . In this method, a method using a cleavage plane for forming end faces parallel to each other, which is indispensable for forming a resonance part of laser oscillation, and a method not using a cleavage plane are shown.

Also disclosed is a method in which a V-shaped trench is formed in a silicon substrate, and a bar-shaped compound semiconductor having the elongated V-shaped cross section is fitted and fixed along the V-shaped trench. Since this bar-shaped compound semiconductor oscillates, opposite parallel end faces are mirror-finished by etching (Patent Document 2).
Moreover, the structure which provides a recessed part in a silicon substrate, and fits and fixes the compound semiconductor containing light emitting diode LED in this recessed part is disclosed (patent document 3).

According to the above light emitting element, the silicon substrate on which the integrated circuit is formed and the compound semiconductor including the active layer are integrated, and for example, a signal composed of an electrical signal of the integrated circuit can be output as an optical signal. . In the following description, a device in which a silicon substrate on which an integrated circuit is formed and a compound semiconductor including an active layer is integrated is referred to as an optoelectronic integrated device.
JP-A-6-90061 JP-A-6-334267 Japanese Patent No. 2610075

  However, the above-described optoelectronic integrated device has a complicated processing process, and it is difficult to efficiently provide a large amount of highly reliable products. In particular, in the case of a laser oscillation element, the element having the above structure is not suitable for mass production continuously.

The present invention aims at providing a silicon substrate on which an integrated circuit is formed, a manufacturing method of the opto-electronic integrated equipment that integrates the compound semiconductor layers including an active layer.

The method for manufacturing an optoelectronic integrated device according to the present invention includes a step of forming a growth support layer on a silicon substrate, a patterning of the growth support layer, and a surrounding window portion that is a groove surrounding the island-shaped growth support layer, and an island shape Forming a linear window extending outwardly from the growth support layer. And a step of filling the window and epitaxially growing the compound semiconductor layer on the growth support layer in the lateral direction. After the compound semiconductor is epitaxially grown in the lateral direction to form a laminated epitaxial growth film including an active layer, the temperature is lowered, and cleavage fracture occurs at the boundary between the surrounding window portion and the linear window portion in plan view.

  By this method, an epitaxial film of an island-shaped compound semiconductor having a passing diameter of a predetermined value or more can be laminated at the center. As a result, in the island portion, an integrated circuit can be formed on the silicon substrate and a light emitting portion can be formed on the epitaxial laminated film thereon. Furthermore, since a laminated structure of thin strip-like epitaxial films extending outward from the island-like portion can be formed, stress concentration is generated at the boundary between the island-like portion and the thin strip-like portion, and the parallel opposing surfaces are formed. A resonant portion can be formed by creating two cleavage planes.

  Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a plan view showing an optoelectronic integrated device 10 according to an embodiment of the present invention. In FIG. 1, the optoelectronic integrated device has a hexagonal shape in plan view, but is not limited to the hexagonal shape, as long as it can be surrounded by a combination of continuous curves or straight lines. Anything In addition, the island shape is preferable if it has a passing diameter of a predetermined value or more. Strictly speaking, the above shape should be an octagon, but the opposite side 21 of the eight sides of the octagon is smaller than the other sides as will be described later, so the optoelectronic integrated device shown in FIG. The planar shape of 10 is called a hexagonal shape.

  In the optoelectronic integrated device 10, a compound semiconductor AlGaAs multilayer structure is formed on a silicon substrate so as to include an active layer that oscillates laser. Opposing end faces 21 parallel to each other for laser oscillation are formed by cleavage planes. The length of this end face is shorter than the other sides when viewed in a plan view.

  What is characteristic in the embodiment of the present invention is that the ELO layer surrounds the outer periphery of the window 2a of the growth support layer (not shown). This feature is derived from the method of manufacturing the optoelectronic integrated device in the present embodiment, and then the reason why the ELO layer is positioned so as to cover the side edge of the growth support layer will be described.

2 is a cross-sectional view taken along line II-II in FIG. In FIG. 2, a GaAs buffer layer 12 is provided on a silicon substrate 1, and a growth support layer 2 made of SiO ₂ is disposed thereon so as to have a window portion 2a. An ELO layer 3 made of n-type AlGaAs is located so as to surround the side edge of the growth support layer 2 and cover the growth support layer 2. On the ELO layer 3, an n-type AlGaAs cladding layer 13, an active layer 4 and a p-type AlGaAs cladding layer 5 are epitaxially grown. The end face 21 of this optoelectronic integrated device is constituted by a cleavage plane.

  As shown in FIG. 3, the active layer 4 has a double heterostructure formed by an n-type AlGaAs layer 4a, an i-type AlGaAs layer 4b thereon, and a p-type AlGaAs layer 4c thereon. However, the active layer is not limited to a double hetero structure. The active layer is excited by light partially reflected at the end face 21 to cause laser oscillation.

Next, a method for manufacturing the optoelectronic integrated device will be described. FIG. 4 is a perspective view showing a state in which a window portion 2a is provided on the growth support layer 2 of SiO ₂ deposited on the silicon substrate 1 in the production of the optoelectronic integrated device. The window portion 2a is formed from a portion surrounding the hexagonal island-shaped growth support layer 2 as a trench having a predetermined width and a portion facing outward from the island-shaped growth support layer in a straight line. ing. The silicon substrate is a substrate having a (100) plane as a main surface.

First, a GaAs buffer layer 12 is grown on the silicon substrate 1 to a thickness of 0.1 to 1 μm by MBE (Molecular Beam Epitaxy). On the GaAs buffer layer 12, a SiO ₂ film 2 having a thickness of 0.1 to 0.5 μm is formed by sputtering. Using the photolithography method, the SiO ₂ film 2 was opened in a trench shape composed of a linear portion parallel to the [011] direction and a portion surrounding the island-shaped growth support layer 2 as described above. The window part 2a is formed.

  As described above, in this embodiment, the island-like growth support layer has a hexagonal shape. The portion surrounding the hexagonal growth support layer is formed from a combination of straight trenches. Among the combined linear trenches, linear trenches parallel to the [011] direction are included.

  The trench width in the window portion surrounding the island-like growth support layer and the straight window portion away from the window portion is 5 μm, and the interval between the hexagonal central parallel sides is the above-described window portion (trench) located outside. And 300 μm. The length of the island-shaped growth support layer in the [011] direction was 200 μm. A plurality of window portions having such shapes can be formed at arbitrary positions on a single substrate.

Growth was performed under the following conditions using the LPE method using the silicon substrate in which the window was formed in this way. A growth support layer of an SiO ₂ layer in which a buffer layer and a window portion are patterned in advance is formed on the silicon substrate. The growth apparatus is of the well-known slide boat method. Referring to FIG. 5, the silicon substrate is accommodated in a recess 51a provided in a slide base 51 so that the boat 52 can be smoothly slid. The slide table 51 and the boat 52 on which these silicon substrates are placed are arranged in a furnace capable of temperature control with sufficient accuracy. First, the following five types of growth solutions are prepared in the solution reservoir of the slide boat 52.

Solution S1: GaAs and Si dissolved in Ga as an n-type impurity Solution S2: GaAs and Al dissolved in Ga and Te as an n-type impurity Solution S3: GaAs and Al dissolved in Ga Solution S4: GaAs and Al dissolved in Ga and Zn as p-type impurities Solution S5: GaAs and Zn dissolved as p-type impurities in Ga Raised the furnace temperature to 500 ° C Contact with solution S1. When the temperature is gradually lowered after the contact, a GaAs epitaxial film (ELO layer) grows in the periphery of the window part and in the window part by lateral growth from the window part. No growth occurs in the region protected by SiO ₂ .

  After cooling to 490 ° C. at 0.1 ° C./min, solution S 1 is separated from the silicon substrate and then brought into contact with solution S 2. In this state, it is cooled to 485 ° C. at 1 ° C./min. The solution S2 is separated and the boat is moved at the same speed to contact the solution S3 and then to separate it.

  Thereafter, the solution S4 and the silicon substrate are brought into contact with each other, and growth is performed at 1 ° C./min up to 480 ° C. Next, after separating the solution S4, the solution S5 is brought into contact with the silicon substrate. In this state, the solution was cooled to 487 ° C., and the solution S5 was separated from the silicon substrate.

  Then, it cooled to room temperature in the state as it was, and took out from the growth furnace.

  When the above-mentioned epitaxial laminated film taken out from the furnace cooled to room temperature was observed with a microscope, it was parallel to the (0-1-1) plane in the vicinity of the boundary between the straight window and the window surrounding the island-like growth support layer. A natural cleavage plane was formed.

  When the extracted epitaxial film was etched with a KOH etching solution, many dislocations were observed in the window and above, but almost no dislocations were observed in the other portions.

  The epitaxial film grown in the above process has an edge-emitting laser structure with the next epitaxial film as an active layer. The thickness and Al composition of each epitaxial layer are as follows. The code | symbol of each epitaxial film respond | corresponds to the code | symbol shown in FIG.

Epitaxial film 3: Al composition 0, thickness 3 μm
Epitaxial film 13 (4a): Al composition 0.3, thickness 2 μm
Epitaxial film 4b: Al composition 0, thickness 0.1 μm
Epitaxial film 4c: Al composition 0.3, thickness 2 μm
Epitaxial film 5: Al composition 0, thickness 0.5 μm
The above manufacturing steps are summarized as shown in FIGS. FIG. 6 is a view showing a state in which the growth support layer 2 in which the window 2a is patterned is formed on the silicon substrate. FIG. 7 is a diagram showing a state in which the solutions S1 to S6 corresponding to the respective epitaxial layers are subsequently brought into contact with the silicon substrate (see FIG. 5) to form an epitaxial laminated structure. FIG. 8 shows a state where a stress concentration is generated at the boundary portion 35 between the straight window portion and the window portion surrounding the island-like growth layer in the process of lowering the furnace temperature to room temperature, and the cleavage plane 21 is formed. FIG. The stress concentration is due to the stress F generated due to the difference in thermal expansion coefficient.

  Thereafter, the other portion of the epitaxial film was removed leaving only the island-like epitaxial multilayer film. Next, as shown in FIG. 9, a rectangular electrode 17 and a lower electrode (not shown) were formed on the island-like epitaxial laminated film, and when a current was passed between both electrodes, laser oscillation could be obtained. These electrodes are electrically connected to an integrated circuit formed on the silicon substrate.

  Next, the mechanism by which cleavage planes occur in the above treatment process will be described. As shown in FIG. 10, after the epitaxial laminated film is grown by the slide boat method, the temperature is lowered from the growth temperature to room temperature. Due to this temperature drop, stress is generated due to the difference in thermal expansion coefficient between the silicon substrate and the epitaxial growth layer (see FIG. 11). That is, for example, in the case of a GaAs epitaxial growth layer on a silicon substrate, tensile stress F is generated in the epitaxial growth layer because the thermal contraction of the epitaxial film growth layer is large. Due to the shape effect of the epitaxial growth layer, stress concentration occurs at the position 35 as described above, and a crack is generated at this position (FIG. 11).

  If the straight window portion is formed so as to extend in the direction perpendicular to the cleavage plane of the epitaxial growth layer, the end including the straight window portion is removed, leaving an island-shaped growth support layer in the center. As a result, it is possible to form a laser oscillation portion that resonates between two cleaved faces 21 that are opposed to each other in parallel.

  According to the above process, an optoelectronic integrated device can be automatically manufactured only by controlling the temperature without manually performing each process of each laser element, which requires a very skillful process of cleaving. it can. In the above optoelectronic integrated device, a plurality of optoelectronic integrated devices can be manufactured in parallel if the window pattern of the growth support layer is appropriately designed. As a result, a large number of optoelectronic integrated devices can be automatically manufactured with high accuracy.

  The lateral current confinement structure of the laser oscillation part is not limited to electrodes, but all of those used in ordinary laser processes, such as those that increase the resistance of the surrounding region by ion implantation, and those that produce the confinement structure by buried growth Is applicable. However, in the case of a process that involves two or more crystal growths, such as by embedding growth, it is possible to control how many times the temperature is lowered after the growth by appropriately designing the shape of the growth layer. be able to. For example, if it is set so that cleavage occurs in the temperature lowering process after the last growth, a fresh cleavage plane can be finally obtained. In addition, the cleavage process is separated from the crystal growth if the cleavage process does not occur in the temperature lowering process from the growth temperature but the subsequent heat treatment, for example, the cleavage occurs in the process of raising the temperature higher than the growth temperature and lowering the temperature. And the degree of freedom of the process is improved.

  12 to 14 are modified examples of FIGS. 6 to 8. An optoelectronic integrated device similar to the above can also be manufactured by using the window pattern 2a shown in FIG. The difference between the window pattern in FIG. 12 and that shown in FIG. 6 is that the window pattern surrounding the island-like growth support layer is completely closed and continuous in FIG. 6 whereas this is not the case in FIG. , Partially broken. When the ELO growth is performed, the ELO film is laterally grown in the same shape as that of FIG. 7 to compensate for the partially interrupted portion, so that the same optoelectronic integrated device can be obtained through the same process.

  FIG. 15 shows the Al composition x of AlGaAs in each stacked portion of the optoelectronic integrated device in the above embodiment. In the above embodiment, the active layer has been described as an apparatus having a double hetero structure. However, it goes without saying that the active layer may be formed with an MQW (Multi-Quantum Well) structure as shown in FIG. Nor.

  Next, modifications of the other embodiments of the present invention including the above-described embodiment will be introduced in a list.

  The opposed end faces of the optoelectronic integrated device may be formed by cleavage planes parallel to each other.

  With this configuration, a laser oscillation unit can be formed as the light emitting unit.

  Further, when viewed in a plan view, the cleavage plane can be located at an end where the width of the ELO layer in the direction along the cleavage plane decreases outward.

  Further, as viewed in a plan view, the cleavage plane can be located in a portion where the width of the ELO layer in the direction along the cleavage plane is partially narrowed (see FIGS. 16 and 17).

  With this configuration, for example, by lowering the temperature, a cleavage plane can be formed by stress resulting from a difference in thermal expansion coefficient between the silicon substrate and the compound semiconductor layer, and a resonance part of laser oscillation can be formed.

  The ELO layer is an InGaAsP layer, InAsP layer, InGaAs layer, GaAs layer, AlGaAs layer, InP layer, AlInGaP layer, InGaP layer, GaAsP layer, GaP layer, AlP layer, AlGaP layer, GaN layer, GaInNAs layer, GaPN layer Any of an InPN layer, an AlPN layer, an InGaN layer, and an AlInGaN layer may be used.

  With this configuration, a compound semiconductor layer suitable for light emission can be formed on the silicon substrate.

  The growth support layer may be an insulator, a conductor, or a dielectric multilayer body.

With the above configuration, not only SiO ₂ but also other nitride films, metal films, and dielectric films can be used as the growth support layer, and the manufacturing flexibility can be increased. Examples of the material include the following.
(1) Insulating material: Metal oxide or nitride such as SiN, TiO ₂ , P ₂ O ₃ , Al ₂ O ₃ (2) Conductive material: Metal such as Ti, Fe, Pt, Ni, and more special Refractory metals such as Co, W, Ta, and Mo as metals (also capable of growing at high temperatures)
(3) Dielectric multilayer: MgO ₂ / SiO ₂ multilayer, ZrO ₂ / SiO ₂ multilayer, etc. In the step of epitaxially growing the above compound semiconductor, the slide boat method can be used in the LPE method. .

  This method makes it possible to easily form an epitaxial film having excellent crystallinity at a low cost.

  Also, after epitaxially growing the compound semiconductor in the lateral direction and forming a laminated epitaxial growth film including the active layer, the temperature is lowered at a predetermined cooling rate or more, and the boundary portion between the surrounding window portion and the linear window portion is seen in plan view. Cleavage can occur.

  By this method, a resonance portion necessary for laser oscillation can be formed between two cleaved surfaces. In addition, if the extending direction (longitudinal direction) of the linear window portion is set to a direction perpendicular to the cleavage plane, for example, [011], cleavage is likely to occur.

  In the above embodiment, an optoelectronic integrated device having a laser oscillation unit has been described. However, the laser oscillation unit may be an LED (Light Emitting Diode).

  While the embodiments of the present invention have been described above, the embodiments of the present invention disclosed above are merely examples, and the scope of the present invention is not limited to these embodiments. The scope of the present invention is defined by the terms of the claims, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  According to the optoelectronic integrated device and the manufacturing method thereof of the present invention, an epitaxial film of an arbitrary compound semiconductor suitable for light emission can be stacked on a silicon substrate having an integrated circuit very easily and at low cost. Since the portion can be automatically formed between two cleavage planes only by temperature control, it is expected to be widely used.

1 is a plan view of an optoelectronic integrated device in an embodiment of the present invention. It is sectional drawing which follows the II-II line of FIG. It is a figure which illustrates the active layer of a double heterostructure. It is a figure which shows the state which formed the pattern of the window part in the growth support layer in manufacture of the optoelectronic integrated device of FIG. It is a figure which shows the slide boat method used by LPE method in lamination | stacking of an epitaxial film. It is a figure which shows a window part pattern. It is a figure which shows the state which grew the ELO layer and the other epitaxial film. It is a figure which shows the state which produced the cleavage surface by making temperature fall. It is a figure which shows the state which has arrange | positioned the upper electrode. It is a figure which shows the state which formed the epitaxial film of the compound semiconductor on the silicon substrate. It is a figure which shows the position which makes a temperature fall and produces a cleavage crack. It is a figure which shows the modification of a window part pattern. It is a figure which shows the compound semiconductor film epitaxially grown from the window part pattern of FIG. It is a figure which shows the state which caused the temperature fall and the cleavage crack was produced. It is a figure which shows Al composition in the epitaxial laminated film of a compound semiconductor. It is a figure which shows the example which provided the cleavage surface in the part in which the width | variety of the ELO layer was partially narrowed. It is a figure which shows another example which provided the cleavage surface in the part in which the width | variety of the ELO layer is partially narrowed.

Explanation of symbols

  1 silicon substrate, 2 growth support layer, 2a window, 3 ELO film, 4 active layer 4a n-type AlGaAs layer, 4b i-type AlGaAs layer, 4c p-type AlGaAs layer, 5p-type AlGaAs cladding layer, 10 optoelectronic integrated device, 12 GaAs buffer layer, 13 n-type AlGaAs cladding layer, 17 upper electrode, 21 cleaved surface, 35 stress concentration part, 51 slide base, 51a recess, 52 boat.

Claims (8)

Forming a growth support layer on the silicon substrate;
Patterning the growth support layer to form an enclosing window that is a groove surrounding the island-shaped growth support layer, and a linear window extending outwardly from the island-shaped growth support layer; and
Embedding the window portion and epitaxially growing a compound semiconductor layer on the growth support layer .
Said compound semiconductor is epitaxially laterally grown, after forming a laminated epitaxial growth film including an active layer, the temperature was lowered, that cause cleavage fracture in the boundary portion between the surrounding window in plan view and the linear window A method of manufacturing an optoelectronic integrated device. In the step of epitaxial lateral growth of the compound semiconductor, using LPE (Liquid Phase Epitaxial) method, a manufacturing method of the optoelectronic integrated apparatus according to claim 1. The method for manufacturing an optoelectronic integrated device according to claim 1, wherein the linear window portion extends in parallel with a <011> direction. 4. The method of manufacturing an optoelectronic integrated device according to claim 1, wherein the surrounding window portion is formed by a combination of linear trenches. The method for manufacturing an optoelectronic integrated device according to claim 4, wherein the straight trench includes a portion parallel to a <011> direction. 6. The method for manufacturing an optoelectronic integrated device according to claim 1, wherein a cleaved surface parallel to the {0-1-1} plane is formed at the boundary portion. The boundary portion is located at an end where a width of the compound semiconductor layer in a direction along a cleavage plane formed by cleavage fracture is reduced outward as viewed in a plan view. The manufacturing method of the optoelectronic integrated device as described. The said boundary part is located in the part where the width | variety of the said compound semiconductor layer of the direction along the cleavage plane formed by cleavage fracture | rupture is partially narrowed seeing planarly. The manufacturing method of the optoelectronic integrated device as described.

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