JP4581864B2 - 半導体基板への貫通配線の形成方法 - Google Patents
半導体基板への貫通配線の形成方法 Download PDFInfo
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- JP4581864B2 JP4581864B2 JP2005181074A JP2005181074A JP4581864B2 JP 4581864 B2 JP4581864 B2 JP 4581864B2 JP 2005181074 A JP2005181074 A JP 2005181074A JP 2005181074 A JP2005181074 A JP 2005181074A JP 4581864 B2 JP4581864 B2 JP 4581864B2
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- Prior art keywords
- semiconductor substrate
- hole
- metal
- insulating layer
- wiring
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
- H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
- H10W20/0242—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes from the back sides of the chips, wafers or substrates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
- H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
- H10W20/0234—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes that stop on pads or on electrodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
- H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
- H10W20/0245—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising use of blind vias during the manufacture
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W20/211—Through-semiconductor vias, e.g. TSVs
- H10W20/212—Top-view shapes or dispositions, e.g. top-view layouts of the vias
- H10W20/2125—Top-view shapes
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
以下、本実施形態における半導体基板への貫通配線の形成方法について図1に基づいて説明するが、図1(a)〜(e)における半導体基板1はダイシング工程を行う前のウェハである。また、本実施形態では、半導体基板1としてシリコン基板を用いる場合について例示する。
以下、本参考例における半導体基板への貫通配線の形成方法について図2に基づいて説明するが、図2(a)〜(h)における半導体基板1はダイシング工程を行う前のウェハである。また、本参考例では、半導体基板1としてシリコン基板を用いる場合について例示する。
2 貫通孔
3 絶縁層
4 金属層
5 金属部
6 貫通配線
Claims (1)
- 半導体基板への貫通配線の形成方法であって、半導体基板に厚み方向に貫通し前記厚み方向の両側から中間位置に近づくにつれて開口面積が徐々に小さくなる貫通孔を形成する貫通孔形成工程と、半導体基板の一表面および他表面および貫通孔の内周面に絶縁層を形成する絶縁層形成工程と、半導体基板の前記他表面側を除いて前記一表面側および貫通孔の内側で絶縁層の表面に金属層を被着する金属層形成工程と、金属層をシード層として電解メッキ法により貫通孔の内側を埋め込む金属部であり金属層とともに貫通配線を構成する金属部を析出させる電解メッキ工程とを備え、絶縁層形成工程では、絶縁層を形成した後も貫通孔の内側では半導体基板の厚み方向の両側から中間位置に近づくにつれて開口面積が徐々に小さくなる形状となるように絶縁層を成膜することを特徴とする半導体基板への貫通配線の形成方法。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005181074A JP4581864B2 (ja) | 2005-06-21 | 2005-06-21 | 半導体基板への貫通配線の形成方法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005181074A JP4581864B2 (ja) | 2005-06-21 | 2005-06-21 | 半導体基板への貫通配線の形成方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2007005403A JP2007005403A (ja) | 2007-01-11 |
| JP4581864B2 true JP4581864B2 (ja) | 2010-11-17 |
Family
ID=37690754
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2005181074A Expired - Fee Related JP4581864B2 (ja) | 2005-06-21 | 2005-06-21 | 半導体基板への貫通配線の形成方法 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4581864B2 (ja) |
Families Citing this family (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8569876B2 (en) | 2006-11-22 | 2013-10-29 | Tessera, Inc. | Packaged semiconductor chips with array |
| WO2010035379A1 (ja) | 2008-09-26 | 2010-04-01 | パナソニック株式会社 | 半導体装置及びその製造方法 |
| US9640437B2 (en) | 2010-07-23 | 2017-05-02 | Tessera, Inc. | Methods of forming semiconductor elements using micro-abrasive particle stream |
| US8847380B2 (en) | 2010-09-17 | 2014-09-30 | Tessera, Inc. | Staged via formation from both sides of chip |
| US8587126B2 (en) | 2010-12-02 | 2013-11-19 | Tessera, Inc. | Stacked microelectronic assembly with TSVs formed in stages with plural active chips |
| US8736066B2 (en) | 2010-12-02 | 2014-05-27 | Tessera, Inc. | Stacked microelectronic assemby with TSVS formed in stages and carrier above chip |
| US8610264B2 (en) * | 2010-12-08 | 2013-12-17 | Tessera, Inc. | Compliant interconnects in wafers |
| JP2013207006A (ja) * | 2012-03-28 | 2013-10-07 | Toppan Printing Co Ltd | 貫通電極付き配線基板及びその製造方法 |
| KR101992352B1 (ko) | 2012-09-25 | 2019-06-24 | 삼성전자주식회사 | 반도체 장치 |
| JP6002008B2 (ja) * | 2012-11-19 | 2016-10-05 | 富士電機株式会社 | 半導体装置の製造方法 |
| JP2015002299A (ja) * | 2013-06-17 | 2015-01-05 | 株式会社ザイキューブ | 漏斗状の貫通電極およびその製造方法 |
| JP6213143B2 (ja) * | 2013-10-23 | 2017-10-18 | 富士電機株式会社 | 半導体基板、及び、半導体基板の製造方法 |
| JP6450296B2 (ja) * | 2015-10-05 | 2019-01-09 | 浜松ホトニクス株式会社 | 配線構造体、及び配線構造体の製造方法 |
| JP6877896B2 (ja) * | 2016-06-21 | 2021-05-26 | 富士通株式会社 | 半導体装置及び半導体装置の製造方法 |
| CN111863754A (zh) * | 2020-08-28 | 2020-10-30 | 中北大学 | 一种具有内部限位环的硅通孔互连结构及其形成方法 |
| JP2022133964A (ja) * | 2021-03-02 | 2022-09-14 | ソニーグループ株式会社 | 半導体基板、半導体基板の製造方法及び半導体基板を有する電子機器 |
| CN119815908B (zh) * | 2025-03-10 | 2025-07-11 | 合肥晶合集成电路股份有限公司 | 一种高集成度的双层集成电路结构及制备方法 |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63202940A (ja) * | 1987-02-18 | 1988-08-22 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
| US20020004320A1 (en) * | 1995-05-26 | 2002-01-10 | David V. Pedersen | Attaratus for socketably receiving interconnection elements of an electronic component |
| JP3918350B2 (ja) * | 1999-03-05 | 2007-05-23 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
| JP2001044197A (ja) * | 1999-08-04 | 2001-02-16 | Sharp Corp | 半導体装置及びその製造方法 |
| JP2003318178A (ja) * | 2002-04-24 | 2003-11-07 | Seiko Epson Corp | 半導体装置及びその製造方法、回路基板並びに電子機器 |
| JP2004128352A (ja) * | 2002-10-04 | 2004-04-22 | Mitsubishi Electric Corp | 半導体装置及び半導体装置の製造方法 |
| JP4019960B2 (ja) * | 2003-01-31 | 2007-12-12 | 三菱電機株式会社 | 基板の製造方法 |
| JP4248928B2 (ja) * | 2003-05-13 | 2009-04-02 | ローム株式会社 | 半導体チップの製造方法、半導体装置の製造方法、半導体チップ、および半導体装置 |
| US7345350B2 (en) * | 2003-09-23 | 2008-03-18 | Micron Technology, Inc. | Process and integration scheme for fabricating conductive components, through-vias and semiconductor components including conductive through-wafer vias |
| JP2006012889A (ja) * | 2004-06-22 | 2006-01-12 | Canon Inc | 半導体チップの製造方法および半導体装置の製造方法 |
| JP2006041148A (ja) * | 2004-07-27 | 2006-02-09 | Seiko Epson Corp | 半導体装置の製造方法、半導体装置、及び電子機器 |
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2005
- 2005-06-21 JP JP2005181074A patent/JP4581864B2/ja not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2007005403A (ja) | 2007-01-11 |
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