JP4584437B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
[Industrial application fields]
  The present invention relates to SOI (SiliconOnIMore particularly, the present invention relates to a semiconductor device having an SOI structure suitable for a large-scale system LSI with high integration, high speed, and high reliability.
  Conventionally, for SOI structure semiconductor devices, bonded SOI wafers or SIMOX (Separation byIMplantedOXygen) MIS field-effect transistors with reduced junction capacitance, depletion layer capacitance, threshold voltage, etc. are formed on a fully depleted SOI substrate using a SOI wafer with an oxide film formed to achieve higher speed and lower power Limited use has beenThe use of a thin SOI substrate has made it impossible to miniaturize MIS field-effect transistors that require a large channel width, making it difficult to achieve high integration, and making it difficult to form highly integrated protection circuits with excellent protection characteristics.However, it is becoming difficult to cope with the formation of large-scale semiconductor integrated circuits having various functions.
  Therefore, there is a demand for means capable of forming various semiconductor elements into a highly integrated SOI structure by a relatively easy manufacturing process.
[0002]
[Prior art]
  FIG.as well asFIG.Is a conventional semiconductor device,FIG.Is a schematic plan view,FIG.Is a schematic cross-sectional side view (channel length direction), a semiconductor integrated circuit including a high-speed N-channel MIS field-effect transistor with a high-current drive N-channel MIS field-effect transistor and an SOI structure formed using a bonded SOI wafer A part of the circuit is shown, 51 is a p-type silicon (Si) substrate, 52 is a bonded oxide film, 53 is a p-type SOI substrate, 54 is an element isolation region forming trench and buried oxide film, 55 Is n-type source / drain region, 56 is n⁺Type source / drain region 57 is a gate oxide film (SiO₂), 58 is a gate electrode (WSi / polySi), 59 is a base oxide film (SiO₂), 60 is side wall (SiO₂), 61 is an oxide film for impurity block (SiO₂), 62 is a phosphosilicate glass (PSG) film, 63 is a barrier metal (Ti / TiN), 64 is a plug (W), 65 is a barrier metal (Ti / TiN), 66 is an AlCu wiring, and 67 is a barrier metal (Ti / TiN).
  FIG.In this case, the bottom part is a p-type silicon film 51 formed on a p-type silicon substrate 51, and the side part is isolated and isolated in an island shape by an isolation region forming trench and a buried oxide film 54. SOI substrate 53 is formed, n-type source / drain region 55 self-aligned with gate electrode 58 and n self-aligned with sidewall 60 are formed on p-type SO1 substrate 53.⁺Two SOI-type N-channel MIS field effect transistors having an LDD structure composed of type source / drain regions 56 are formed.FIG.As is clear, the high-speed MIS field-effect transistor with the same structure, but the left side shows a very compact MIS field effect transistor, and the right side shows a large current-driven MIS with a very large occupied area formed at the input or output section. 1 shows a field effect transistor.
  Therefore, it is normal to reduce the junction capacitance by forming the source / drain region surrounded by the insulating film, reduce the depletion layer capacitance by fully depleting the SOI substrate, and reduce the threshold voltage by improving the subthreshold characteristics, etc. Compared with a semiconductor integrated circuit formed of an N-channel MIS field effect transistor formed on a bulk wafer, a higher speed and lower power can be achieved.
  However, high-speed MIS field-effect transistors used in random logic circuits have a small footprint, but large-current-driven MIS field-effect transistors used for input or output must have a wide channel width. Therefore, on the surface layout, an extremely large occupation area is required, and the degree of integration cannot be improved in a semiconductor integrated circuit such as a gate array, a microprocessor, and a system LSI that requires a large number of input terminals and output terminals. There is a drawback that it is difficult to form a large-scale semiconductor integrated circuit.
[0003]
[Problems to be solved by the invention]
  The problem to be solved by the present invention is, as shown in the prior art, a high-speed MIS field effect transistor formed in an SOI structure and a large current for input or output that is always used in the formation of a semiconductor integrated circuit. The coexistence formation with the driving MIS field effect transistor requires a large channel area because the large current driving MIS field effect transistor secures a large driving current, and therefore requires a very large occupied area in the surface layout. Since the degree of integration was not improved, it was difficult to form a large-scale semiconductor integrated circuit that required a large number of input terminals and output terminals due to limitations such as yield, and high-speed MIS field effect. Gate array with various functions due to the difficulty of highly integrated coexistence formation of transistors and various semiconductor elements (especially longitudinally operating elements) In microprocessors and system LSI or the like is that the formation of large-scale semiconductor integrated circuit is difficult.
0004
[Means for Solving the Problems]
  The above issuesA thin SOI substrate and a thick SOI substrate are provided on the semiconductor substrate via an insulating film, and the thin SOI substrate is provided with a first MIS field effect transistor that operates on the upper surface of the thin SOI substrate, and the thick SOI substrate is provided. The SOI substrate is provided with a second MIS field effect transistor that operates on at least a side surface of the thick SOI substrate, or a protective circuit element that operates the thick SOI substrate in a vertical direction.This can be solved by a semiconductor device.
[0005]
[Operation]
  That is, in the semiconductor device of the present invention, a thin SOI substrate is formed by a SIMOX oxide film formed by oxygen ion implantation and high temperature annealing on a part of a thick SOI substrate formed by bonding oxide film on a semiconductor substrate. Forming a deep trench in a part of the semiconductor substrate, forming a SIMOX oxide film on the entire surface, forming a thin SOI substrate, and then forming an epitaxial silicon layer in the deep trench portion to form a thick SOI substrate; After a pair of shallow trenches and a pair of deep trenches are formed on a semiconductor substrate, an oxide film (hereinafter referred to as a bridge oxide film) is formed by connecting the fine trenches by selective oxidation in the lateral direction using an oxidation mask layer. By forming a thin SOI substrate and a thick SOI substrate, it is possible to form SOI substrates having different thicknesses on one semiconductor substrate. .
  Therefore, MIS field-effect transistors for high-speed and highly integrated logic circuits are formed on a thin fully-depleted SOI substrate, and miniaturization is achieved by providing a channel region on the side of the SOI substrate on a thick SOI substrate. In addition, it is possible to form a large current drive MIS field effect transistor for the input section and the output section.
In addition, high-speed and highly-integrated MIS field-effect transistors for logic circuits are formed on a thin fully-depleted SOI substrate, and high-integration composed of bidirectional PN diodes operating in the vertical (vertical) direction on a thick SOI substrate. In addition, a protection circuit having excellent protection characteristics can be formed.
  In other words, it is possible to form various types of semiconductor integrated circuits for large-scale system LSIs that have high integration, high reliability, and high speed.ComplexSiliconOnIA semiconductor device having a structure (named nsulator, hereinafter abbreviated as CSOI) can be obtained.
[0006]
【Example】
  Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.
  FIG. 1 is a schematic plan view of a first embodiment of the semiconductor device of the present invention, and FIG. 2 is a schematic side sectional view of the first embodiment of the semiconductor device of the present invention (cross-sectional view taken along the line pp in FIG. 1). FIG. 3 is a schematic side sectional view of the first embodiment of the semiconductor device of the present invention (a cross-sectional view taken along the line q-q in FIG. 1).4 is a schematic sectional side view of a second embodiment of the semiconductor device of the present invention, FIG. 5 is a schematic sectional side view of the third embodiment of the semiconductor device of the present invention, and FIGS. 6 to 11 are semiconductors of the present invention. It is process sectional drawing of one Example of the manufacturing method in an apparatus.
  Throughout the drawings, the same object is denoted by the same reference numeral. However, diagonal lines are written only for main insulating films. 1 to 3 show a first embodiment of the semiconductor device of the present invention, FIG. 1 is a schematic plan view, FIG. 2 is a schematic side cross-sectional view (cross-sectional view taken along the line pp in FIG. 1, channel length direction), Fig. 3 is a schematic side cross-sectional view (q-q arrow cross-sectional view in Fig. 1, in the channel width direction). This is a high-speed SO1 structure using a bonded SOI wafer and using an oxide film formed by the SIMOX method. 1 shows a part of a semiconductor integrated circuit including an N-channel MIS field-effect transistor and a large-current-driven N-channel MIS field-effect transistor.¹⁵cm⁻³About p-type silicon substrate, 2 is about 0.5μm bonding oxide film (SiO₂), 3a is a p-type SOI substrate having a thickness of about 5 μm, 3b is a p-type SOI substrate having a thickness of about 0.1 μm, and 4 is a trench for forming an isolation region and a buried oxide film (SiO 2).₂), 5 is about 0.1μm SIMOX formation oxide film (SiO₂), 6 is a p-type semiconductor layer (back channel gate electrode), 7 is 10¹⁷cm⁻³About n-type source / drain region, 8 is 10²⁰cm⁻³Degree n⁺9a is a metal source region (W) of a high-speed N-channel MIS field effect transistor, 9b is a metal drain region (W) of a high-speed N-channel MIS field effect transistor, and 9c is a high-current drive N-channel MIS The metal source region (W) of the field effect transistor, 9d is the metal drain region (W) of the N-channel MIS field effect transistor driven by a large current, and 10 is a gate oxide film (Ta₂O_Five/ SiO₂), 11 is a barrier metal (TiN) of about 20 nm, 12 is a gate electrode (Al) having a gate length of about 0.2 μm, 13 is a phosphosilicate glass (PSG) film of about 0.8 μm, 14 is a barrier metal (Ti / TiN), 15 is a plug (W), 16 is a barrier metal (Ti / TiN) of about 50 nm, 17 is an AlCu wiring of about 0.8 μm, and 18 is a barrier metal (Ti / TiN) of about 50 nm.
  In the schematic plan view of FIG. 1, both the high-speed N-channel MIS field effect transistor on the left side and the high-current N-channel MIS field effect transistor on the right side are finely formed with the same occupation area on the surface layout.
  In the schematic side sectional view of FIG. 2 (cross-sectional view taken along the line pp in FIG. 1, in the channel length direction), the left half isolated by the trench for forming the isolation region and the buried oxide film 4 has a p-type A pair of metal sources on an oxide film (SIMOX formation oxide film) 5 formed by implanting oxygen ions in a part of a thick p-type SOI substrate 3a bonded to the silicon substrate 1 through an oxide film 2 A drain region (9a, 9b) is provided, and a thin p-type SOI substrate 3b is provided between the metal source drain region (9a, 9b) so as to be in contact with a part of the metal source drain region (9a, 9b). N on the thin p-type SOI substrate 3b in contact with the metal source / drain regions (9a, 9b) to be⁺Type source / drain region 8 is provided.⁺An n-type source / drain region 7 is provided in contact with the source / drain region 8, and a gate oxide film (Ta) is formed on the thin p-type SOI substrate 3b and on the side walls of the opposing metal source / drain regions (9a, 9b).₂O_Five/ SiO₂) 10 and this gate oxide film (Ta₂O_Five/ SiO₂) 10 and the gate electrode (Al) 12 having the barrier metal (TiN) 11 is buried flat, and the p-type semiconductor layer (back channel gate electrode) 6 under the SIMOX formation oxide film 5 has a back channel. A high-speed N-channel MIS field-effect transistor having a structure to which an off voltage is applied to prevent the occurrence of the occurrence of the MIS field-effect transistor (not shown) is formed. In the right half, a pair of metal source / drain regions (9c, 9d) are provided on the bonded oxide film 2, and a metal source / drain region (9c, 9d) is provided between the metal source / drain regions (9c, 9d). A thick p-type SOI substrate 3a is provided in contact with a part of the thick n-type SOI substrate 3a in contact with the opposing metal source / drain regions (9c, 9d).⁺Type source / drain region 8 is provided.⁺An n-type source / drain region 7 is provided in contact with the source / drain region 8, and a gate oxide film (Ta) is formed on the thick p-type SOI substrate 3a and on the side walls of the opposing metal source / drain regions (9c, 9d).₂O_Five/ SiO₂) 10 and this gate oxide film (Ta₂O_Five/ SiO₂) 10 and a gate electrode (Al) 12 having a barrier metal (TiN) 11 is embedded in a flat manner to form a large current drive N-channel MIS field effect transistor. (If the bonded oxide film 2 is thickened, a back channel gate electrode is not necessarily required, but a p-type silicon substrate 1 may be used as a back channel gate electrode and an off voltage may be applied.)
  In the schematic side cross-sectional view of FIG. 3 (q-q arrow cross-sectional view of FIG. 1, channel width direction), a side cross-sectional view in the channel width direction of the N-channel MIS field effect transistor driven by large current is shown. A gate oxide film (Ta) is formed on the upper and side surfaces of the thick p-type SOI substrate 3a.₂O_Five/ SiO₂) 10 and this gate oxide film (Ta₂O_Five/ SiO₂) A gate electrode (Al) 12 having a barrier metal (TiN) 11 through 10 is flatly embedded, and has a structure in which a channel is formed not only on the top surface but also on the side surface. A field effect transistor is formed. (A high-speed N-channel MIS field-effect transistor forms a channel only on the top surface.) However, in order to fully deplete a thick SOI substrate, a depletion layer is applied from both sides by a voltage applied to the gate electrodes on both sides. It is necessary to form the channel width on the upper surface so that it can be completely depleted by spreading.
  Therefore, even the side surface of a thick SOI substrate can be used as a channel region, so the large surface drive area used for the input and output sections is the same as that of a high-speed N-channel MIS field effect transistor. The MIS field effect transistor can be formed with extremely high integration.
  In addition, a semiconductor layer consisting of a part of a thick SOI substrate can be formed under the thin SIMOX formation oxide film, and this semiconductor layer can be used as a back channel gate electrode, so back channel leakage can be suppressed and high reliability is possible. Become.
  Further, only the channel region, the low concentration source / drain region, and the very small high concentration source / drain region are formed on the SOI substrate, and most of the source / drain region is not an impurity region but a low resistance conductive film (metal film or Alloy film), the junction capacitance can be reduced (nearly zero) and the resistance of the source / drain region can be reduced, and the source / drain region due to impurities can be formed before the formation of the gate electrode. It is also possible to form a low-resistance gate electrode made of (Al), and Ta having a high dielectric constant.₂O_FiveCan be used as the gate oxide film, so that the gate oxide film can be thickened, and a small current leakage between the gate electrode and the SOI substrate can be improved and the gate capacitance can be reduced.
  As a result, an SOI structure semiconductor device having high integration, high reliability, and high speed can be obtained.
[0007]
  Figure 4In the semiconductor device of the present inventionSecond embodimentAs shown in FIG. 1, a part of a semiconductor integrated circuit including a high-speed N-channel MIS field-effect transistor and a protection circuit having a SO1 structure using a bonded SOI wafer and using a SIMOX forming oxide film is used. 1-9b, 10-18 are the same as in FIG.19Is an n-type thick SOI substrate,20Is n⁺Type impurity region,twenty oneIs p⁺A type impurity region is shown.
  In the same figure, instead of providing a large current N-channel MIS field effect transistor on a thick SOI substrate, an SOI structure semiconductor device having the same structure as FIG. 1 is provided except that a protection circuit comprising a bidirectional PN diode is provided. Is formed. Although not shown here, the n-type thick SOI substrate19A power supply voltage is applied to the p-type thick SOI substrate 3b, and a ground voltage is applied to the p-type thick SOI substrate 3b.
  In this embodiment, as in the first embodiment, in addition to the effect of the high-speed MIS field effect transistor, the protection circuit required for protecting the semiconductor integrated circuit from voltage noise affects other circuits. In addition, it is possible to coexist with a high-speed MIS field-effect transistor having excellent protection characteristics and a small area and operating in a lateral direction. (When forming a PN diode on a thin SOI substrate, it is necessary to secure an n-type SOI substrate and a p-type SOI substrate by increasing the area on the surface and not forming a vertical PN diode. This is disadvantageous for high integration and protection characteristics.)
[0008]
  FIG.In the semiconductor device of the present inventionThird embodimentA semiconductor including a high-speed N-channel MIS field-effect transistor with an SOI structure and a large-current drive N-channel MIS field-effect transistor formed by using a normal p-type silicon substrate (bulk wafer). A part of the integrated circuit is shown, and 1, 3a to 4, 7 to 18 are the same as those in FIG.twenty twoIndicates a thermal oxide film (an oxide film formed at the bottom and in the lateral direction, a bridge oxide film) for forming an SOI structure.
  In the figure, a thick SOI substrate and a thin SOI substrate are formed by using a semiconductor substrate (bulk wafer) and a selective oxidation using an oxidation mask layer, and a bridge oxide film formed in a fine lateral direction. An SOI structure semiconductor device having the same structure as that of FIG. 1 is formed.
  In this embodiment, an effect similar to that of the first embodiment can be obtained by using an inexpensive bulk wafer and an easy process.
[0009]
  The present invention is not limited to the above description. For example, the formation of the metal source / drain region may be a metal film, an alloy film, or two or more kinds of metal films including a barrier metal. A normal polycide gate (WSi / polySi) may be used, and the gate oxide film may be another oxide film or an insulating film.
  As for the MIS field effect transistor, the case of an N-channel MIS field effect transistor is described. However, a P-channel MIS field effect transistor may be used or a CMOS may be used, and a semiconductor substrate used is an N type. However, it may be a P-type or a compound semiconductor substrate.
  In addition, the oxide film for forming the SOI substrate may be a bonded oxide film, a SIMOX formation film, a bridge oxide film using selective oxidation, or an insulating film formed by another method. It may be.
  In addition, the SOI substrate having two kinds of film thickness is used as the SOI substrate, but the present invention can be realized even if the SOI substrate having three or more kinds of film thickness is used.
[0010]
  Next, an embodiment of a method of manufacturing a semiconductor device according to the present invention6 to 11This will be described with reference to FIG. However, here, only the manufacturing method related to the formation of the semiconductor device of the present invention is described, and the description of the manufacturing method related to the formation of various elements (other transistors, resistors, capacitors, etc.) mounted on a general semiconductor integrated circuit is omitted. To do.
  Fig. 6
  An oxide film (SiO2) of about 0.5 μm is formed on a p-type silicon substrate 1.₂) 2 is attached to the surface of the p-type SOI substrate 3a having a thickness of about 5 μm and a chemical vapor deposition oxide film having a thickness of about 600 nm (not shown, SiO₂) Grow up. Next, using the normal photolithography technique, the thick chemical vapor deposition oxide film (not shown) is selectively dry etched anisotropically using a resist (not shown) as a mask layer. Next, the resist (not shown) is removed. Next, a thermal oxide film of about 10 nm (not shown, SiO₂). Next, a p-type SOI substrate 3a heated to about 500 ° C. with a thick oxide film (not shown) as a mask layer, 10¹⁸cm⁻²Ion-implant oxygen with a moderate dose. Next, a thermal oxide film of about 10 nm (not shown, SiO₂) Is removed by etching. Then N₂Annealing is performed at about 1250 ° C. for about 1 hour in an atmosphere to form a p-type SOI substrate 3b of about 0.1 μm and a SIMOX formation oxide film 5 of about 0.1 μm on a part of the thick p-type SOI substrate 3a. Next, the thick oxide film (not shown) is removed by etching.
  FIG.
  Next, about 5nm thermal oxide film (SiO₂)twenty threeTo grow. Next, a nitride film (Si_ThreeN_Four)twenty fourTo grow. Next, using a normal photolithographic technique, using a resist (not shown) as a mask layer, a nitride filmtwenty four,Oxide filmtwenty threeThen, the p-type SOI substrate 3a is selectively anisotropically etched to form a trench for element isolation. Next, the resist (not shown) is removed. Next, chemical vapor deposition oxide film (SiO₂) Is grown, and anisotropic dry etching is performed to fill the trench and form an element isolation region 4.
  FIG.
  Next, using a normal photolithography technique, using a resist (not shown) as a mask layer, a nitride filmtwenty four,Oxide filmtwenty threeThen, the p-type SOI substrates (3a, 3b) are selectively and sequentially subjected to anisotropic dry etching to open metal source / drain formation regions. Next, the resist (not shown) is removed. Next, trench 4 and nitride film embedded with oxide filmtwenty fourAs a mask layer, phosphorus is obliquely ion-implanted into the side surface of the p-type SOI substrate (3a, 3b). Continuously, arsenic ions are obliquely implanted into the side surface of the p-type SOI substrate (3a, 3b). Next, boron is ion-implanted into the p-type SOI substrate 3b using a normal photolithography technique using a resist (not shown) as a mask layer. Next, the resist (not shown) is removed. Next, using a normal photolithography technique, a resist (not shown) and a nitride filmtwenty fourAs a mask layer, boron is ion-implanted into the side surface of the p-type SOI substrate 3a. Next, the resist (not shown) is removed. Next, N at about 900 ° C₂N-type source / drain regions 7 and n are diffused laterally by applying annealing.⁺A type source / drain region 8 is formed. (n-type source / drain regions 7 and n⁺If it is difficult to control the lateral diffusion of the type source / drain region 8, a separate heat treatment may be applied. At the same time, the substrate concentration of the p-type SOI substrates (3a, 3b) is controlled to control the threshold voltage. When ion implantation is performed on the side surface of the p-type SOI substrate (3a, 3b), a thin barrier metal (Ti / TiN) is provided on the side surface of the p-type SOI substrate (3a, 3b) without direct implantation. Diagonal ion implantation of phosphorus, arsenic, and boron may be performed through metal.
  FIG.
  Next, a tungsten film (W) is grown by sputtering. Next, Chemical Mechanical Laboratory (ChemicalMechanicalPThe metal source / drain regions (9a, 9b, 9c, 9d) are formed flatly by olishing (hereinafter abbreviated as CMP).
  FIG.
  Next, using a normal photolithography technique, using a resist (not shown) as a mask layer, a nitride filmtwenty fourAnd oxide filmtwenty threeAnisotropic dry etching. (Part where the gate electrode is formed on the upper surface) Next, a part of the oxide film buried in the oxide isolation region forming trench 4 (extraction part for connecting the gate electrode of the high-speed MIS field effect transistor) is about 0.2 μm Perform anisotropic dry etching. Using normal photolithography technology continuously, using a resist (not shown) that covers the high-speed MIS field-effect transistor as a mask layer, forming an element isolation region that embeds an oxide film of a high-current drive MIS field-effect transistor An anisotropic dry etching is performed on a part of the oxide film of the trench 4 for etching to about 5 μm (until all side surfaces of the thick SOI substrate are exposed). Next, the resist (not shown) is removed. Next, a gate oxide film (Ta₂O_Five/ SiO₂) Grows 10. Next, a barrier metal (TiN) 11 of about 20 nm and an Al film 12 to be a gate electrode of about 0.2 μm are grown by continuous sputtering. Next, the gate electrode 12 is formed by flat filling by chemical mechanical polishing (CMP).
  FIG.
  Next, a phosphosilicate glass (PSG) film 13 of about 0.8 μm is grown by chemical vapor deposition. Next, using a normal photolithography technique, the PSG film 13 is anisotropically dry etched using a resist (not shown) as a mask layer to selectively open contact holes. Next, Ti and TiN 14 as barrier metals are successively grown by sputtering. Next, a tungsten film is grown on the entire surface by chemical vapor deposition. Next, the contact hole is filled flat by chemical mechanical polishing (CMP) to form a plug (W) 15.
  Figure 2
  Next, Ti and TiN 16 as barrier metals are successively grown by sputtering. Next, Al (containing several percent of Cu) 17 to be a wiring is grown to about 0.8 μm by sputtering. Next, Ti and TiN 18 as barrier metals are successively grown by sputtering. Next, using ordinary photolithography technology, an AlCu wiring 17 is formed by anisotropic dry etching the barrier metal, Al (including several percent of Cu) and the barrier metal using a resist (not shown) as a mask layer. A semiconductor device is completed.
  In the manufacturing method described above, the buried layer is formed by anisotropic dry etching in some processes, but all of these processes may be performed by chemical mechanical polishing (CMP).
[0011]
【The invention's effect】
  As described above, according to the semiconductor device of the present invention, the bonded oxide film and the selectively formed SIMOX oxide film, the SIMOX formed oxide film and the selectively formed epitaxial layer, the trenches of different depths, the selectively oxidized formed bridge oxide film, and the like. By technology, a thin SO1 substrate and a thick SOI substrate can be formed on the same semiconductor substrate.
Therefore, MIS field-effect transistors for high-speed and highly integrated logic circuits are formed on a thin fully-depleted SOI substrate, and miniaturization is achieved by providing a channel region on the side of the SOI substrate on a thick SOI substrate. In addition, it is possible to form a large current drive MIS field effect transistor for the input section and the output section.
In addition, MIS field-effect transistors for high-speed and highly-integrated logic circuits are formed on a thin fully-depleted SOI substrate, and high-integration and protection characteristics consisting of bidirectional PN diodes for vertical operation are formed on a thick SOI substrate. It is also possible to form an excellent protection circuit.
  That is, it is possible to obtain a semiconductor device having a composite SOI (CSOI) structure that enables formation of various semiconductor integrated circuits for large-scale system LSIs that have extremely high integration, high reliability, and high speed.
[Brief description of the drawings]
FIG. 1 is a schematic plan view of a first embodiment of a semiconductor device of the present invention.
2 is a schematic side sectional view of the first embodiment of the semiconductor device of the present invention (a cross-sectional view taken along the line pp in FIG. 1).
3 is a schematic side cross-sectional view of the first embodiment of the semiconductor device of the present invention (a cross-sectional view taken along the line q-q in FIG. 1).
FIG. 4 is a schematic side sectional view of a second embodiment of the semiconductor device of the present invention.
FIG. 5 is a schematic side sectional view of a third embodiment of the semiconductor device of the present invention.
FIG. 6 is a process cross-sectional view of an embodiment of a method for manufacturing a semiconductor device according to the present invention.
FIG. 7 is a process cross-sectional view of an embodiment of a manufacturing method of a semiconductor device of the present invention.
FIG. 8 is a process cross-sectional view of an embodiment of a manufacturing method of a semiconductor device of the present invention.
FIG. 9 is a process cross-sectional view of an embodiment of a method for manufacturing a semiconductor device of the present invention.
FIG. 10 is a process cross-sectional view of an embodiment of a method for manufacturing a semiconductor device according to the present invention.
FIG. 11 is a process cross-sectional view of an embodiment of a manufacturing method of a semiconductor device of the present invention.
FIG. 12 is a schematic plan view of a conventional semiconductor device.
FIG. 13 is a schematic side sectional view of a conventional semiconductor device.
[Explanation of symbols]
1 p-type silicon (Si) substrate
2 Bonding oxide film (SiO₂)
3a Thick p-type SOI substrate
3b Thin p-type SOI substrate
4 Trench for element isolation region and buried oxide film (SiO₂)
5 SIMOX formation oxide film (SiO₂)
6 p-type semiconductor layer (back channel gate electrode)
7 n-type source / drain region
8 n⁺Type source / drain region
9a Metal source region (W) of high-speed MIS field-effect transistor
9b Metal drain region (W) of high-speed MIS field-effect transistor
9c Metal source region (W) of high current drive MIS field effect transistor
9d Metal drain region (W) of MIS field effect transistor driven by high current
10 Gate oxide film (Ta₂O_Five/ SiO₂)
11 Barrier metal (TiN)
12 Gate electrode (Al)
13 Phosphosilicate glass (PSG) film
14 Barrier metal (Ti / TiN)
15 Plug (W)
16 Barrier metal (Ti / TiN)
17 AlCu wiring
18 Barrier metal (Ti / TiN)
19 n-type thick SOI substrate
20 n ⁺ Type impurity region
21 p ⁺ Type impurity region
22 Thermal oxide film (bridge oxide film) for SOI structure formation
23 Oxide film (SiO ₂ )
24 Nitride (Si _Three N _Four )

Claims (4)

A thin semiconductor layer (SOI substrate) and a thick semiconductor layer (SOI substrate) are provided on the semiconductor substrate via an insulating film, and the thin SOI substrate includes a first MIS electric field that operates on an upper surface of the thin SOI substrate. An effect transistor is provided, and the thick SOI substrate is provided with a second MIS field effect transistor that operates on at least a side surface of the thick SOI substrate . In the second MIS field effect transistor, a source / drain region made of an impurity is provided on the thick SOI substrate immediately below the gate electrode provided on the upper side, and the thick SOI substrate just below the gate electrode is provided outside the thick SOI substrate. 2. The semiconductor device according to claim 1, wherein a source / drain region (metal source / drain region) made of a conductive film in contact with the impurity source / drain region is provided. The second MIS field effect transistor according to claim wherein said conductive film is the gate electrode is provided over the opposite second gate insulating film in the side surface of the thick SOI substrate is non provided 2. The semiconductor device according to 2 . A method for manufacturing a semiconductor device, wherein a first MIS field effect transistor is provided on a thin SOI substrate and a second MIS field effect transistor is provided on a thick SOI substrate, the insulating film being formed on the semiconductor substrate. forming a thin SOI substrate and the thick SOI substrate whole surface mask layer, selectively trench isolation region for insulating separating the thin SOI substrate and the thick SOI substrate on which the mask layer is formed in an island shape A step of forming, a step of further selectively etching away the thin SOI substrate and the thick SOI substrate on which the remaining mask layer is formed, and forming a first opening, and the exposed thin SOI substrate Impurity ion implantation is performed on two opposing side surfaces of the substrate and the thick SOI substrate, annealing is performed to form an impurity source / drain region, and the conductive film is embedded in the first opening portion flatly. A step of writing, further remaining the mask layer is removed by etching to expose the step of forming a second opening, the remaining two opposing sides of the thick SOI substrate on which the conductive film is not embedded forming a third opening, said second and performs, burying flat gate insulating film and a gate electrode on the third opening, said first MIS in the thin SOI substrate A method of manufacturing a semiconductor device, comprising: forming a field effect transistor; and forming the second MIS field effect transistor on the thick SOI substrate.