JP4593066B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a structure of a MOS type semiconductor element used in a composite semiconductor device using an SOI (Silicon on Insulator) substrate and a manufacturing method thereof, and in particular, to improve characteristics as an insulating layer between electrodes of a MOS type capacitor. The present invention relates to a semiconductor device and a manufacturing method thereof.
[0002]
[Problems to be solved by the invention]
2. Description of the Related Art In recent years, semiconductor devices having a structure in which a plurality of types of semiconductor elements are formed in a composite manner on a semiconductor substrate are widely applied using an SOI substrate. This is because a region layer for forming a semiconductor element is provided as an insulator with an oxide film interposed between the underlying support substrate and can be used as an excellent electrical property. is there.
[0003]
However, it has been reported many times that the film quality of the gate insulating film of the MOS type semiconductor device formed on such an SOI substrate is inferior to the film quality of the gate insulating film formed on the normal bulk silicon substrate. Yes.
[0004]
As a MOS capacitor formed on an SOI substrate, for example, there is a MOS capacitor 1 having a cross-sectional structure as shown in FIG. This is because a thermal oxide film is formed as a gate insulating film 8 in a state in which a diffusion layer 6 and a LOCOS 7 serving as electrodes are formed on an SOI substrate 5 having a silicon layer 4 formed on an oxide film 3 on a support substrate 2. The capacitor upper electrode 9 is formed as the upper electrode.
[0005]
FIG. 17 shows the results of measuring the current-voltage characteristics (IV characteristics) of the MOS capacitor 1 for a number of samples. As can be seen from FIG. 17, in the MOS capacitor formed on the SOI substrate, an intermediate breakdown voltage failure (B mode failure) that breaks down at a voltage lower than the intrinsic breakdown voltage of the gate insulating film 8 frequently occurs. Even if a MOS capacitor is formed by the same manufacturing method, it appears as a remarkable defective mode as compared with the case of using a normal bulk silicon substrate.
[0006]
Considering this cause, it can be considered as follows.
[0007]
When a MOS type semiconductor element is formed on an SOI substrate, the SOI substrate has a structure in which a silicon semiconductor layer is formed on a silicon support substrate via buried oxide films having different thermal expansion coefficients. During the heat treatment performed in the process, a bimetal effect unique to the SOI substrate occurs.
[0008]
Due to the bimetal effect inherent to this SOI substrate, at least the silicon semiconductor layer and the thermal oxide film (gate insulating film) formed on the surface of the silicon semiconductor layer behave differently from those formed on the bulk silicon substrate. It is estimated that the film quality is affected.
[0009]
As a gate insulating film of a MOS capacitor formed on a bulk silicon substrate, an ONO film (silicon oxide film / silicon nitride film / silicon oxide film), which is a dielectric laminated film of a silicon oxide film and a silicon nitride film and has both characteristics, is used. )It has been known. When the MOS capacitor 1 shown in FIG. 16 is configured using this ONO (Oxide Nitride Oxide) film as a gate insulating film and the current-voltage characteristics (IV characteristics) are measured, the results shown in FIG. 18 are obtained.
[0010]
From this result, it can be seen that the use of an ONO film as the gate insulating film can suppress the occurrence of B-mode defects as an initial characteristic. However, as a temporal characteristic, when the time-lapse breakdown life characteristic was measured by a constant voltage TDDB (Time Dependency Dielectric Breakdown) method, as shown in FIG. 19, it was newly found that accidental failures frequently occurred, Even when an ONO film is used as the gate insulating film, it has been found that the yield is still low as long as the SOI substrate is used.
[0011]
  The present invention has been made in view of the above circumstances, and an object of the present invention is to deteriorate characteristics caused by a bimetal effect inherent to an SOI substrate that is considered to be generated by heat treatment when a MOS type element is formed on an SOI substrate. As much as possible,In the case of forming a MOS type element on an SOI substrate, an ONO film is used as a gate insulating film of the MOS type element to reduce the intermediate withstand voltage defect and to obtain a high withstand voltage, and to improve the breakdown life with time. There is in doing so.
[0013]
[Means for Solving the Problems]
  According to the first aspect of the present invention, in a semiconductor device having a structure in which a plurality of MOS type elements are formed on an SOI substrate in which a silicon semiconductor layer is formed on a support substrate via a buried insulating film, Since the trench isolation layer reaching the buried insulating film and having a thermal expansion coefficient different from that of the silicon semiconductor layer is provided so as to insulate and isolate at least the formation region of the MOS capacitor, the influence of the bimetal effect unique to the SOI substrate is provided. It can be mitigated by the trench isolation layer, and it effectively suppresses deterioration of the gate insulating film quality in MOS type capacitors with large capacity and size that are built in to absorb surges among MOS type elements. Thus, the characteristics of the MOS type element can be improved.
  Since the trench isolation layer is composed of an insulating layer formed on the side surface of the groove and polycrystalline silicon, and the total thickness dimension of the insulating layer is formed to be 1/3 or more of the width dimension of the groove, Among MOS type elements, the MOS capacitor forming region can be surrounded by a thick insulating layer, and the buffering effect described above can be effectively achieved.
  Also, among the plurality of MOS type elements, an ONO film is used as the gate insulating film of the MOS type capacitor, and the thickness of the lower oxide film of the ONO film is set to 50 nm or less. In this way, by reducing the thickness of the lower oxide film of the ONO film that is easily affected by surface defects in the semiconductor region, it is possible to suppress deterioration of the breakdown lifetime with time due to accidental failure, and with high breakdown voltage and with time An ONO film on an SOI substrate having a long breakdown lifetime can be obtained.Since the thickness of the lower oxide film is set to be 25 nm or more, it is possible to obtain a MOS type capacitor having stable characteristics by reducing the variation in capacitance of the MOS type capacitor using the ONO film. This is due to the following reason. That is, in a MOS type element using an SOI substrate, attention is paid to the fact that when the lower oxide film of the ONO film is made thinner, the variation in capacitance of the MOS type capacitor due to the state of the silicon / oxide film interface becomes remarkable. is there.
[0015]
When a plurality of MOS capacitors are integrated, it is desirable to surround each MOS capacitor with a trench isolation layer. However, if the capacitance and size of the MOS capacitor are small, one capacitor surrounded by the trench isolation layer is used. A plurality of MOS capacitors may be arranged in the island region.
[0018]
Claim2According to the invention of claim1In the present invention, since the ONO film is set so that the thickness of the nitride film is 40 nm or more, in the structure using the ONO film on the SOI substrate, it has a high withstand voltage and deteriorates the breakdown life with time due to an accidental failure. Can be suppressed.
[0020]
Claim3According to the invention, in each of the above inventions, since the silicon substrate having a silicon semiconductor layer thickness of 10 μm or more is used as the SOI substrate, the film thickness of the silicon semiconductor layer easily affected by the bimetal effect inherent to the SOI substrate is obtained. A particularly remarkable effect can be obtained for a thick material, and a semiconductor device with a highly reliable gate insulating film can be provided.
[0021]
Claim4According to the present invention, in each of the above-described inventions, the surface impurity concentration of the diffusion region of the silicon semiconductor layer serving as the lower electrode of the MOS capacitor is 10.¹⁸atoms / cm^ThreeSince the setting is made as described above, it is possible to obtain a characteristic in which the voltage dependency of the capacitance is reduced in the MOS type capacitor.
[0022]
Claim5According to the invention, in the method of manufacturing a semiconductor device having a structure in which a plurality of MOS type elements are formed on an SOI substrate having a silicon semiconductor layer formed on a support substrate via a buried insulating film, As a step of providing a trench isolation layer for insulating and isolating at least a MOS capacitor formation region, a step of forming a groove with a depth reaching from the surface of the silicon semiconductor layer to the buried insulating film, and dry etching for forming the groove As a step of performing a treatment step and a treatment step of recovering or removing an etching damage layer generated by the dry etching treatment and filling the trench with a material having a thermal expansion coefficient different from that of the silicon semiconductor layer, the sidewall of the trench Forming an insulating layer in such a manner that the total thickness of the insulating layer is 1/3 or more of the width of the groove; Since the step of embedding polycrystalline silicon in the voids of the trench is performed, the trench isolation layer is formed without providing a special step, and the influence of the bimetal effect inherent to the SOI substrate is mitigated by the trench isolation layer. As a result, it is possible to effectively prevent the deterioration of the gate insulating film of the MOS type capacitor among the MOS type elements, and to improve the characteristics of the MOS type element.
  Also, at least in the step of forming the gate insulating film of the MOS capacitor among the MOS type elements, the ONO film is formed under the condition that the thickness of the lower oxide film is 50 nm or less.2Similarly to the above, the lower oxide film of the ONO film can be configured not to be affected by the surface defects of the semiconductor region, and the deterioration of the destruction lifetime with time due to the accidental failure can be suppressed.Since the lower oxide film is formed under the condition that the film thickness is 25 nm or more, as in the first aspect of the invention, the variation in capacitance of the MOS type capacitor using the ONO film is reduced and stable characteristics are obtained. This makes it possible to obtain a MOS type capacitor.
[0026]
Claim6According to the invention of claim5In the present invention, in the ONO film forming step, the nitride film is formed under the condition that the film thickness is 40 nm or more.2As in the case of the present invention, it is possible to secure a high withstand voltage and to suppress the deterioration of the destruction lifetime with time due to an accidental failure.
[0027]
Claim7According to the invention of claim5 or 6In this invention, since the upper oxide film of the ONO film is formed simultaneously with the gate insulating film of another MOS type element, the manufacturing process can be simplified and the cost can be reduced.
[0029]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment in which the present invention is applied to a semiconductor device in which a MOS capacitor, a CMOS, an LDMOS, and a bipolar transistor are integrated will be described with reference to FIGS. In the following description, two configuration examples will be described together with examples of three manufacturing steps.
[0030]
[Example of the first configuration]
1 and 2 are schematic cross-sectional views shown at each stage of the manufacturing process of the semiconductor device 12 using the SOI substrate 11. FIG. 2 (i) shows the integrated circuit 12 in a completed state. The semiconductor device 12 has a configuration in which a MOS capacitor 13, CMOSs 14a and 14b and LDMOS (Laterally Diffused MOS) 15 as a MOS type element are provided, and a bipolar transistor 16 is provided.
[0031]
In the SOI substrate 11, a buried oxide film 11b having a thickness of, for example, about 1.3 μm is formed on a silicon support substrate 11a, and first conductivity type silicon semiconductor layers 11c and 11d are formed in a single crystal. Is. In this case, the silicon semiconductor layer 11c is formed with a high impurity concentration, and the silicon semiconductor layer 11d is formed with a low impurity concentration. For example, a film having a thickness of about 16 μm is formed.
[0032]
Each of the MOS capacitor 13, CMOS 14a, 14b, LDMOS 15 and bipolar transistor 16 is formed in an electrically insulated state so as to be surrounded by a trench isolation layer 17 described later. The trench isolation layer 17 is composed of an oxide film 17a formed on the side wall of the trench and a polycrystalline silicon 17b filled in the central portion. LOCOS 18 for performing electrical element isolation is formed at various places on the surface portion where each element is formed.
[0033]
In the MOS capacitor 13, a buried first conductivity type layer 19 functioning as a lower layer electrode is formed in the silicon semiconductor layer 11d, a capacitor insulating layer 20 is formed on the surface thereof, and a polycrystalline silicon film is formed thereon. An upper layer electrode 21 is formed. Further, a first conductivity type high concentration region 22 is formed in order to be electrically connected to the buried first conductivity type layer 19.
[0034]
In the CMOSs 14a and 14b, a first conductivity type well 23 and a second conductivity type well 24 are respectively formed in the silicon semiconductor layer 11d, and a high concentration second conductivity type layer 25 is formed as a source / drain region in each of the wells 23 and 24. A high-concentration first conductivity type layer 26 is formed. A gate insulating film 27 is formed on the surface portion of the channel formation region, and a gate electrode 28 is formed thereon.
[0035]
In the LDMOS 15, a second conductivity type channel layer 29 is formed in the silicon semiconductor layer 11 d, which includes a high concentration first conductivity type layer 26 as a source region and a high concentration as a channel contact region. A second conductivity type layer 25 is formed. A gate insulating film 27 is formed on the surface portion of the channel formation region, and a gate electrode 30 is formed thereon.
[0036]
In the bipolar transistor 16, a high-concentration first conductivity type sink layer 31 diffused to reach the silicon semiconductor layer 11c is provided in the silicon semiconductor layer 11d, and further, a second conductivity type base region is formed in the silicon semiconductor layer 11d. 32 is formed. A first conductivity type emitter region 33 is formed inside the base region 32.
[0037]
[Example of first manufacturing process]
Next, a manufacturing process of the semiconductor device 12 having the above configuration will be described. As shown in FIG. 1A, in the SOI substrate 11, the high-concentration silicon semiconductor layer 11c and the low-concentration silicon semiconductor layer 11d are stacked on the support substrate 11a through the buried oxide film 11b as described above. Is. A mask material 34 for forming the trench is formed on the SOI substrate 11 and patterned so as to be separated into shapes corresponding to the respective regions of the MOS type element. Using this mask material 34 as an etching mask, a dry etching process is performed to form a groove 35 (see FIG. 5B). The groove 35 is for forming the trench isolation layer 17. Thereafter, annealing, sacrificial oxidation, wet etching, or a combination of these is performed as a processing step for recovering or removing the etching damage layer generated in the dry etching processing.
[0038]
Next, a thick oxide film 17a is formed on the side wall of the groove 35 (see FIG. 5C). The thick oxide film 17 a is formed so that the total film thickness becomes 1/3 or more of the width dimension of the groove 35. After this oxide film 17a is formed, the remaining gap is filled with polycrystalline silicon 17b. Thereafter, unnecessary mask material 34 is removed, and the substrate surface is planarized, thereby forming trench isolation layer 17 having a thermal expansion coefficient different from that of silicon semiconductor layer 11b (see FIG. 4D). ). After the trench isolation layer 17 is formed, the buried first conductivity type layer 19 and the high concentration first conductivity type sink layer 31 which are the lower layer electrodes of the MOS capacitor 13 are formed. Subsequently, the first conductivity type well 23, the second conductivity type well 24 of the CMOSs 14a and 14b, and the second conductivity type base region 32 of the bipolar transistor 16 are formed (see FIG. 4E).
[0039]
Thereafter, a LOCOS 18 for fine element isolation is formed at a predetermined portion of the surface. Subsequently, after performing a sacrificial oxidation process, the capacitor insulating layer 20 and the gate insulating film 27 are formed by thermal oxidation. The sacrificial oxidation treatment is a surface treatment for forming a high-quality element region (see FIG. 2F). Next, a polycrystalline silicon film is formed on the surface and patterned to form the upper electrode 21 of the MOS capacitor 13, the gate electrode 28 of the CMOSs 14a and 14b, and the gate electrode 30 of the LDMOS 15 (FIG. )reference).
[0040]
After forming various electrodes made of polycrystalline silicon, impurity implantation treatment and heat treatment are appropriately performed to form the first conductivity type emitter region 33 of the bipolar transistor 16 and the second conductivity type channel layer 29 of the LDMOS 15. (See FIG. 11H). Further, a second conductivity type high concentration layer 25 and a first conductivity type high concentration layer 26 are formed (see FIG. 5I). Thereafter, although not shown in the figure, the MOS capacitor 13, the CMOS 14a, 14b, the LDMOS 15 and the bipolar transistor 16 are integrally formed on the SOI substrate 11 by forming a metal wiring by forming a contact hole through a thick insulating layer. The formed semiconductor device 12 is obtained.
[0041]
[Example of second configuration]
Next, a configuration and manufacturing process when an ONO film is provided in the configuration of the above embodiment will be described with reference to FIGS. The difference from the above-described embodiment is that the ONO film is used as the gate insulating film, and the following description will focus on the different parts. Here, a case where the ONO film is applied as a capacitor insulating film of a MOS capacitor is shown.
[0042]
FIG. 4F corresponds to a cross-sectional view in the step of FIG. 2H described in the first embodiment. In this figure, a semiconductor device 36 is provided with a MOS capacitor 37 instead of the MOS capacitor 13 shown in the first embodiment. In the figure, an LDMOS 15 is shown as another MOS type element, and the CMOSs 14a and 14b and the bipolar transistor 16 are omitted.
[0043]
In this configuration, an ONO film 38 is provided as a capacitor insulating film of the MOS capacitor 37. The ONO film 38 includes a lower oxide film 38a, an intermediate silicon nitride film 38b, and an upper oxide film 38c. The lower oxide film 38a is formed under film forming conditions with a film thickness of 50 nm or less. The thickness of the lower oxide film 38a is more preferably 25 nm or more and 40 nm or less, more preferably 35 nm or less. Further, the intermediate silicon nitride film 38b is formed under the film forming conditions with a film thickness of 40 nm or more. The silicon nitride film 38b is more preferably formed under film forming conditions of 50 nm or more.
[0044]
Note that the lower layer electrode for forming the capacitor with the ONO film 38 interposed therebetween is the buried first conductivity type layer 19 formed in the silicon semiconductor layer 11d, but this impurity concentration is 1E18 (1 × 10¹⁸) Atoms / cm^ThreeIt is set to be above.
This is to reduce the voltage dependency of the capacitance, as will be described later.
[0045]
[Example of second manufacturing process]
In the above configuration, the process of forming the ONO film 38 is as follows. That is, the process shown in FIG. 3A is shown from the process following the process of FIG. 1E in the first embodiment, and this figure shows a state in which the LOCOS 18 is formed. From this state, after performing a sacrificial oxidation process for obtaining a good element region, a lower oxide film 38a of the ONO film 38 is formed by thermal oxidation (see FIG. 5B). As described above, the film thickness is 50 nm or less, preferably 40 nm or less, more desirably 35 nm or less, and 25 nm or more.
[0046]
Next, an intermediate silicon nitride film 38b is deposited and formed by LPCVD under film forming conditions of 40 nm or more, preferably 50 nm or more (see FIG. 3C), and finally an upper oxide film 38c is formed by thermal oxidation. (See FIG. 4 (d)). As a result, an ONO film 38 having a three-layer structure is formed. Thereafter, the ONO film 38 of the other part is removed while leaving the ONO film 38 of the MOS capacitor 37, and the gate insulating film 27 of another MOS type element (LDMOS 15 in the illustrated example) is formed by thermal oxidation (same as above). (Refer figure (e)).
[0047]
Thereafter, a gate electrode 30 is formed by depositing and processing polycrystalline silicon, another diffusion layer necessary for a composite semiconductor element is formed, a contact hole is formed through a thick insulating film, and metal wiring is performed. Thus, the semiconductor device 36 is formed. As a result, a semiconductor device 36 having a structure in which a MOS capacitor 37 having a high withstand voltage, no accidental failure, a sufficient aging failure life, and no voltage dependency is combined on the SOI substrate 11 can be obtained.
[0048]
[Example of third manufacturing process]
FIG. 5 shows an example in which a manufacturing process different from the second manufacturing process is adopted for the second configuration example. The difference from the second manufacturing process is the process of forming the ONO film 38. That is, in the example of the second manufacturing process, the LDMOS 15 and the gate insulating film 27 of another MOS type element are separately formed after forming the ONO film 38 up to the upper oxide film 38c. The place where they are formed simultaneously is different.
[0049]
In this embodiment, following the step shown in FIG. 3C in the example of the second manufacturing process, as shown in FIG. 5D, the lower oxide film 38a in the portion corresponding to the MOS capacitor 37, the intermediate oxide film 38a, The lower oxide film 38a and the nitride film 38b of other MOS type elements (such as LDMOS 15) that do not use the ONO film 38 as a gate insulating film are removed, leaving the silicon nitride film 38b.
[0050]
Thereafter, the upper oxide film 38c as the ONO film 38 and the gate insulating film 27 of the LDMOS 15 are simultaneously formed in the same thermal oxidation process (see FIG. 4E). Thereby, it becomes possible to simultaneously perform the processes performed separately in the second embodiment, and the process can be simplified.
[0051]
Next, characteristics of the semiconductor devices 12 and 36 adopting the above-described configuration and manufacturing process will be described with reference to the drawings while comparing with those of the conventional configuration.
[0052]
Whether the capacitor insulating film 20 or the gate insulating film 27 such as the MOS type elements 13, 14a, 14b, 15 formed on the SOI substrate 11 is a thermal oxide film or an ONO film (38), the above manufacturing is performed. The film quality of the gate insulating film deteriorates due to the bimetal effect inherent to the SOI substrate 11 generated during the heat treatment in the process. Among MOS type elements, a MOS capacitor having a large capacity that is built in especially for surge absorption is, for example, 1 mm.²As described above, the size is large, and it is easy to be influenced by the bimetal effect, and it is necessary to suppress deterioration of the gate insulating film quality. In addition, when a MOS type element represented by the LDMOS 15 is formed in combination, due to manufacturing restrictions such as the formation time of the diffusion layer, a thermal history due to a high-temperature heat treatment process is formed after the gate insulating film 27 is formed. The deterioration of the gate insulating film is further manifested by the bimetal effect inherent to the SOI substrate 11.
[0053]
Regarding the film quality deterioration of the gate insulating film due to the bimetal effect inherent to the SOI substrate 11, in order to measure the characteristics of the CMOS transistors CMOS14a, 14b, LDMOS15 and MOS capacitors 13, 37, a thermal oxide film is formed on the SOI substrate. A MOS capacitor (SOI-MOS capacitor) was formed as the gate insulating film. In addition, a comparison was made with a MOS capacitor (bulk MOS capacitor) when a similar composite semiconductor device was formed under the same conditions on a normal bulk silicon substrate.
[0054]
The surface impurity concentration of the diffusion region as the lower electrode is 1E19 (1 × 10¹⁹) Atoms / cm^ThreeAnd a thermal oxide film is used as a gate insulating film thereon, and the gate area is 1.00 mm.²A number of MOS capacitor samples were prepared, and their breakdown voltage distributions were measured. FIG. 6A is a histogram showing a breakdown voltage distribution when the MOS type capacitor is formed on a bulk silicon substrate. Further, FIG. 6B shows the breakdown voltage distribution of the MOS type capacitor when elements having the same structure are formed on the SOI substrate by the same manufacturing method.
[0055]
6A and 6B, even if the MOS capacitor having the same structure formed by the same manufacturing method is formed on the SOI substrate, the gate insulating film of the MOS capacitor can be insulated. The breakdown voltage is lower than that formed on the bulk silicon substrate due to the bimetal effect inherent to the SOI substrate, and many B-mode defects occur. In order to reduce the voltage dependency of the capacitance in the MOS capacitor, the occurrence of this B-mode failure is caused by a high surface concentration (1E18 atoms / cm as the lower layer electrode).^ThreeThis is more noticeable when a diffusion layer doped with impurities is used.
[0056]
Therefore, in the above first configuration example, prior to forming the various MOS type elements 13, 14a, 14b, 15 and the like on the SOI substrate 11, the silicon semiconductor layers 11c, 11d forming the semiconductor elements are formed on the silicon substrate layers 11c, 11d. A trench 35 reaching the buried oxide film 11b is formed, a thick oxide film 17a is formed in the trench as a material having a different thermal expansion coefficient from the silicon semiconductor layers 11c and 11d, and the remaining void is filled with the polycrystalline silicon 17b. Since the trench isolation layer 17 is formed, the bimetal effect inherent to the SOI substrate 11 can be mitigated by the trench isolation layer, and the film quality of the oxide film formed on the surface of the silicon semiconductor layer 11d is attributed to the bimetal effect. It can suppress that it deteriorates.
[0057]
For example, in the above-described case, the groove 35 has a width of 2 μm, and a one-side film thickness of about 0.5 μm is formed on the side surface of the groove to form a 1 μm thick oxide film 17a. A buried trench isolation layer 17 is formed. The thickness of the thick oxide film 17a is 1/3 or more with respect to the width of the groove 35 of 2 μm, and the trench isolation layer 17 having a thermal expansion coefficient different from that of the silicon semiconductor layers 11c and 11d is formed.
[0058]
FIG. 6C shows the breakdown voltage distribution in the case where the trench isolation layer 17 is formed so as to surround the formation region of the MOS capacitor having the same structure as that shown in FIGS. 6A and 6B. . As is apparent from this result, in the first configuration example in which the trench isolation layer 17 is formed, the deterioration of the gate insulating film 20 due to the bimetal effect inherent in the SOI substrate 11 generated during the heat treatment is suppressed. Compared to the configuration shown in FIG. 6B, it is possible to significantly suppress the occurrence of intermediate breakdown voltage failure (B mode failure) and improve the breakdown voltage.
[0059]
When a plurality of MOS capacitors are integrated, it is desirable to surround each MOS capacitor with a trench isolation layer. However, if the capacitance and size of the MOS capacitor are small, it is not necessary to individually set the trench isolation layer, and a plurality of MOS capacitors may be arranged in one island region surrounded by the trench isolation layer. Good.
[0060]
If an ONO film is used as the gate insulating film in the MOS capacitor structure (MOS type capacitor formed on the SOI substrate) in the case of FIG. 6B, the B mode failure is suppressed as shown in FIG. Distribution improves. Further, if an ONO film is used as the gate insulating film in the MOS capacitor structure (MOS type capacitor on the SOI substrate surrounded by the trench isolation layer) in the case of FIG. 6C, the occurrence of B-mode defects is further suppressed. This improves the breakdown voltage distribution. However, by using ONO 38 with the lower oxide film thickness and nitride film thickness adjusted as in the second configuration example, it is possible to effectively suppress the deterioration of the breakdown lifetime with time due to accidental failure for the first time. There was found.
[0061]
When comparing a thermal oxide film obtained by thermally oxidizing the surface of a silicon semiconductor layer of an SOI substrate with a thermal oxide film obtained by thermally oxidizing the surface of a normal bulk silicon substrate, the above-mentioned bimetallic effect is obtained in the case of an SOI substrate. In addition, the surface thermal oxide film is affected by defects on the semiconductor surface due to the fact that the surface region defects cannot be effectively gettered due to the presence of the buried insulating film, and traps in the thermal oxide film are also bulky. It is estimated that the size and the generation rate are larger than the thermal oxide film on silicon.
[0062]
According to the second configuration example, when the ONO film is used as the gate insulating film, the lower oxide film thickness and the nitride film thickness are adjusted, and the lower layer of the ONO film 38 that is most affected by the surface of the SOI substrate. The thickness of the oxide film 38a is reduced, so that the influence of traps in the thermal oxide film can be suppressed and deterioration of the destruction life with time due to accidental failure can be suppressed. In addition to this, the thickness of the silicon nitride film 38b constituting the intermediate layer of the ONO film 38 is optimally set to 40 nm or more, preferably 50 nm or more, so that a high withstand voltage is ensured and the aging breakdown life due to accidental failure is ensured. It is possible to obtain the ONO film 38 having a long fracture life over time by further suppressing deterioration of the film. That is, by depositing the silicon nitride film 38b of the ONO film 38 to a thickness of 40 nm or more, preferably 50 nm or more, the traps present in the lower oxide film 38a of the ONO film 38 during the deposition of the nitride film are hydrogen (H). Therefore, it is estimated that the deterioration of the destruction life with time due to the accidental failure can be further suppressed.
[0063]
As a result of measuring the constant current TDDB characteristics of the MOS capacitor in which the ONO film is applied to the MOS capacitor in the case of FIG. 6C, the film thickness dependence of the lower oxide film 38a is as shown in FIG. When the thickness of the lower oxide film 38a is as thick as 56 nm, accidental failures due to traps in the oxide film frequently occur. If this behavior is arranged by the breakdown total charge amount 50% Qbd when the cumulative failure rate is 50%, as shown in FIG. 8, 50% Qbd tends to deteriorate as the thickness of the lower oxide film 38a of the ONO film 38 increases. I found out that
[0064]
For this reason, by forming the ONO film 38 of the lower oxide film 38a having a film thickness of 50 nm or less, preferably 40 nm or less and more desirably 35 nm or less on the SOI substrate 11, the MOS type semiconductor element is prevented from accidental failure, and is destroyed over time. A MOS type element having a long lifetime can be obtained. The upper limit value of the lower oxide film may be set according to acceptable conditions, for example, 50% Qbd is 30 C / cm.²If the above is set as an allowable condition, the target upper limit value of the lower oxide film is 40 nm.
[0065]
Further, as shown in FIG. 9, as the lower oxide film 38a of the ONO film 38 becomes thinner, the capacitance of the MOS capacitor 37 on the SOI substrate 11 using the ONO film 38 depends on the state of the silicon / oxide film interface. Variation increases. Accordingly, when the allowable condition for capacitance variation is, for example, 5 to 6% or less, it is desirable that the thickness of the lower oxide film 38a of the ONO film 38 used for the MOS type element on the SOI substrate 11 is set to 25 nm or more. Become.
[0066]
Furthermore, regarding the film thickness of the silicon nitride film 38b, which is an intermediate layer of the ONO film 38, the gate area formed on the SOI substrate 11 is 1.0 mm as in the case of the lower oxide film 38a.²The result of measuring the constant current TDDB of the MOS capacitor 37 is shown in FIG. FIG. 11 shows the relationship between the thickness of the silicon nitride film 38b in the ONO film 38 and 50% Qbd. As is apparent from FIGS. 10 and 11, when the thickness of the silicon nitride film 38b, which is an intermediate layer of the ONO film 38 formed on the SOI substrate 11, is as thin as 30 nm, accidental failures frequently occur. Therefore, it is desirable to increase the thickness of the silicon nitride film 38b, which is an intermediate layer of the ONO film 38 formed on the SOI substrate 11. The film thickness of the silicon nitride film 38b may be set according to acceptable conditions. For example, 50% Qbd is 30 C / cm.²When the above is set as an allowable condition, it is desirable that the film thickness is 40 nm or more, preferably 50 nm or more.
[0067]
FIG. 12 shows the result of summarizing the optimum requirements for the thickness of the lower oxide film 38a and the thickness of the silicon nitride film 38b in the ONO film 38 described above. By depositing an ONO film under the film thickness conditions in the high-quality guaranteed region of FIG. 12, an ONO film having a high withstand voltage and a long breakdown life can be obtained even when formed on an SOI substrate. A highly reliable gate insulating film of the device can be obtained.
[0068]
In particular, a semiconductor device with high gate reliability can be obtained in a semiconductor device in which a silicon semiconductor layer (total thickness of the silicon semiconductor layers 11c and 11d) is 10 μm or more as an SOI substrate.
[0069]
In FIG. 12, as an example of the ONO film in the high quality assurance region, a large number of samples of SOI structure MOS type semiconductor devices having a lower oxide film of 35 nm, a silicon nitride film of 55 nm, and an upper oxide film of 2 nm are manufactured, and a constant voltage TDDB is produced in an atmosphere of 150 ° C. Was measured. The voltage application conditions were 8.3 MV / cm, 8.5 MV / cm, and 9.0 MV / cm in terms of electric field strength. The measurement results are shown in FIG. Further, FIG. 14 shows the results organized by the relationship between the lifetime until the cumulative failure rate reaches 1.0% and 2.5 ppm and the applied electric field strength.
[0070]
As is apparent from FIGS. 13 and 14, unlike the case of FIG. 19, by using the ONO film in the high-quality guaranteed region, the MOS type semiconductor element is suppressed from accidental failure and a MOS type element having a long breakdown life is obtained. be able to. Further, for example, a life of 19 years or longer can be realized under a 24V application condition.
[0071]
Further, as the semiconductor device 36 using the SOI substrate 11 in the second configuration example described above, the gate area is 1.0 mm.²FIG. 15 shows the evaluation results of the yield (insulation breakdown voltage yield) with respect to the intrinsic breakdown voltage value in the IV characteristic measurement of the MOS capacitor 37 and the yield (TDDB yield) that causes wear failure in the TDDB measurement.
[0072]
In FIG. 15, as the SOI substrate 11 provided with the trench isolation layer 17 in the present embodiment, the surface concentration of impurities as the lower electrode 19 in the silicon semiconductor layers 11 c and 11 d is 1E19 (1 × 10¹⁹) Atoms / cm^ThreeA high-concentration buried diffusion layer 19 is formed, and a MOS capacitor 37 formed as a gate insulating film by an ONO film 38 on the buried diffusion layer 19 is used, which is denoted as DeepN / SOI in the drawing. Yes. In contrast, an ideal MOS capacitor having a configuration in which an ONO film formed under the same conditions as a gate insulating film on a bulk silicon substrate is used as a MOS type capacitor to be compared.^-/ Bulk.
[0073]
As is clear from this result, the characteristics of both are almost the same, and even with the Deep N / SOI semiconductor device 36 of this embodiment produced under severe conditions, either the withstand voltage yield or the TDDB yield N is expected to produce the best results^-/ Yield characteristics that are comparable to those of Bulk and comparable to those of Bulk.
[0074]
In other words, by applying the configuration and the manufacturing method of the present embodiment, it is possible to obtain the gate insulating films 20 and 27 and the ONO film 38 having good characteristics that are hardly adversely affected by the SOI substrate 11. As a result, the dielectric breakdown yield and the TDDB yield equivalent to the case of using the bulk silicon substrate can be ensured while fully taking advantage of the electrical characteristics by using the SOI substrate 11.
[0075]
(Other embodiments)
The present invention is not limited to the above embodiment, and can be modified or expanded as follows.
[0076]
As the trench isolation layer having a thermal expansion coefficient different from that of the silicon semiconductor layer, a single material may be used in addition to the thick oxide film 17a and the polycrystalline silicon 17b formed in the groove 35, and various types may be used. These materials may be formed in a composite manner, and further, in addition to those formed by embedding trenches, those having a trench isolation layer already embedded and formed as an SOI substrate may be used.
[0077]
The ONO film 38 has been described as applied to the MOS capacitor 37. However, the ONO film 38 can also be applied as a gate insulating film in other MOS type elements such as CMOSs 14a and 14b and LDMOS 15, thereby improving the gate reliability. It becomes possible to plan more.
[0078]
Even if the total thickness dimension of the silicon semiconductor layers 11c and 11d is 10 μm or less, the SOI substrate 11 can be applied to this embodiment.
[0079]
The MOS type element has been described as having a structure using the MOS capacitor 13, CMOS 14a, 14b, LDMOS 15 and the like. However, as long as these elements are integrated or integrated in combination, all kinds of elements can be combined. It can be applied without. Further, the present invention can be applied to all semiconductor devices including a manufacturing process in which heat treatment is performed after forming a gate insulating film.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view (No. 1) corresponding to each stage of a manufacturing process of a semiconductor device having a first structure showing an embodiment of the present invention;
FIG. 2 is a schematic cross-sectional view (part 2) corresponding to each stage of the manufacturing process of the semiconductor device having the first structure;
FIG. 3 is a schematic cross-sectional view (No. 1) corresponding to each step of a manufacturing process of a semiconductor device having a second structure;
FIG. 4 is a schematic cross-sectional view (No. 2) corresponding to each stage of a manufacturing process of a semiconductor device having a second structure;
FIG. 5 is a view corresponding to FIG. 4 corresponding to a different manufacturing process of the semiconductor device having the second structure;
FIGS. 6A to 6C are diagrams showing distribution of dielectric strength of MOS capacitors manufactured on a bulk silicon substrate, an SOI substrate without a trench isolation layer, and an SOI substrate with a trench isolation layer, respectively.
FIG. 7 is a graph showing the dependence of constant current TDDB characteristics of a MOS capacitor on the lower oxide thickness.
FIG. 8 is a characteristic diagram showing the dependency of the total breakdown charge amount of the ONO film on the lower oxide film thickness.
FIG. 9 is a characteristic diagram showing uniformity of capacitance of MOS capacitors.
FIG. 10 is a diagram showing the nitride film thickness dependence of constant current TDDB characteristics of a MOS capacitor.
FIG. 11 is a characteristic diagram showing the nitride film thickness dependence of the total breakdown charge amount of the ONO film.
FIG. 12 is a diagram showing optimum conditions for each thickness of the lower oxide film and the nitride film of the ONO film.
FIG. 13 is a diagram showing the applied electric field strength dependence of constant voltage TDDB characteristics of a MOS capacitor.
FIG. 14 is a view showing a film life evaluation result of a MOS capacitor.
FIG. 15 is a diagram showing the breakdown voltage yield and the TDDB yield values of the embodiment and those formed of bulk silicon.
FIG. 16 is a schematic cross-sectional view of an SOI structure MOS capacitor;
17 is an IV characteristic diagram of a MOS capacitor formed on an SOI substrate using an oxide film as a gate insulating film. FIG.
FIG. 18 is an IV characteristic diagram of a MOS capacitor formed on an SOI substrate using an ONO film as a gate insulating film.
FIG. 19 shows a constant voltage TDDB characteristic of a MOS capacitor formed on an SOI substrate using an ONO film as a gate insulating film.
[Explanation of symbols]
11 SOI substrate
11a Support substrate
11b buried oxide film
11c, 11d silicon semiconductor layer
12, 36 Semiconductor device
13, 37 MOS capacitor (MOS type element, MOS type capacitor)
14a, 14b CMOS (MOS type element)
15 LDMOS (MOS type device)
16 Bipolar transistor
17 Trench isolation layer
17a Thick oxide film
17b polycrystalline silicon
18 LOCOS
20 Capacitor insulation film
21 Upper layer electrode
27 Gate insulation film
35 groove
38 ONO film
38a Underlayer oxide film
38b Silicon nitride film
38c Upper layer oxide film

Claims (9)

In a semiconductor device having a structure in which a plurality of MOS-type elements are formed on an SOI (Silicon on Insulator) substrate in which a silicon semiconductor layer is formed on a support substrate via a buried insulating film,
At least a MOS capacitor forming region of the MOS type element reaches the buried insulating film and is insulated and separated by a trench isolation layer having a thermal expansion coefficient different from that of the silicon semiconductor layer.
The trench isolation layer is composed of an insulating layer formed on the side surface of the groove and polycrystalline silicon,
The total thickness dimension of the insulating layer is set to 1/3 or more of the width dimension of the groove,
A semiconductor device characterized in that an ONO (Oxide Nitride Oxide) film is used as a gate insulating film of a MOS capacitor, and a thickness of a lower oxide film of the ONO film is set to 25 nm or more and 50 nm or less. The semiconductor device according to claim 1 ,
The ONO film has a nitride film thickness set to 40 nm or more. The semiconductor device according to claim 1 or 2 ,
The SOI substrate has a silicon semiconductor layer having a thickness of 10 μm or more. The semiconductor device according to claims 1 to 3,
A semiconductor device characterized in that the surface impurity concentration of the diffusion region of the silicon semiconductor layer constituting the lower electrode of the MOS capacitor is set to 10 ¹⁸ atoms / cm ³ or more. In a method for manufacturing a semiconductor device having a structure in which a plurality of MOS elements are formed on an SOI substrate in which a silicon semiconductor layer is formed on a support substrate via a buried insulating film,
Forming a trench at a depth reaching from the surface of the silicon semiconductor layer to the buried insulating film as a step of providing a trench isolation layer for insulatingly isolating at least a MOS capacitor formation region of the MOS type element;
As the step of forming the groove, a dry etching treatment step for groove formation, a treatment step of recovering or removing the etching damage layer generated by the dry etching treatment,
As a step of filling the inside of the groove with a material having a thermal expansion coefficient different from that of the silicon semiconductor layer, an insulating layer is formed on the side wall of the groove so that the total thickness becomes 1/3 or more of the width of the groove. An insulating layer forming step to be formed on, and a step of embedding polycrystalline silicon in the gap in the groove ,
In the step of forming the gate insulating film of the MOS capacitor, the ONO film is formed under the condition that the thickness of the lower oxide film is 25 nm or more and 50 nm or less. In the manufacturing method of the semiconductor device according to claim 5 ,
In the ONO film formation step, the ONO film is formed under the condition that the nitride film has a thickness of 40 nm or more. In the manufacturing method of the semiconductor device according to claim 5 or 6 ,
A method of manufacturing a semiconductor device, wherein an upper oxide film of the ONO film is formed simultaneously with a gate insulating film of another MOS type element. In the manufacturing method of the semiconductor device in any one of Claims 5 thru | or 7 ,
A method for manufacturing a semiconductor device, wherein the method is applied to a silicon semiconductor layer having a thickness of 10 μm or more on the SOI substrate. In the manufacturing method of the semiconductor device in any one of Claims 5 thru | or 8 ,
A method of manufacturing a semiconductor device, comprising forming a diffusion region in the silicon semiconductor layer as a lower electrode of the MOS capacitor under a condition that a surface impurity concentration is 10 ¹⁸ atoms / cm ³ or more.

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