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JP4600082B2 - Multilayer composite electronic components - Google Patents
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JP4600082B2 - Multilayer composite electronic components - Google Patents

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JP4600082B2
JP4600082B2 JP2005049108A JP2005049108A JP4600082B2 JP 4600082 B2 JP4600082 B2 JP 4600082B2 JP 2005049108 A JP2005049108 A JP 2005049108A JP 2005049108 A JP2005049108 A JP 2005049108A JP 4600082 B2 JP4600082 B2 JP 4600082B2
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capacitor
curing
electrode
carbon
composite electronic
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JP2006237234A (en
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研次郎 羽田野
重克 山本
隆司 澤田
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Murata Manufacturing Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/40Structural combinations of fixed capacitors with other electric elements, the structure mainly consisting of a capacitor, e.g. RC combinations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/002Details
    • H01G4/018Dielectrics
    • H01G4/06Solid dielectrics
    • H01G4/08Inorganic dielectrics
    • H01G4/12Ceramic dielectrics

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  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Ceramic Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Description

本発明は、積層型複合電子部品、特に、ノイズフィルタなどに用いられる積層型複合電子部品に関する。   The present invention relates to a multilayer composite electronic component, and more particularly to a multilayer composite electronic component used for a noise filter or the like.

ICの電源ラインでは、一般的にグランドとの間にバイパスコンデンサを接続することによりノイズを除去している。ところで、高密度実装するために略全面が電源電極パターンやグランド電極パターンで覆われたプリント基板を用いた場合、電源とグランド間で共振現象が発生する。共振現象が発生すると、放射ノイズが発生するため、共振現象を抑制する必要がある。   In the power supply line of an IC, noise is generally removed by connecting a bypass capacitor to the ground. By the way, when a printed circuit board having a substantially entire surface covered with a power electrode pattern or a ground electrode pattern is used for high-density mounting, a resonance phenomenon occurs between the power source and the ground. When a resonance phenomenon occurs, radiation noise is generated, and therefore it is necessary to suppress the resonance phenomenon.

ところが、等価直列抵抗(ESR)が数mΩと小さい積層セラミックコンデンサをバイパスコンデンサとして用いると、自己共振周波数が1〜100MHz程度であるため、この周波数帯のインピーダンスが小さくなる。この結果、1〜100MHz帯で発生する前記共振現象を抑えることができない。   However, when a multilayer ceramic capacitor having a small equivalent series resistance (ESR) of several mΩ is used as a bypass capacitor, the self-resonant frequency is about 1 to 100 MHz, and the impedance in this frequency band is reduced. As a result, the resonance phenomenon occurring in the 1 to 100 MHz band cannot be suppressed.

一般的な対策として、積層セラミックコンデンサに対して直列に抵抗を接続すれば、共振現象を抑制できることが知られている。このため、特許文献1に記載するような積層セラミックコンデンサが提案されている。このコンデンサは、外部電極が抵抗膜を介してコンデンサ電極と導通させることによって、部品内に主コンデンサと抵抗が直列接続した回路を構成している。   As a general measure, it is known that a resonance phenomenon can be suppressed by connecting a resistor in series to a multilayer ceramic capacitor. For this reason, a multilayer ceramic capacitor as described in Patent Document 1 has been proposed. This capacitor constitutes a circuit in which a main capacitor and a resistor are connected in series in a component by allowing the external electrode to conduct with the capacitor electrode through a resistance film.

しかしながら、抵抗は周波数に関係なく一定のインピーダンスをもつため、単に抵抗を直列に接続しただけでは、積層セラミックコンデンサの自己共振周波数から離れた周波数帯でのノイズ除去効果が損なわれるという問題点を有していた。
実開昭62−184728号公報
However, since the resistor has a constant impedance regardless of the frequency, simply connecting the resistors in series impairs the noise removal effect in a frequency band away from the self-resonant frequency of the multilayer ceramic capacitor. Was.
Japanese Utility Model Publication No. 62-184728

そこで、本発明の目的は、共振現象の発生し易い1〜100MHz帯域で高インピーダンスであり、ノイズ成分の高周波帯域(100MHz以上)で低インピーダンスである積層型複合電子部品を提供することにある。   SUMMARY OF THE INVENTION An object of the present invention is to provide a multilayer composite electronic component having a high impedance in the 1 to 100 MHz band in which a resonance phenomenon is likely to occur and a low impedance in a high frequency band (100 MHz or higher) of noise components.

前記目的を達成するため、本発明に係る積層型複合電子部品は、複数のセラミック層を積み重ねて構成した積層体と、積層体に内蔵された複数のコンデンサ電極にて構成された主コンデンサと、積層体の端部に形成され、かつコンデンサ電極と電気的に接続する複数の外部電極とを有する積層型複合電子部品において、外部電極の少なくとも一つが誘電性抵抗膜を介してコンデンサ電極と電気的に接続し、外部電極とコンデンサ電極との間に、誘電性抵抗膜によるRC並列回路を形成して、主コンデンサとRC並列回路を電気的に直列接続し、積層型複合電子部品が3端子貫通コンデンサであり、コンデンサ電極は信号用貫通電極とグランド用貫通電極とで構成され、誘電性抵抗膜は前記グランド用貫通電極に接続され、誘電性抵抗膜はカーボン粉末と有機樹脂とを含むカーボン抵抗膜であり、カーボン抵抗膜は、硬化後の膜厚が0.01mm以上0.03mm未満のときは、硬化後のカーボン含有率が4〜15体積%になるように設定され、硬化後の膜厚が0.03mm以上0.05mm未満のときは、硬化後のカーボン含有率が6〜15体積%になるように設定され、硬化後の膜厚が0.05mm以上0.08mm未満のときは、硬化後のカーボン含有率が8〜15体積%になるように設定され、硬化後の膜厚が0.08mm以上0.10mm以下のときは、硬化後のカーボン含有率が10〜15体積%になるように設定されていること、を特徴とする。誘電性抵抗膜とコンデンサ電極の間にさらに下地電極が配設されていてもよい。 In order to achieve the above object, a multilayer composite electronic component according to the present invention includes a multilayer body configured by stacking a plurality of ceramic layers, a main capacitor configured by a plurality of capacitor electrodes built in the multilayer body, In a multilayer composite electronic component formed at an end of a multilayer body and having a plurality of external electrodes electrically connected to the capacitor electrode, at least one of the external electrodes is electrically connected to the capacitor electrode through a dielectric resistance film. Is formed, and an RC parallel circuit is formed by a dielectric resistance film between the external electrode and the capacitor electrode, the main capacitor and the RC parallel circuit are electrically connected in series, and the multilayer composite electronic component penetrates through three terminals. a capacitor, the capacitor electrode is composed of a signal through electrodes and the ground through-electrode, the dielectric resistance film is connected to the through electrode the ground, dielectric resistance film car When the film thickness after curing is 0.01 mm or more and less than 0.03 mm, the carbon content after curing is 4 to 15% by volume. When the film thickness after curing is 0.03 mm or more and less than 0.05 mm, the carbon content after curing is set to 6 to 15% by volume, and the film thickness after curing is 0. When the thickness is 0.05 mm or more and less than 0.08 mm, the carbon content after curing is set to 8 to 15% by volume. When the thickness after curing is 0.08 mm or more and 0.10 mm or less, after curing The carbon content of is set to be 10 to 15% by volume . A base electrode may be further disposed between the dielectric resistance film and the capacitor electrode.

本発明によれば、外部電極とコンデンサ電極との間に、誘電性抵抗膜によるRC並列回路を形成して、主コンデンサとRC並列回路を電気的に直列接続したので、周波数が比較的低い帯域(100MHz未満)では、主コンデンサと抵抗の直列回路として機能する。この回路では、主コンデンサによる電圧変動抑制効果と、抵抗による共振抑制効果が認められる。そのため、電源ラインでの電圧変動を抑えるとともに、電源ラインとグランド間の共振現象を抑制することができる。   According to the present invention, since the RC parallel circuit by the dielectric resistance film is formed between the external electrode and the capacitor electrode, and the main capacitor and the RC parallel circuit are electrically connected in series, the frequency band is relatively low. (Under 100 MHz) functions as a series circuit of a main capacitor and a resistor. In this circuit, a voltage fluctuation suppressing effect by the main capacitor and a resonance suppressing effect by the resistance are recognized. Therefore, it is possible to suppress voltage fluctuations in the power supply line and to suppress a resonance phenomenon between the power supply line and the ground.

一方、周波数が比較的高い帯域(100MHz未満)では、RC並列回路のコンデンサのインピーダンスが下がるので、コンデンサ単体に近い特性となり、信号ラインの高調波等が伝播して入った高周波ノイズを効果的に除去することができる。この効果は、残留直列インダクタンスが小さい積層複合電子部品ほど、より高周波帯まで発現するので、3端子貫通コンデンサには有利である。   On the other hand, in the relatively high frequency band (less than 100 MHz), the impedance of the capacitor of the RC parallel circuit is lowered, so that the characteristics are close to those of the capacitor alone, and the high-frequency noise that has propagated through the propagation of the harmonics of the signal line is effectively reduced. Can be removed. This effect is more advantageous for a three-terminal feedthrough capacitor because the multilayer composite electronic component having a smaller residual series inductance is manifested to a higher frequency band.

以下に、本発明に係る積層型複合電子部品の実施例について添付図面を参照して説明する。   Embodiments of a multilayer composite electronic component according to the present invention will be described below with reference to the accompanying drawings.

(第1実施例、図1〜図9)
図1に示すように、3端子積層セラミックコンデンサ1は、信号用貫通電極3とグランド用貫通電極4をそれぞれ設けたセラミックグリーンシート2と、予め導体パターンを設けない外層用セラミックグリーンシート2等で構成されている。
(First embodiment, FIGS. 1 to 9)
As shown in FIG. 1, a three-terminal multilayer ceramic capacitor 1 is composed of a ceramic green sheet 2 provided with a signal through electrode 3 and a ground through electrode 4 respectively, and an outer layer ceramic green sheet 2 provided with no conductor pattern in advance. It is configured.

セラミックグリーンシート2は、チタン酸バリウムなどを主成分とする誘電体の原料粉末を溶剤に分散させてセラミックスラリを調整し、これをドクターブレード法によりシート状に成形することにより得る。   The ceramic green sheet 2 is obtained by adjusting a ceramic slurry by dispersing a dielectric raw material powder mainly composed of barium titanate or the like in a solvent, and forming the ceramic slurry into a sheet shape by a doctor blade method.

次に、セラミックグリーンシート2のそれぞれにニッケルなどを主成分とする導電ペーストをスクリーン印刷法によって塗布、印刷して貫通電極3,4を形成する。信号用貫通電極3はシート2の上面に広面積に設けられ、その引出し部3aがシート2の左右の辺に露出している。同様に、グランド用貫通電極4はシート2の上面に広面積に設けられ、その引出し部4aがシート2の手前側及び奥側の辺に露出している。   Next, a conductive paste mainly composed of nickel or the like is applied and printed on each ceramic green sheet 2 by screen printing to form the through electrodes 3 and 4. The signal through electrode 3 is provided in a large area on the upper surface of the sheet 2, and the lead-out portion 3 a is exposed on the left and right sides of the sheet 2. Similarly, the ground penetrating electrode 4 is provided in a large area on the upper surface of the sheet 2, and the lead-out portion 4 a is exposed on the near side and the far side of the sheet 2.

各セラミックグリーンシート2は貫通電極3,4が交互になるように積み重ねられ、さらに、上下に外層用セラミックグリーンシート2が配置された後、圧着して積層体ブロックとする。積層体ブロックは所定のサイズにカットされた後、一体的に焼成される。これにより、図2に示す積層体10とされる。   The ceramic green sheets 2 are stacked so that the through electrodes 3 and 4 are alternately arranged. Further, after the ceramic green sheets 2 for the outer layer are arranged on the upper and lower sides, they are pressure-bonded to form a laminated body block. The laminated body block is cut into a predetermined size and then fired integrally. Thereby, the laminated body 10 shown in FIG. 2 is obtained.

次に、図3に示すように、積層体10の両側面に露出した信号用貫通電極3の引出し部3aをそれぞれ覆う下地電極11a,11bを形成する。下地電極11a,11bは銅を主成分とする導電ペーストを帯状に塗布し、焼き付けすることにより形成される。   Next, as shown in FIG. 3, base electrodes 11 a and 11 b that respectively cover the lead portions 3 a of the signal through electrode 3 exposed on both side surfaces of the multilayer body 10 are formed. The base electrodes 11a and 11b are formed by applying and baking a conductive paste mainly composed of copper in a band shape.

次に、図4に示すように、積層体10の両端面に露出したグランド用貫通電極4の引出し部4aをそれぞれ覆うカーボン抵抗膜(誘電性抵抗膜)12a,12bを形成する。カーボン抵抗膜12a,12bはカーボン粉末と有機樹脂(フェノール樹脂)などからなる熱硬化性のカーボン抵抗ペーストを塗布し、硬化させることにより形成される。   Next, as shown in FIG. 4, carbon resistance films (dielectric resistance films) 12 a and 12 b are formed to cover the lead portions 4 a of the ground through electrodes 4 exposed on both end faces of the laminate 10. The carbon resistance films 12a and 12b are formed by applying and curing a thermosetting carbon resistance paste made of carbon powder and organic resin (phenol resin).

その後、図5に示すように、下地電極11a,11b及びカーボン抵抗膜12a,12bの上に、通常の電解めっきでニッケル、錫の順でめっき膜15を形成して、信号用外部電極21a,21b及びグランド用外部電極G1,G2とする。   Thereafter, as shown in FIG. 5, a plating film 15 is formed on the base electrodes 11a and 11b and the carbon resistance films 12a and 12b in the order of nickel and tin by ordinary electrolytic plating, and the signal external electrodes 21a, 21b and ground external electrodes G1 and G2.

なお、カーボン抵抗膜12a,12bの上に電解めっきが付きにくい場合は、カーボン抵抗膜12a,12bの表面を粗面化したり、カーボン抵抗膜12a,12bの表面の化学状態を変化させてめっき付き性を向上させる。あるいは、カーボン抵抗ペーストの表面に導電ペーストを塗布する方法、カーボン抵抗ペーストの表面に金属粉などを付着させる方法を採用してもよい。また、カーボン抵抗膜12a,12bの下に下地電極を形成して、カーボン抵抗膜12a,12bとグランド用貫通電極4の間に下地電極を配設してもよい。これにより、カーボン抵抗膜12a,12bによるコンデンサが形成され易くなり、RC並列回路の容量の微調整が可能になる。   In addition, when it is difficult to attach electrolytic plating on the carbon resistance films 12a and 12b, the surface of the carbon resistance films 12a and 12b is roughened, or the chemical state of the surfaces of the carbon resistance films 12a and 12b is changed. Improve sexiness. Alternatively, a method of applying a conductive paste to the surface of the carbon resistance paste, or a method of attaching metal powder or the like to the surface of the carbon resistance paste may be employed. Alternatively, a base electrode may be formed under the carbon resistance films 12a and 12b, and the base electrode may be disposed between the carbon resistance films 12a and 12b and the ground through electrode 4. As a result, a capacitor is easily formed by the carbon resistance films 12a and 12b, and the capacitance of the RC parallel circuit can be finely adjusted.

信号用外部電極21a,21bはそれぞれ、信号用貫通電極3の一方の引出し部3a及び他方の引出し部3aに電気的に接続されている。グランド用外部電極G1,G2はそれぞれ、カーボン抵抗膜12a,12bを介してグランド用貫通電極4の一方の引出し部4a及び他方の引出し部4aに電気的に接続されている。   The signal external electrodes 21 a and 21 b are electrically connected to one lead portion 3 a and the other lead portion 3 a of the signal through electrode 3, respectively. The ground external electrodes G1 and G2 are electrically connected to one lead portion 4a and the other lead portion 4a of the ground through electrode 4 via carbon resistance films 12a and 12b, respectively.

なお、カーボン抵抗膜(誘電性抵抗膜)に用いる有機樹脂は、本第1実施例や以下に説明する第2実施例で用いた熱硬化性フェノール樹脂(比誘電率5〜8)に限らず、例えば、エポキシ樹脂(比誘電率4〜4.5)などの熱硬化性樹脂を用いることができる。有機樹脂の比誘電率は10以下と小さく、樹脂自体の比誘電率だけで誘電性抵抗幕に必要な比誘電率を得ることは難しい。有機樹脂中にカーボン粒子が均一に分散し、カーボン粒子間の微少な隙間に有機樹脂が入ることで、高い比誘電率を得ることができる。   The organic resin used for the carbon resistance film (dielectric resistance film) is not limited to the thermosetting phenol resin (relative dielectric constant 5 to 8) used in the first embodiment or the second embodiment described below. For example, a thermosetting resin such as an epoxy resin (relative dielectric constant 4 to 4.5) can be used. The relative permittivity of the organic resin is as small as 10 or less, and it is difficult to obtain the relative permittivity required for the dielectric resistance curtain only by the relative permittivity of the resin itself. A high relative dielectric constant can be obtained by uniformly dispersing carbon particles in the organic resin and allowing the organic resin to enter minute gaps between the carbon particles.

以上の構成からなる3端子積層セラミックコンデンサ1は、図6に示すように、積層体10の端部に形成されたカーボン抵抗膜12a,12bがRC並列回路を形成する。つまり、グランド用外部電極G1,G2とグランド用貫通電極4との間にそれぞれ、カーボン抵抗膜12a,12bによるRC並列回路を形成している。そして、積層体10に内蔵された信号用貫通電極3及びグランド用貫通電極4にて構成された主コンデンサCと、カーボン抵抗膜12a,12bによるRC並列回路とが電気的に直列接続している。   In the three-terminal multilayer ceramic capacitor 1 having the above configuration, as shown in FIG. 6, the carbon resistance films 12a and 12b formed at the end of the multilayer body 10 form an RC parallel circuit. That is, an RC parallel circuit including the carbon resistance films 12a and 12b is formed between the ground external electrodes G1 and G2 and the ground through electrode 4 respectively. The main capacitor C constituted by the signal through electrode 3 and the ground through electrode 4 incorporated in the laminate 10 is electrically connected in series with the RC parallel circuit including the carbon resistance films 12a and 12b. .

図7は3端子積層セラミックコンデンサ1の電気等価回路図である。図7において、符号Cは主コンデンサ、Lsは残留直列インダクタンス、C’はRC並列回路のコンデンサ、RはRC並列回路の抵抗を表示している。   FIG. 7 is an electrical equivalent circuit diagram of the three-terminal multilayer ceramic capacitor 1. In FIG. 7, a symbol C indicates a main capacitor, Ls indicates a residual series inductance, C ′ indicates a capacitor of an RC parallel circuit, and R indicates a resistance of the RC parallel circuit.

3端子積層セラミックコンデンサ1は、主コンデンサとRC並列回路を電気的に直列接続しているので、図8に模式的に示すような挿入損失(IL)特性となる。すなわち、主コンデンサの自己共振周波数より高い1GHz付近で、減衰極Pが形成される特性が得られる。点線31は主コンデンサCによる挿入損失成分であり、主コンデンサCの容量値が大きくなると下方に移動し、小さくなると上方に移動する。点線32は抵抗Rによる挿入損失成分であり、抵抗Rの抵抗値が大きくなると上方に移動し、小さくなると下方に移動する。点線33はコンデンサC’による挿入損失成分であり、コンデンサC’の容量値が大きくなると下方に移動し、小さくなると上方に移動する。点線34は残留直列インダクタンスLsによる挿入損失成分であり、残留直列インダクタンスLsの値が大きくなると上方に移動し、小さくなると下方に移動する。   The three-terminal multilayer ceramic capacitor 1 has an insertion loss (IL) characteristic as schematically shown in FIG. 8 because the main capacitor and the RC parallel circuit are electrically connected in series. That is, the characteristic that the attenuation pole P is formed near 1 GHz higher than the self-resonance frequency of the main capacitor is obtained. A dotted line 31 is an insertion loss component by the main capacitor C, and moves downward when the capacitance value of the main capacitor C increases, and moves upward when the capacitance value decreases. A dotted line 32 is an insertion loss component due to the resistor R, and moves upward when the resistance value of the resistor R increases, and moves downward when it decreases. A dotted line 33 is an insertion loss component due to the capacitor C ′, and moves downward when the capacitance value of the capacitor C ′ increases, and moves upward when it decreases. A dotted line 34 is an insertion loss component due to the residual series inductance Ls, and moves upward when the value of the residual series inductance Ls increases, and moves downward when it decreases.

図8から分かるように、周波数が比較的低い帯域(100MHz未満)では、主コンデンサCと抵抗Rの直列回路として機能する。この回路では、主コンデンサCによる電圧変動抑制効果と、抵抗Rによる共振抑制効果が認められる。そのため、電源ラインでの電圧変動を抑えるとともに、残留直列インダクタンスLsの小さいコンデンサで問題となる電源ラインとグランド間の共振現象を抑制することができる。この効果は、抵抗Rを主コンデンサCに直列に接続した場合に発現する(領域Iの部分参照)。ただし、主コンデンサCの容量値が小さい場合、または残留直列インダクタンスLsの値が大きい場合、または抵抗Rの抵抗値が小さい場合には、領域Iの部分は小さくなり、前記効果が発現しにくくなる。   As can be seen from FIG. 8, it functions as a series circuit of the main capacitor C and the resistor R in a band having a relatively low frequency (less than 100 MHz). In this circuit, a voltage fluctuation suppressing effect by the main capacitor C and a resonance suppressing effect by the resistor R are recognized. Therefore, voltage fluctuations in the power supply line can be suppressed, and a resonance phenomenon between the power supply line and the ground can be suppressed with a capacitor having a small residual series inductance Ls. This effect is manifested when the resistor R is connected in series with the main capacitor C (see the region I). However, when the capacitance value of the main capacitor C is small, the value of the residual series inductance Ls is large, or the resistance value of the resistor R is small, the region I becomes small, and the above-described effect is hardly exhibited. .

一方、周波数が比較的高い帯域(100MHz以上)では、RC並列回路のコンデンサC’のインピーダンスが下がるので、主コンデンサCとコンデンサC’の直列回路として機能する。この回路では、信号ラインの高調波等が伝播して入った高周波ノイズを効果的に除去することができる。この効果は、抵抗Rのみを主コンデンサCに直列に接続しただけでは発現しない(領域IIの部分参照)。ただし、コンデンサC’の容量値が小さい場合、または残留直列インダクタンスLsの値が大きい場合、または抵抗Rの抵抗値が小さい場合には、領域IIの部分は小さくなり、前記効果が発現しにくくなる。また、この効果は残留直列インダクタンスLsが小さい積層複合電子部品ほど、より高周波帯まで発現するので、3端子貫通コンデンサには有利である。   On the other hand, in the band having a relatively high frequency (100 MHz or more), the impedance of the capacitor C ′ of the RC parallel circuit is lowered, so that it functions as a series circuit of the main capacitor C and the capacitor C ′. In this circuit, it is possible to effectively remove high-frequency noise that has entered through the propagation of harmonics of the signal line. This effect does not appear when only the resistor R is connected in series to the main capacitor C (see the part of region II). However, when the capacitance value of the capacitor C ′ is small, or when the value of the residual series inductance Ls is large, or when the resistance value of the resistor R is small, the portion of the region II becomes small and the above-described effect is hardly exhibited. . Further, this effect is more advantageous for a three-terminal feedthrough capacitor because a multilayer composite electronic component having a smaller residual series inductance Ls is manifested up to a higher frequency band.

図9は3端子積層セラミックコンデンサ1の挿入損失特性を示すグラフである(実線35参照)。なお、図9には比較のため、RC並列回路を有さない3端子積層セラミックコンデンサの挿入損失特性を示すグラフも併せて記載している(実線36参照)。   FIG. 9 is a graph showing insertion loss characteristics of the three-terminal multilayer ceramic capacitor 1 (see the solid line 35). For comparison, FIG. 9 also shows a graph showing insertion loss characteristics of a three-terminal multilayer ceramic capacitor that does not have an RC parallel circuit (see solid line 36).

より最適なRC並列回路を形成するために、カーボン抵抗膜12a,12bの硬化後のカーボン含有率及び硬化後の膜厚T(図6参照)を変えて3端子積層セラミックコンデンサ1の試料を作製し、特性を評価した。ここで、部品サイズは長さ2.0mm×幅1.25mm×厚み0.85mmとした。評価結果を表1及び表2に示す。   In order to form a more optimal RC parallel circuit, a sample of the three-terminal multilayer ceramic capacitor 1 is prepared by changing the carbon content after curing of the carbon resistance films 12a and 12b and the film thickness T after curing (see FIG. 6). And the characteristics were evaluated. Here, the component size was 2.0 mm long × 1.25 mm wide × 0.85 mm thick. The evaluation results are shown in Tables 1 and 2.

Figure 0004600082
Figure 0004600082

Figure 0004600082
Figure 0004600082

ところで、周波数が比較的低い帯域(100MHz未満)での主コンデンサCによる電圧変動抑制効果や抵抗Rによる共振抑制効果が得られるのは、挿入損失(1MHz)が10dB以上のときである。そこで、表1及び表2から、1MHzでの挿入損失をまとめた(表3参照)。また、周波数が比較的高い帯域(100MHz以上)でのノイズ除去効果が得られるのは、1GHzでの挿入損失から1MHzでの挿入損失を引いたものが2dB以上のときである。そこで、表1及び表2から、1GHzでの挿入損失から1MHzでの挿入損失を引いた値をまとめた(表4参照)。   By the way, the voltage fluctuation suppression effect by the main capacitor C and the resonance suppression effect by the resistor R in the relatively low frequency band (less than 100 MHz) can be obtained when the insertion loss (1 MHz) is 10 dB or more. Therefore, Table 1 and Table 2 summarize the insertion loss at 1 MHz (see Table 3). Further, the noise removal effect in a relatively high frequency band (100 MHz or higher) is obtained when the insertion loss at 1 GHz minus the insertion loss at 1 MHz is 2 dB or higher. Therefore, Table 1 and Table 2 summarize the values obtained by subtracting the insertion loss at 1 MHz from the insertion loss at 1 GHz (see Table 4).

Figure 0004600082
Figure 0004600082

Figure 0004600082
Figure 0004600082

そして、表3及び表4から、周波数が比較的低い帯域(100MHz未満)では電圧変動抑制効果や共振抑制効果が得られ、かつ、周波数が比較的高い帯域(100MHz以上)ではノイズ除去効果が得られるようにするためには、表5に示すカーボン含有量と膜厚Tの関係が必要であることがわかる。   From Tables 3 and 4, a voltage fluctuation suppressing effect and a resonance suppressing effect are obtained in a relatively low frequency band (less than 100 MHz), and a noise removing effect is obtained in a relatively high frequency band (100 MHz or higher). It can be seen that the relationship between the carbon content and the film thickness T shown in Table 5 is necessary in order to achieve this.

Figure 0004600082
Figure 0004600082

表5より、カーボン抵抗膜12a,12bの最適条件は以下のとおりである。   From Table 5, the optimum conditions for the carbon resistance films 12a and 12b are as follows.

(1)硬化後の膜厚が0.01mm以上0.03mm未満のときは、硬化後のカーボン含有率は4〜15体積%になるように設定する必要がある。   (1) When the film thickness after curing is 0.01 mm or more and less than 0.03 mm, the carbon content after curing needs to be set to 4 to 15% by volume.

(2)硬化後の膜厚が0.03mm以上0.05mm未満のときは、硬化後のカーボン含有率が6〜15体積%になるように設定する必要がある。   (2) When the film thickness after curing is 0.03 mm or more and less than 0.05 mm, it is necessary to set the carbon content after curing to be 6 to 15% by volume.

(3)硬化後の膜厚が0.05mm以上0.08mm未満のときは、硬化後のカーボン含有率が8〜15体積%になるように設定する必要がある。   (3) When the film thickness after curing is 0.05 mm or more and less than 0.08 mm, it is necessary to set the carbon content after curing to 8 to 15% by volume.

(4)硬化後の膜厚が0.08mm以上0.10mm以下のときは、硬化後のカーボン含有率が10〜15体積%になるように設定する必要がある。   (4) When the film thickness after curing is 0.08 mm or more and 0.10 mm or less, it is necessary to set the carbon content after curing to 10 to 15% by volume.

(第2実施例、図10〜図12)
図10に示すように、2端子積層セラミックコンデンサ41は、コンデンサ電極43,44をそれぞれ設けたセラミックグリーンシート42と、予め導体パターンを設けない外層用セラミックグリーンシート42等で構成されている。
(Second embodiment, FIGS. 10 to 12)
As shown in FIG. 10, the two-terminal multilayer ceramic capacitor 41 is composed of a ceramic green sheet 42 provided with capacitor electrodes 43 and 44, an outer layer ceramic green sheet 42 not previously provided with a conductor pattern, and the like.

コンデンサ電極43はシート42の上面に広面積に設けられ、その引出し部43aがシート42の手前側の辺に露出している。同様に、コンデンサ44はシート42の上面に広面積に設けられ、その引出し部44aがシート42の奥側の辺に露出している。   The capacitor electrode 43 is provided in a large area on the upper surface of the sheet 42, and the lead-out portion 43 a is exposed on the front side of the sheet 42. Similarly, the capacitor 44 is provided in a large area on the upper surface of the sheet 42, and the lead-out portion 44 a is exposed on the back side of the sheet 42.

各セラミックグリーンシート42はコンデンサ電極43,44が交互になるように積み重ねられ、さらに、上下に外層用セラミックグリーンシート42が配置された後、圧着して積層体ブロックとする。積層体ブロックは所定のサイズにカットされた後、一体的に焼成される。これにより、図11に示す積層体50とされる。   The ceramic green sheets 42 are stacked so that the capacitor electrodes 43 and 44 are alternately arranged. Further, after the ceramic green sheets 42 for outer layers are arranged on the upper and lower sides, they are pressure-bonded to form a laminated body block. The laminated body block is cut into a predetermined size and then fired integrally. Thereby, the laminated body 50 shown in FIG. 11 is obtained.

次に、積層体50の両端面に露出したコンデンサ電極43,44の引出し部43a,44aをそれぞれ覆うカーボン抵抗膜(誘電性抵抗膜)52a,52bを形成する。カーボン抵抗膜52a,52bはカーボン粉末と有機樹脂(フェノール樹脂)などからなる熱硬化性のカーボン抵抗ペーストを塗布し、硬化させることにより形成される。   Next, carbon resistance films (dielectric resistance films) 52a and 52b are formed to cover the lead portions 43a and 44a of the capacitor electrodes 43 and 44 exposed on both end faces of the multilayer body 50, respectively. The carbon resistance films 52a and 52b are formed by applying and curing a thermosetting carbon resistance paste made of carbon powder and organic resin (phenol resin).

その後、カーボン抵抗膜52a,52bの上に、通常の電解めっきでニッケル、錫の順でめっき膜を形成して、外部電極53a,53bとする。   Thereafter, on the carbon resistance films 52a and 52b, plating films are formed in the order of nickel and tin by ordinary electrolytic plating to form external electrodes 53a and 53b.

なお、カーボン抵抗膜52a,52bの下に下地電極を形成して、カーボン抵抗膜52a,52bとコンデンサ電極44,43の間にそれぞれ下地電極を配設してもよい。これにより、カーボン抵抗膜52a,52bによるコンデンサが形成され易くなり、RC並列回路の容量の微調整が可能になる。   A base electrode may be formed under the carbon resistance films 52a and 52b, and the base electrode may be disposed between the carbon resistance films 52a and 52b and the capacitor electrodes 44 and 43, respectively. This facilitates the formation of capacitors by the carbon resistance films 52a and 52b, and enables fine adjustment of the capacity of the RC parallel circuit.

外部電極53a,53bはそれぞれ、カーボン抵抗膜52a,52bを介してコンデンサ電極44の引出し部44a及びコンデンサ電極43の引出し部43aに電気的に接続されている。   The external electrodes 53a and 53b are electrically connected to the lead portion 44a of the capacitor electrode 44 and the lead portion 43a of the capacitor electrode 43 via the carbon resistance films 52a and 52b, respectively.

以上の構成からなる2端子積層セラミックコンデンサ41は、積層体50の端部に形成されたカーボン抵抗膜52a,52bがRC並列回路を形成する。つまり、外部電極53a,53bとコンデンサ電極44,43との間にそれぞれ、カーボン抵抗膜52a,52bによるRC並列回路を形成している。そして、積層体50に内蔵されたコンデンサ電極43,44にて構成された主コンデンサCと、カーボン抵抗膜52a,52bによるRC並列回路とが電気的に直列接続している。図12は2端子積層セラミックコンデンサ41の電気等価回路図である。   In the two-terminal multilayer ceramic capacitor 41 having the above configuration, the carbon resistance films 52a and 52b formed at the end of the multilayer body 50 form an RC parallel circuit. That is, an RC parallel circuit is formed by the carbon resistance films 52a and 52b between the external electrodes 53a and 53b and the capacitor electrodes 44 and 43, respectively. And the main capacitor C comprised by the capacitor electrodes 43 and 44 incorporated in the laminated body 50 and the RC parallel circuit by the carbon resistance films 52a and 52b are electrically connected in series. FIG. 12 is an electrical equivalent circuit diagram of the two-terminal multilayer ceramic capacitor 41.

2端子積層セラミックコンデンサ41は、主コンデンサCとRC並列回路を電気的に直列接続しているので、周波数が比較的低い帯域(100MHz未満)では、主コンデンサCと抵抗Rの直列回路として機能する。この回路では、主コンデンサCによる電圧変動抑制効果と、抵抗Rによる共振抑制効果が認められる。そのため、電源ラインでの電圧変動を抑えるとともに、残留直列インダクタンスLsの小さいコンデンサで問題となる電源ラインとグランド間の共振現象を抑制することができる。   Since the two-terminal multilayer ceramic capacitor 41 electrically connects the main capacitor C and the RC parallel circuit in series, it functions as a series circuit of the main capacitor C and the resistor R in a relatively low frequency band (less than 100 MHz). . In this circuit, a voltage fluctuation suppressing effect by the main capacitor C and a resonance suppressing effect by the resistor R are recognized. Therefore, voltage fluctuations in the power supply line can be suppressed, and a resonance phenomenon between the power supply line and the ground can be suppressed with a capacitor having a small residual series inductance Ls.

一方、周波数が比較的高い帯域(100MHz以上)では、RC並列回路のコンデンサC’のインピーダンスが下がるので、主コンデンサCとコンデンサC’の直列回路として機能する。この回路では、信号ラインの高調波等が伝播して入った高周波ノイズを効果的に除去することができる。   On the other hand, in the band having a relatively high frequency (100 MHz or more), the impedance of the capacitor C ′ of the RC parallel circuit is lowered, so that it functions as a series circuit of the main capacitor C and the capacitor C ′. In this circuit, it is possible to effectively remove high-frequency noise that has entered through the propagation of harmonics of the signal line.

より最適なRC並列回路を形成するために、カーボン抵抗膜52a,52bの硬化後のカーボン含有率及び硬化後の膜厚Tを変えて2端子積層セラミックコンデンサ41の試料を作製し、特性を評価した。評価結果を表6及び表7に示す。   In order to form a more optimal RC parallel circuit, a sample of the two-terminal multilayer ceramic capacitor 41 is prepared by changing the carbon content after curing of the carbon resistance films 52a and 52b and the film thickness T after curing, and the characteristics are evaluated. did. The evaluation results are shown in Tables 6 and 7.

Figure 0004600082
Figure 0004600082

Figure 0004600082
Figure 0004600082

ところで、周波数が比較的低い帯域(100MHz未満)での主コンデンサCによる電圧変動抑制効果や抵抗Rによる共振抑制効果が得られるのは、挿入損失(1MHz)が10dB以上のときである。そこで、表6及び表7から、1MHzでの挿入損失をまとめた(表8参照)。また、周波数が比較的高い帯域(100MHz以上)でのノイズ除去効果が得られるのは、1GHzでの挿入損失から1MHzでの挿入損失を引いたものが2dB以上のときである。そこで、表6及び表7から、1GHzでの挿入損失から1MHzでの挿入損失を引いた値をまとめた(表9参照)。   By the way, the voltage fluctuation suppression effect by the main capacitor C and the resonance suppression effect by the resistor R in the relatively low frequency band (less than 100 MHz) can be obtained when the insertion loss (1 MHz) is 10 dB or more. Therefore, Table 6 and Table 7 summarize the insertion loss at 1 MHz (see Table 8). Further, the noise removal effect in a relatively high frequency band (100 MHz or higher) is obtained when the insertion loss at 1 GHz minus the insertion loss at 1 MHz is 2 dB or higher. Therefore, Table 6 and Table 7 summarize the values obtained by subtracting the insertion loss at 1 MHz from the insertion loss at 1 GHz (see Table 9).

Figure 0004600082
Figure 0004600082

Figure 0004600082
Figure 0004600082

そして、表8及び表9から、周波数が比較的低い帯域(100MHz未満)では電圧変動抑制効果や共振抑制効果が得られ、かつ、周波数が比較的高い帯域(100MHz以上)ではノイズ除去効果が得られるようにするためには、表10に示すカーボン含有量と膜厚Tの関係が必要であることがわかる。   From Table 8 and Table 9, a voltage fluctuation suppressing effect and a resonance suppressing effect are obtained in a relatively low frequency band (less than 100 MHz), and a noise removing effect is obtained in a relatively high frequency band (100 MHz or higher). It can be seen that the relationship between the carbon content and the film thickness T shown in Table 10 is necessary to achieve this.

Figure 0004600082
Figure 0004600082

表10より、カーボン抵抗膜52a,52bの最適条件は以下のとおりである。   From Table 10, the optimum conditions for the carbon resistance films 52a and 52b are as follows.

(1)硬化後の膜厚が0.01mm以上0.02mm未満のときは、硬化後のカーボン含有率が8〜10体積%になるように設定する必要がある。   (1) When the film thickness after curing is 0.01 mm or more and less than 0.02 mm, it is necessary to set the carbon content after curing to 8 to 10% by volume.

(2)硬化後の膜厚が0.02mm以上0.03mm未満のときは、硬化後のカーボン含有率が10〜15体積%になるように設定する必要がある。   (2) When the film thickness after curing is 0.02 mm or more and less than 0.03 mm, it is necessary to set the carbon content after curing to 10 to 15% by volume.

(3)硬化後の膜厚が0.03mm以上0.05mm未満のときは、硬化後のカーボン含有率が15体積%になるように設定する必要がある。   (3) When the film thickness after curing is 0.03 mm or more and less than 0.05 mm, it is necessary to set the carbon content after curing to 15 volume%.

(4)硬化後の膜厚が0.05mm以上0.06mm未満のときは、硬化後のカーボン含有率が15〜20体積%になるように設定する必要がある。   (4) When the film thickness after curing is 0.05 mm or more and less than 0.06 mm, it is necessary to set the carbon content after curing to 15 to 20% by volume.

(5)硬化後の膜厚が0.06mm以上0.10mm以下のときは、硬化後のカーボン含有率が20体積%になるように設定する必要がある。   (5) When the film thickness after curing is 0.06 mm or more and 0.10 mm or less, it is necessary to set the carbon content after curing to 20 volume%.

(他の実施例)
なお、本発明に係る積層型複合電子部品は前記実施例に限定するものではなく、その要旨の範囲内で種々に変更することができる。
(Other examples)
The multilayer composite electronic component according to the present invention is not limited to the above-described embodiment, and various modifications can be made within the scope of the gist thereof.

例えば、前記実施例では、セラミックグリーンシートを積み重ねて積層体を形成するものを示したが、誘電体ペーストと導電ペーストを交互に順に重ね塗りする方法で積層体を形成するものであってもよい。   For example, in the above embodiment, the ceramic green sheets are stacked to form a laminated body. However, the laminated body may be formed by a method in which a dielectric paste and a conductive paste are alternately and sequentially applied. .

本発明に係る積層型複合電子部品の一実施例を示す分解斜視図。1 is an exploded perspective view showing an embodiment of a multilayer composite electronic component according to the present invention. 図1に続く製造工程を示す外観斜視図。FIG. 2 is an external perspective view showing a manufacturing process following FIG. 1. 図2に続く製造工程を示す外観斜視図。FIG. 3 is an external perspective view showing a manufacturing process following FIG. 2. 図3に続く製造工程を示す外観斜視図。FIG. 4 is an external perspective view showing a manufacturing process following FIG. 3. 図4に続く製造工程を示す外観斜視図。FIG. 5 is an external perspective view illustrating a manufacturing process subsequent to FIG. 4. 図5のVI−VIの垂直断面を示す模式図。The schematic diagram which shows the vertical cross section of VI-VI of FIG. 図5に示した積層型複合電子部品の電気等価回路図。FIG. 6 is an electrical equivalent circuit diagram of the multilayer composite electronic component shown in FIG. 5. 図5に示した積層型複合電子部品の挿入損失特性を示す模式的に表したグラフ。6 is a graph schematically showing insertion loss characteristics of the multilayer composite electronic component shown in FIG. 図5に示した積層型複合電子部品の挿入損失特性を示すグラフ。6 is a graph showing insertion loss characteristics of the multilayer composite electronic component shown in FIG. 5. 本発明に係る積層型複合電子部品の別の実施例を示す分解斜視図。The disassembled perspective view which shows another Example of the multilayer composite electronic component which concerns on this invention. 図10に続く製造工程を示す外観斜視図。FIG. 11 is an external perspective view illustrating a manufacturing process subsequent to FIG. 10. 図11に示した積層型複合電子部品の電気等価回路図。FIG. 12 is an electrical equivalent circuit diagram of the multilayer composite electronic component shown in FIG. 11.

符号の説明Explanation of symbols

1,41…積層セラミックコンデンサ
2,42…セラミックグリーンシート
3…信号用貫通電極
4…グランド用貫通電極
10,50…積層体
12a,12b,52a,52b…カーボン抵抗膜
21a,21b…信号用外部電極
G1,G2…グランド用外部電極
43,44…コンデンサ電極
53a,53b…外部電極
C…主コンデンサ
C’…RC並列回路のコンデンサ
R…RC並列回路の抵抗
DESCRIPTION OF SYMBOLS 1,41 ... Multilayer ceramic capacitor 2,42 ... Ceramic green sheet 3 ... Signal through electrode 4 ... Ground through electrode 10, 50 ... Laminated body 12a, 12b, 52a, 52b ... Carbon resistance film 21a, 21b ... Signal outside Electrodes G1, G2 ... Ground external electrodes 43, 44 ... Capacitor electrodes 53a, 53b ... External electrodes C ... Main capacitor C '... Capacitor in RC parallel circuit R ... Resistance in RC parallel circuit

Claims (2)

複数のセラミック層を積み重ねて構成した積層体と、前記積層体に内蔵された複数のコンデンサ電極にて構成された主コンデンサと、前記積層体の端部に形成され、かつ前記コンデンサ電極と電気的に接続する複数の外部電極とを有する積層型複合電子部品において、
前記外部電極の少なくとも一つが誘電性抵抗膜を介して前記コンデンサ電極と電気的に接続し、前記外部電極と前記コンデンサ電極との間に、前記誘電性抵抗膜によるRC並列回路を形成して、前記主コンデンサと前記RC並列回路を電気的に直列接続し、
前記積層型複合電子部品が3端子貫通コンデンサであり、コンデンサ電極は信号用貫通電極とグランド用貫通電極とで構成され、前記誘電性抵抗膜は前記グランド用貫通電極に接続され、
前記誘電性抵抗膜はカーボン粉末と有機樹脂とを含むカーボン抵抗膜であり、
前記カーボン抵抗膜は、
硬化後の膜厚が0.01mm以上0.03mm未満のときは、硬化後のカーボン含有率が4〜15体積%になるように設定され、
硬化後の膜厚が0.03mm以上0.05mm未満のときは、硬化後のカーボン含有率が6〜15体積%になるように設定され、
硬化後の膜厚が0.05mm以上0.08mm未満のときは、硬化後のカーボン含有率が8〜15体積%になるように設定され、
硬化後の膜厚が0.08mm以上0.10mm以下のときは、硬化後のカーボン含有率が10〜15体積%になるように設定されていること、
を特徴とする積層型複合電子部品。
A laminated body constituted by stacking a plurality of ceramic layers, a main capacitor constituted by a plurality of capacitor electrodes built in the laminated body, and formed at an end of the laminated body, and electrically connected to the capacitor electrode In a multilayer composite electronic component having a plurality of external electrodes connected to
At least one of the external electrodes is electrically connected to the capacitor electrode through a dielectric resistance film, and an RC parallel circuit is formed by the dielectric resistance film between the external electrode and the capacitor electrode; Electrically connecting the main capacitor and the RC parallel circuit in series;
The multilayer composite electronic component is a three-terminal through capacitor, the capacitor electrode is composed of a signal through electrode and a ground through electrode, and the dielectric resistance film is connected to the ground through electrode ,
The dielectric resistance film is a carbon resistance film containing carbon powder and an organic resin,
The carbon resistive film is
When the film thickness after curing is 0.01 mm or more and less than 0.03 mm, the carbon content after curing is set to 4 to 15% by volume,
When the film thickness after curing is 0.03 mm or more and less than 0.05 mm, the carbon content after curing is set to be 6 to 15% by volume,
When the film thickness after curing is 0.05 mm or more and less than 0.08 mm, the carbon content after curing is set to 8 to 15% by volume,
When the film thickness after curing is 0.08 mm or more and 0.10 mm or less, the carbon content after curing is set to be 10 to 15% by volume ,
A multilayer composite electronic component characterized by
前記誘電性抵抗膜と前記コンデンサ電極の間に下地電極が配設されていることを特徴とする請求項1に記載の積層型複合電子部品。 2. The multilayer composite electronic component according to claim 1, wherein a base electrode is disposed between the dielectric resistance film and the capacitor electrode.
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