JP4604341B2 - Synchronous word search method and synchronous word search circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
INDUSTRIAL APPLICABILITY The present invention is effective for searching for a synchronization word such as a data stream obtained by encoding a moving image, and searching for a synchronization word when decoding a data stream composed of a unique synchronization word and variable-length encoded data. Regarding the method.
[0002]
H.261 / H.263 standardized by ITU-T (International Telecommunication Union-Telecommunication Standardization Sector) and MPEG (Moving Picture Experts Group) standardized by ISO (International Organization for Standardization) There is 1/2/4 mag.
[0003]
In these moving image transmissions, it is required to search a synchronization word reliably from a data stream and display a moving image in which decoded data is not lost.
[0004]
[Prior art]
FIG. 9 is a diagram for explaining the prior art.
[0005]
In the figure, reference numeral 100 denotes a buffer memory that temporarily stores an input data stream, and reference numeral 200 denotes a synchronization word search unit that takes out the data stream from the stored buffer memory 100 and searches for a synchronization word therein. , 300 is a header parsing unit that extracts a header part from the data stream and analyzes the header when a synchronization word is searched and its position is fixed.
[0006]
Reference numeral 400 denotes an encoded data decoding unit that demodulates the variable-length encoded data that is input after the header parsing unit 300 confirms the normality of the header, and 500 is decoded by the encoded data decoding unit 400. It is an error detection unit that detects an error in the decoded data.
[0007]
In the configuration shown in the figure, the input data stream is temporarily stored in the buffer memory 100 and then read into the synchronization word search unit 200 to search for a synchronization word. When a sync word is searched, a header is extracted from the sync word position, and the normality of the header is analyzed. When the header is normal, the input variable-length encoded data is decoded, and the error detection unit 500 detects an error in the decoded data.
[0008]
Here, when an error is detected during the decoding process, it is possible to stop the decoding process. However, if the decoding process is stopped, it becomes impossible to decode the variable-length encoded data after the error occurs. When the method is adopted, each time an error occurs, for example, an operator who monitors the decoded moving image needs to restart the synchronization word search circuit, and the efficiency of the decoding process is poor. Become.
[0009]
Therefore, when an error is detected in the middle of decoding the data stream, the synchronization word is searched from that point, and the decoding process is resumed from the point where the synchronization word has been searched.
[0010]
Here, as a method of detecting errors in the data stream,
(1) When a variable length code that does not exist is decoded.
[0011]
(2) When an inconsistency in the decoding result is detected.
[0012]
Is determined to have occurred.
[0013]
(2) is the case where the value of the decoded data exceeds a predetermined value range, etc., and error detection is usually performed by combining (1) and (2).
[0014]
[Problems to be solved by the invention]
In the above-described conventional technique, an error detection point when decoding variable length encoded data may be in the middle of decoding variable length encoded data. In some cases, this error mixture cannot be detected and the decoding process is continued, and an error is detected during reading of a unique synchronization word. At this time, if the search for the synchronization word is started from the point where the error is detected, the synchronization word at the position where the error is detected cannot be detected, and the variable-length encoded data up to the next synchronization word cannot be decoded.
[0015]
FIG. 10 is a diagram for explaining the operation of the prior art and explains the above-described operation.
[0016]
(A) shows an example of an input data stream. Variable length encoded data (shown as a variable length code string in the figure) follows a synchronization word, and the synchronization word and variable length encoded data are alternately input.
[0017]
(B) shows the operation when an error is detected during decoding of the data stream.
[0018]
(1) While variable length encoded data is being decoded, an error has occurred at the position of the x mark at point (1), but the error cannot be detected and the decoding operation is continued.
[0019]
(2) This error occurrence is detected at point (2) in the middle of the synchronization word.
[0020]
(3) Since an error is detected, a search operation for the next synchronization word is started from this point.
[0021]
(4) A synchronization word is detected at the next point (4) and the decoding operation is restarted. In this case, the variable length encoded data in the shaded portion (3) cannot be decoded.
[0022]
In order to prevent the occurrence of undecoded variable-length encoded data when an error is detected, two hardware units are prepared: hardware that detects a unique synchronization word and hardware that decodes variable-length encoded data. It is possible to operate these two pieces of hardware independently and in parallel. However, since two pieces of hardware are required, the cost of hardware increases. In addition, the software can detect a unique synchronization word and decode the variable-length encoded data in parallel. However, such a configuration uses a large amount of resources such as memory to perform parallel processing. The circuit is costly.
[0023]
In the present invention, when an error is detected in the decoding process of a data stream composed of a unique synchronization word and encoded data, it is not decoded by performing a search for the synchronization word after reading back a predetermined number of bits. An object of the present invention is to realize a synchronous word search method capable of preventing the generation of encoded data.
[0024]
[Means for Solving the Problems]
FIG. 1 is a diagram for explaining the first principle of the present invention. The figure shows a method of searching for a synchronization word when decoding a data stream consisting of a unique synchronization word and encoded data. Step 1 reads the data stream into the buffer memory, and Step 2 includes the data stream read into the buffer memory. Step 3 searches for a synchronization word in the data stream, decodes the encoded data following the synchronization word, and Step 4 performs error detection in the decoded data of the encoded data. Next, when an error is detected in the decoded data of the encoded data, step 5 reads back the data in the buffer memory by a predetermined number of bits, and returns to step 2 to search for a synchronization word. Performs decoding from the encoded data after the search for the synchronization word is performed and outputs the decoded data.
[0025]
With this process, even if an error in the encoded data is detected during the search for the sync word, the search for the sync word is performed after performing the read-back after a predetermined number of bits, so the search for the sync word can be prevented. Decoding leakage of encoded data can be prevented.
[0026]
FIG. 2 is a diagram for explaining the operation of the first invention. It is assumed that the input data stream has the same configuration as that described with reference to FIG.
[0027]
(1) While the encoded data is being decoded, an error has occurred at point (1), but the error cannot be detected and the decoding operation is continued.
[0028]
(2) An error is detected at point (2) in the middle of the synchronization word.
[0029]
(3) Since an error has been detected, a predetermined number of bits are read back.
[0030]
{Circle around (4)} Search for the next sync word, and search for the sync word with the next sync word of the encoded data in which an error has occurred.
[0031]
(5) Thereafter, normal decryption processing is started. Encoded data indicated by shading cannot be decoded in the prior art, but can be decoded in the present invention. (Claim 1)
Also, by setting the predetermined number of bits at the time of reading back to a value greater than or equal to the maximum code length of the encoded data, it is possible to prevent the synchronization word from being overlooked. Further, the predetermined number of bits when reading back is set to a value that does not exceed the code length of the synchronization word. This is because if the predetermined number of bits when reading back exceeds the code length of the sync word, the sync word searched last time will be detected when searching for the next sync word at the time of error detection. It will fall into the loop action. Therefore, it is possible to prevent a loop operation from occurring by setting a value that does not exceed the code length of the synchronization word. By setting the read-back position after the position of the synchronization word, it is possible to reliably search for the next synchronization word and reduce the decoding leak of the variable-length encoded data.
[0032]
FIG. 3 is a diagram for explaining the second principle of the present invention. The figure shows a synchronization word search circuit at the time of decoding a data stream consisting of a unique synchronization word and encoded data. Reference numeral 100 in the figure is a buffer memory for reading the data stream, and reference numeral 200 is in the data stream read into the buffer memory 100. , 300 is a header parsing unit that analyzes the synchronization word searched by the synchronization word searching unit 200, and 400 is a header parsing unit 300 that confirms the normality of the synchronization word. The encoded data decoding unit decodes the encoded data subsequent to the synchronization word.
[0033]
Reference numeral 500 denotes an error detection unit that detects an error in the decoded data of the encoded data. Reference numeral 600 denotes a read-back of a predetermined number of bits when the error detection unit 500 detects a decoding error of the encoded data. Read back position control means for controlling the read position.
[0034]
With this configuration, when the error detection unit 500 detects a decoding error in the encoded data during the search for the synchronization word in the buffer memory 100, the read-back position control unit 600 performs read-back by a predetermined number of bits. Since the search for the synchronization word is performed above, the search for the synchronization word is eliminated and the decoding of the encoded data can be prevented. (Claim 2)
Further, the read back position control means 600 is provided with a register 620 that describes the position of the sync word searched by the sync word search unit 200, and when the read position control unit 610 controls the read position, Control is performed according to the bit position stored in the register 620.
[0035]
With this configuration, it is possible to reliably search for a synchronization word.
[0036]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 4 is a diagram for explaining a data stream used in the embodiment of the present invention, and FIGS. 5 to 7 show operation flowcharts (1) to (3) of the first embodiment of the present invention.
[0037]
In the embodiment of the present invention, an MPEG-4 data stream is used, and its configuration will be described with reference to FIG. The MPEG-4 data stream is indicated as a video object sequence (hereinafter referred to as VOS), a video object layer (hereinafter referred to as VOL), and a video object plane (hereinafter referred to as VOP). ), And a hierarchical structure composed of video packets (hereinafter referred to as VP). The VP data is obtained by dividing an image of one moving image into a plurality of macro blocks and encoding the data of each macro block.
[0038]
Also, as shown in the figure, a header is attached to the head of each layer, and a VOS has a VOS header, a VOL has a VOL header, a VOP has a VOP header, and a VP has a VP header. Yes.
[0039]
Furthermore, a start code is added to the head of each header as a unique synchronization word. The VOS has a VOS start code, the VOL has a VOL start code, the VOP has a VOP start code, and the VP has a VOP start code. A VP start code is attached.
[0040]
The operation of the embodiment of the present invention will be described below with reference to FIGS.
[0041]
In step S11, data in the buffer memory 100 storing the input data stream is sequentially extracted, and a search for a VOS synchronization word composed of, for example, 32 bits is performed. When a synchronization word is detected in S12, it is determined whether or not it is a VOS start code. If a start code can be searched in S13, the bit position of the VOS start code is stored in a register 620 (described in FIG. 8). In step S14, the searched VOS header is analyzed. In step S15, it is determined whether or not an error is detected. If an error is detected, the process ends in error. In S16, if it is not a VOS start code in S12, it is determined whether or not it is a VOS end code. If it is not an end code, the process ends in error, and if it is an end code, it ends normally.
[0042]
If there is no error in the VOS header searched in S15, S21 searches for a VOL synchronization word. After detecting the VOL sync word in S22, it is determined whether or not it is a VOL start code. If the VOL start code cannot be detected, return to the search for the VOS sync word in S11 and search for the VOL start code. If so, the bit position of the VOL start code is stored in the register 620 in S23. In S24, the searched VOL header is analyzed. In S25, it is determined whether or not an error is detected. If an error is detected, the next VOL synchronization word is detected in S26 and the process returns to S22. If no error can be detected in S25, the process proceeds to S31 next to (2).
[0043]
In S31, if there is no error in the VOL header searched in S25, the VOP synchronization word is searched. After detecting the VOP sync word, it is determined whether or not it is a VOP start code in S32. If the VOP start code cannot be detected, the process returns to S21 for searching for the VOL sync word in (3), and the VOP start code can be searched. If so, the bit position of the VOP start code is stored in the register 620 in S33. In S34, the searched VOP header is analyzed. In S35, it is determined whether or not an error is detected. If an error is detected, the next VOP synchronization word is detected in S36 and the process returns to S32. If no error can be detected in S35, the process proceeds to the next S41.
[0044]
In S41, if there is no error in the VOP header searched in S35, the VP synchronization word is searched. After detecting the VP sync word, it is determined whether or not it is a VP start code in S42. If the VP start code cannot be detected, the process returns to the search for the VOP sync word in S31 and the VP start code can be searched. If so, the bit position of the VP start code is stored in the register 620 in S43. In S44, the searched VP header is analyzed. In S45, it is determined whether or not an error is detected. If an error is detected, the next VP synchronization word is detected in S46 and the process returns to S42. If no error can be detected by the header parsing of S45, the process proceeds to S51 of (5).
[0045]
In S51, when an error cannot be detected in S45, after decoding the VP data, in S52, it is detected whether there is an error in the decoded data of the VP data or whether there is a contradiction in the decoding result. The contradiction in the decoding result is that the number of macroblocks currently decoded is larger than the maximum number of macroblocks in one frame or the number of macroblocks included in one video packet is a value read from the header. And the number of macroblocks actually decoded does not match. If an error or an inconsistency in the decoding result is detected in S52, the process returns to S41 in (6) to search for the next VP start code. If no error or inconsistency of the decoding result cannot be detected in S52, the 32-bit read-back that is the same as the number of bits of the start code is performed in S53, and the bit position in which the read-back is performed in S54 is stored in the register 620. If the bit position is earlier than the position stored in the register 620, the position where the search for the VP sync word is started is added to the position "+1" stored in the register 620 in S55. Bit position.
[0046]
With this processing, even when an error is detected in the decoding result of the VP data, the synchronization word is searched after reading back the specified number of bits. It becomes possible to reliably detect the sync word from the incoming sync word.
[0047]
In S53 of FIG. 7, 32-bit read-back that is the number of bits of the synchronization word is performed. This 32-bit read-back makes it possible to detect the synchronization word that is being input when the variable-length encoded data in which an error has occurred. Furthermore, by starting the search from the synchronization word after the previous synchronization word, it is possible to prevent the occurrence of a loop due to detection of the same synchronization word.
[0048]
FIG. 8 is a diagram for explaining a second embodiment of the present invention. The buffer memory 100, the synchronization word search unit 200, the header parsing unit 300, the encoded data decoding unit 400, and the error detection unit 500 in the figure have the same configuration as described in the principle diagram of FIG.
[0049]
In the second embodiment shown in FIG. 8, the read back position control means 600 described in the principle diagram is added to a read position control unit 610 that controls the read position when the error detection unit 500 detects an error in the decoded data. A read-back bit number setting unit (shown as a read-back bit number setting unit in the figure) 611 for setting the number of read-back bits when performing read-back, and a register for storing a bit position when a synchronization word is detected 620 and a counter 630 that counts the bit positions of the data stream. In the configuration shown in the figure, the input data stream is stored in the buffer memory 100 and sequentially input to the synchronization word search unit 200 while the read bit positions are counted by the counter 630 to search for synchronization words. When the synchronization word is searched, the bit position is stored in the register 620.
[0050]
Next, the searched synchronization word is analyzed by the header parsing unit 300. If the header is normal, the variable length encoded data decoding unit 400 decodes the variable length encoded data following the synchronization word, and the error detection unit An error is detected at 500. If no error is detected, the next sync word is searched. If the sync word can be searched, the decoding process for the next variable-length encoded data is repeatedly executed.
[0051]
If an error is detected, the number of bits set in the read back bit number setting unit 611 and the data stream are read back, and then the sync word search unit 200 starts searching for the next sync word.
[0052]
At this time, by setting a value greater than or equal to the maximum code length of the encoded data in the read-back bit number setting unit 611 as the read-back bit number, it is possible to prevent the synchronization word from being overlooked. In addition, when the synchronization word is 32 bits, a variable in which an error has occurred can be obtained by setting 32 bits in the read-back bit number setting unit 611, performing a 32-bit read-back, and then searching for the synchronization word. It is possible to reliably search for the next synchronization word of the long encoded data. Further, when the read back is performed, the returned bit position is compared with the bit position stored in the register 620. If the bit position is before the bit position of the register 620, the bit position obtained by adding “+1” to the value of the register 620. Therefore, it is possible to prevent falling into an infinite loop by searching for a synchronization word.
[0053]
(Supplementary Note 1) A method for searching for a synchronization word in a data stream composed of a unique synchronization word and encoded data,
Reading the data stream into the buffer memory;
Searching for synchronization words in the data stream read into the buffer memory;
Searching for a sync word in the data stream and decoding the encoded data following the sync word;
Detecting an error in the decoded data of the encoded data;
A synchronization word search method comprising: a step of reading back a predetermined number of bits of data in a buffer memory and returning to a step of searching for a synchronization word when an error in the decoded data is detected.
[0054]
(Supplementary note 2) In the synchronous word search method according to supplementary note 1,
A method for searching for a synchronous word, characterized in that a predetermined number of bits when reading back is set to a value equal to or greater than a maximum code of encoded data.
(Supplementary note 3) In the synchronous word search method according to supplementary note 1,
A synchronization word search method characterized in that a predetermined number of bits for reading back is set to a value not exceeding the code length of the previous synchronization word.
[0055]
(Supplementary note 4) In the synchronous word search method according to supplementary note 1,
A method for searching for a synchronization word, characterized in that the read-back position is made after the previous synchronization word search position.
[0056]
(Supplementary Note 5) A search circuit for a synchronization word in a data stream composed of a unique synchronization word and encoded data,
A buffer memory to read the data stream;
A synchronization word search unit for searching for a synchronization word in the data stream read into the buffer memory;
A header parsing unit for analyzing a synchronization word searched by the synchronization word search unit;
When the normality of the synchronization word is confirmed in the header parsing unit, an encoded data decoding unit that decodes encoded data subsequent to the synchronization word;
An error detection unit for detecting an error in the encoded data;
A synchronous word search circuit comprising: a read back position control means for controlling a read position for reading back a predetermined number of bits when an error is detected by the error detector.
[0057]
(Supplementary note 6) In the synchronous word search circuit according to supplementary note 5,
A register for storing the position of the synchronization word searched by the synchronization word search unit;
A synchronous word search circuit, wherein when the reading position control means controls the reading position, control is performed based on the read back bit position and the bit position stored in the register.
[0058]
【The invention's effect】
According to the present invention, when an error is detected in the decoding process of a data stream composed of a unique synchronization word and variable-length encoded data, the synchronization word is searched after a predetermined number of bits are read back. Thus, it is possible to realize a synchronous word search method that can prevent the occurrence of variable-length encoded data that is not decoded.
[Brief description of the drawings]
FIG. 1 illustrates the first principle of the present invention. FIG. 2 illustrates the operation of the first invention. FIG. 3 illustrates the second principle of the present invention. FIG. 5 is a diagram for explaining a data stream used in the embodiment of the present invention. FIG. 5 is an operation flowchart (1) of the first embodiment of the present invention.
FIG. 6 is an operation flowchart (2) of the first embodiment of the present invention.
FIG. 7 is an operation flowchart (3) according to the first embodiment of this invention;
FIG. 8 is a diagram for explaining a second embodiment of the present invention. FIG. 9 is a diagram for explaining the prior art. FIG. 10 is a diagram for explaining the operation of the prior art.
DESCRIPTION OF SYMBOLS 100 Buffer memory 200 Synchronous word search part 300 Header parsing part 400 Encoded data decoding part 500 Error detection part 600 Read back position control means 610 Read position control part 611 Read back bit number setting part 620 Register 630 Counter

Claims (2)

A method of searching for a synchronization word in a data stream consisting of a unique synchronization word and encoded data,
Reading the data stream into a buffer memory;
A step of searching for said synchronization word in the data stream read into the buffer memory,
And performing decoding of the coded data subsequent to the synchronization word and the synchronization word,
Detecting an error in the decoded data;
Upon detecting the error in loading of the synchronous word, the data stream in the buffer memory read back a predetermined number of bits, sync word search method characterized by comprising the step of returning to the step of searching for the synchronization word . A search circuit for a sync word in a data stream consisting of a unique sync word and encoded data,
A buffer memory for reading the data stream;
A synchronization word search unit for searching for the sync word in the data stream read into the buffer memory,
A header parsing unit for analyzing the sync word which is searched by the synchronization word search unit,
When normality of the synchronization word in the header parsing unit is confirmed, the encoded data decoding unit for decoding subsequent coded data in the sync word and the sync word,
An error detection unit for detecting an error in the decoded data;
When an error is detected by the error detection unit during reading of the synchronization word, the data stream in the buffer memory is constituted by a read back position control means for controlling a read position for reading back a predetermined number of bits. Synchronous word search circuit.