JP4606181B2 - Multilayer wiring board - Google Patents

Description

  The present invention relates to a multilayer wiring board, and more specifically, a package for storing an electronic component such as a package for housing a semiconductor element for housing a semiconductor integrated circuit element, or a probe card for performing an electrical inspection of a semiconductor integrated circuit or the like. The present invention relates to a multilayer wiring board used for, for example.

  2. Description of the Related Art In recent years, in semiconductor integrated circuits, the number of terminals formed on a semiconductor substrate has increased and the pitch of terminals has been reduced due to higher integration of semiconductor elements and an increase in the number of processing signals. As a result, the pitch of the connection terminals of the package for housing the semiconductor element that houses the semiconductor integrated circuit element and the probe of the probe card that performs electrical inspection of the semiconductor integrated circuit is also required.

  In response to this demand for narrow pitches, in the package for housing semiconductor devices, the mounting form of the semiconductor devices is changed from wire bonding connection to flip chip connection, and the probe card is a cantilever type, and needle-like probes are finely latticed. It has changed to something arranged in a shape.

  In addition, the structure of the multilayer wiring board used in the semiconductor element storage package and the probe card is formed by forming a wiring conductor layer obtained by patterning a copper foil on an insulating layer obtained by impregnating and curing an organic resin on a substrate made of glass fiber. Multi-layer consisting of a thin insulating layer and a wiring conductor layer on the top surface of the substrate, which is excellent in narrowing the pitch of the wiring conductor layer and can be arranged in a fine lattice pattern. It is changing to a build-up type multilayer wiring board in which a wiring part is formed.

Such a build-up type multilayer wiring board is made of polyimide resin or the like on the upper surface of the board, and an insulating layer formed by applying a resin precursor by a curtain coating method or a spin coating method and heat curing, and a copper It consists of metal such as aluminum and aluminum, and has a structure in which wiring conductor layers formed by adopting thin film formation technology such as plating method and vapor deposition method and photolithography technology are alternately laminated in multiple layers .
JP 11-163520 A Japanese Patent Laid-Open No. 11-38044

  However, in a multilayer wiring board in which an insulating layer made of polyimide resin or the like is laminated in multiple layers on the upper surface of the substrate, the polyimide resin is cured by heating or bonded or heated and pressurized and cooled. Due to the difference in thermal expansion coefficient, the surface of the multilayer wiring board has a concave warp, and when a chip such as a semiconductor element is mounted with a bump, it cannot be joined well due to the height variation due to the warp of the board. there were.

  In addition, in order to reduce the warpage generated in the substrate, the insulating layer made of polyimide resin or the like is laminated on the back side of the substrate in the same manner as the upper surface of the substrate, and the warpage is reduced by forming the same resin structure in the upper and lower sides. When trying to prevent it, there is a problem that the heat dissipation of the heat generated from the chip is lowered.

  The present invention has been made in view of the problems in the background art as described above, and the object thereof is high mounting reliability and connection reliability of the wiring conductor layer of the multilayer wiring board, and a narrow pitch of the wiring conductor layer. It is an object of the present invention to provide a multilayer wiring board that can cope with the above.

The multilayer wiring board of the present invention is an insulating layer formed by laminating an insulating film layer and an insulating adhesive layer and a plurality of wiring conductor layers alternately, and is insulated from the insulating layer. The non-forming part of the adhesive layer is provided in a plurality of layers, and the non-forming parts adjacent to each other in the stacking direction of the insulating layers are arranged so as not to overlap each other in a plan view .

  The multilayer wiring board of the present invention is preferably characterized in that the area occupied by the non-formed part is gradually increased from the central part to the outer peripheral part of the insulating adhesive layer.

  According to the multilayer wiring board of the present invention, in a multilayer wiring board in which an insulating layer formed by laminating an insulating film layer and an insulating adhesive layer and a plurality of wiring conductor layers are alternately laminated, By providing the non-forming part of the insulating adhesive layer, the non-forming part absorbs the expansion and contraction of the insulating adhesive layer having a large thermal expansion coefficient, thereby reducing the dimensional change of the insulating adhesive layer as a whole. The tensile stress from the insulating adhesive layer generated by the difference in thermal expansion can be reduced.

  That is, it is possible to reduce the warpage that the surface of the multilayer wiring board that is generated due to the difference in thermal expansion becomes a concave shape, and it is possible to reduce the height variation due to the board warpage when mounting a chip such as a semiconductor element with a bump. Thus, the connection reliability of the bumps can be improved.

  According to the multilayer wiring board of the present invention, preferably, the area occupied by the non-formed part is gradually increased from the central part to the outer peripheral part of the insulating adhesive layer, so that it increases from the central part to the corner part of the board. The tensile stress due to heat shrinkage of the insulating adhesive layer can be reduced more effectively. Therefore, the warpage of the multilayer wiring board can be further reduced, and a sufficient pressure can be applied when a chip such as a semiconductor element is mounted on the central portion of the outermost layer of the multilayer wiring board by bumps.

According to the multilayer wiring board of the present invention, the non-formation portions adjacent in the stacking direction of the insulation layer since the staggered so as not to overlap in a plan perspective, further stress warping caused by thermal expansion difference Can be reduced.

  That is, when the non-formed portions adjacent to each other in the stacking direction of the insulating layers are overlapped with each other in plan view, the tensile stress generated in the lower layer is added to the tensile stress generated in the lower layer. Although the warpage is large, it is possible to disperse the tensile stress as the stress for each layer by arranging the non-formed portions adjacent to each other in the stacking direction of the insulating layers so as not to overlap each other as in the present invention, Ultimately, the total tensile stress applied to the multilayer wiring board can be reduced. Moreover, the non-formation part adjacent to the lamination direction of an insulating layer does not overlap, but the flatness of a surface layer can be improved.

  Therefore, even in a multilayer wiring board structure in which a resin insulating layer and a wiring conductor layer are stacked, the mounting reliability and the connection reliability of the wiring conductor layer of the multilayer wiring board are high, and the pitch of the wiring conductor layer can be reduced. It becomes a multilayer wiring board.

  Hereinafter, a multilayer wiring board of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a longitudinal sectional view showing an example of an embodiment of a multilayer wiring board according to the present invention. 2 and 3 are cross-sectional views of an insulating adhesive layer portion in various examples of embodiments of the multilayer wiring board of the present invention. 4A and 5A are longitudinal sectional views showing various examples of the embodiment of the multilayer wiring board of the present invention. FIGS. 4B and 5B are respectively shown in FIG. ) And FIG. 5A are cross-sectional views taken along the line XX of FIG. 4C, and FIG. 5C are the multilayer wiring boards of FIG. 4A and FIG. 5A, respectively. It is a cross-sectional view in the YY line.

  In these drawings, 1 is a substrate, 2 is an insulating layer, 3 is a wiring conductor layer, 4 is an insulating film layer as a part of the insulating layer 2, 5 is an insulating adhesive layer as a part of the insulating layer 2, 6 is a through conductor, 7 is a through hole, and 8 is a non-formed portion of the insulating adhesive layer.

  On the upper surface of the substrate 1, a multilayer wiring portion in which an insulating layer 2 (consisting of an insulating film layer 4 and an insulating adhesive layer 5) and a wiring conductor layer 3 are laminated in multiple layers is disposed. It functions as a support that supports the part.

  The substrate 1 is made of an oxide ceramic such as an aluminum oxide sintered body or a mullite sintered body, an aluminum nitride sintered body having an oxide film on its surface, or a non-oxide ceramic such as a silicon carbide sintered body. It is formed of an electrically insulating material such as a glass epoxy resin obtained by impregnating a glass fiber base material with an epoxy resin, or a glass fiber base material impregnated with a bismaleimide triazine resin.

  When the substrate 1 is formed of, for example, an aluminum oxide sintered body, an appropriate organic solvent or solvent is added to and mixed with raw material powders such as alumina, silica, calcia, and magnesia to form a slurry. A ceramic green sheet (ceramic green sheet) is formed by adopting a doctor blade method or a calender roll method, and thereafter, the ceramic green sheet is appropriately punched to obtain a predetermined shape and a high temperature (about 1600 ° C.). ). Alternatively, a raw material powder is prepared by adding and mixing an appropriate organic solvent and solvent to a raw material powder such as alumina, and the raw material powder is formed into a predetermined shape by a press molding machine. Finally, the compact is heated to a high temperature (about 1600 ° C. ). Moreover, when it consists of glass epoxy resins, it manufactures, for example by impregnating the base material which consists of glass fiber with the precursor of an epoxy resin, and thermosetting this epoxy resin precursor at predetermined temperature.

  The substrate 1 is provided with a multilayer wiring portion in which a plurality of insulating layers 2 and wiring conductor layers 3 are laminated in multiple layers on the upper surface thereof. The insulating layer 2 electrically insulates the wiring conductor layer 3 positioned above and below, and the wiring conductor layer 3 functions as a transmission path for transmitting an electrical signal.

  The insulating layer 2 of the multilayer wiring portion is composed of, for example, an insulating film layer 4 and an insulating adhesive layer 5, and the insulating film layer 4 is made of polyimide resin, polyphenylene sulfide resin, wholly aromatic polyester resin, fluororesin, or the like. Consists of. The insulating adhesive layer 5 is made of siloxane-modified polyamideimide resin, siloxane-modified polyimide resin, polyimide resin, bismaleimide triazine resin, or the like.

  The insulating layer 2 is prepared, for example, by first applying an insulating adhesive to an insulating film of about 12.5 to 50 μm to a dry thickness of about 5 to 20 μm using a doctor blade method or the like, and drying the insulating film. It is formed by stacking the film layer 4 so that the insulating adhesive layer 5 is disposed between the upper surfaces of the substrate 1 and the lower insulating layer 2, and heating and pressurizing the film layer 4 using a hot press device.

Also, the insulating layer 2 having a non-formation portion of the present invention, the absolute Enfu Irumu layer 4 to form a non-formation portion 8 of the insulating adhesive layer 5 by cutting or stamping or the like into a desired shape insulating The insulating layer 2 is formed by being disposed between the layers 2 and laminated. However, in the non-formed portion 8 of the insulating adhesive layer 5, the tensile stress generated by thermal contraction increases from the center portion to the corner portion of the substrate. 2 and 3, it is preferable to provide a large number of non-formed portions 8 at the corners and the outer periphery of the substrate. In addition, it is preferable to reduce the occupied area of the non-formed part or not to provide the non-formed part so that stress is sufficiently applied to the central part of the substrate when mounting a chip such as a semiconductor element.

Further, when the non-formed portion 8 has a circular shape or a complicated shape as shown in FIG. 3 or is formed with improved accuracy of vertical overlap as shown in FIGS. After the insulating adhesive layer 5 is temporarily laminated by a hot press apparatus, a resist pattern is formed so as to cover the portion other than the non-formed portion 8 using a photolithography method, and then a chemical etching method or a dry etching method is performed. The non-formation part 8 is formed by removing by etc. Thereafter, the resist pattern is removed, absolute Enfu Irumu layer 4 insulating layer 2 having a non-formation portion 8 by heat and pressure bonded by heat pressing apparatus stacked is formed.

The non-forming portion 8 of the insulating adhesive layer 5 is processed into a shape as shown in FIGS. 4B and 5C and FIGS. 5B and 5C, and FIGS. When the layers are stacked as in A), the adjacent non-formed portions of the insulating adhesive layer 5 are arranged so as not to overlap each other in the stacking direction (vertical direction), so that the tensile stress generated at the time of thermal shrinkage is different for each layer. Each stress can be dispersed, and the total tensile stress applied to the substrate can be finally reduced. Furthermore, since the non-formed portions which are adjacent in the vertical direction do not overlap, thereby improving the surface flatness.

Thus, by laminating the insulating layer 2 having the non-formed portion 8 to produce a multilayer wiring board, after being heated and pressed by a heating press device and bonded, the thermal expansion difference between the substrate 1 and the insulating adhesive layer 5 By reducing the tensile stress due to the difference in thermal shrinkage caused by the concave warpage can be reduced, and when mounting the chip with bumps, the height variation due to the warpage of the multilayer wiring board can be reduced, Bump connection reliability can be improved.

  As a combination of the insulating film layer 4 and the insulating adhesive layer 5 used for these, for example, there is a combination in which the insulating film layer 4 is a polyimide resin and the insulating adhesive layer 5 is a siloxane-modified polyamideimide resin. According to this combination, the adhesion between the siloxane-modified polyamideimide resin and the polyimide resin is good and the heat resistance is high, so that the multi-layer wiring board formed by these is resistant to being mounted on a printed board or the like. Good solder heat resistance and the like.

  As a combination with higher heat resistance, it is preferable to use the insulating film layer 4 as a polyimide resin and the insulating adhesive layer 5 as a thermoplastic polyimide resin having a melting point lower than that of the insulating film layer 4. In the case of this combination, the heat resistance is high and the stress due to the difference in linear expansion coefficient for reducing the difference in linear expansion coefficient between the insulating film layer 4 and the insulating adhesive layer 5 can be reduced. As a result, the stress that causes separation at the interface between the wiring conductor layer 3 and the through conductor 6 can be reduced. In addition, since it becomes possible to reduce the overall warpage of the multilayer wiring board, the multilayer wiring can better cope with the narrow pitch of the terminals of the semiconductor integrated circuit element mounted on the surface thereof. It can be a substrate.

  Further, each insulating layer 2 is provided with a wiring conductor layer 3 on the surface, and is provided on the insulating layer 2 in order to electrically connect the wiring conductor layers 3 positioned above and below the insulating layer 2. A through conductor 6 is embedded in the through hole 7. The wiring conductor layer 3 and the through conductor 6 employ a thin film forming technique such as sputtering, vapor deposition, plating, etc., of a metal material such as copper, gold, aluminum, nickel, chromium, molybdenum, titanium, and alloys thereof. Can be formed.

  The through conductors 6 may be formed separately from the wiring conductor layer 3, but it is preferable that these are formed at the same time in that the number of steps can be reduced, and also in terms of reliability of electrical connection between them. It will be good. In addition, when the wiring conductor layer 3 and the through conductor 6 are integrally formed, the wiring conductor layer 3 and the through conductor 6 are mainly formed by using an electrolytic plating method so that each of the wiring conductor layer 3 and the through conductor 6 can be formed to have a desired thickness. It is good to keep.

  As a method for forming the wiring conductor layer 3 and the through conductor 6, for example, first, the through hole 7 for the through conductor 6 is formed on the surface of the insulating layer 2. The through hole 7 is formed by removing the insulating layer 2 at a predetermined position using, for example, a laser. In particular, when the opening diameter of the through hole 7 is small, it is desirable to control the angle of the inner wall surface of the through hole 7 and to form the inner wall surface of the through hole 7 with an ultraviolet laser or the like that is processed smoothly. .

  Next, an underlying conductor layer composed of a diffusion prevention layer (barrier layer) made of chromium, molybdenum, titanium or the like and a copper layer mainly made of copper deposited thereon on the entire upper surface of the insulating layer 2 Is formed by electroless plating or sputtering. Then, a resist pattern is formed on the substrate 1 on which the base conductor layer is formed so as to cover the portion other than the portion that becomes the wiring conductor layer 3 by using a photolithography method, and then the wiring conductor layer 3 and the main conductor layer of the through conductor 6 are formed. The part is formed by electrolytic plating. Thereafter, the resist pattern is removed, and the excess base conductor layer covered with the resist pattern is removed by a chemical etching method, a dry etching method, or the like, thereby forming the wiring conductor layer 3.

  Further, the main conductor layer of the wiring conductor layer 3 formed on the surface of the insulating layer 2 which is the uppermost layer of the multilayer wiring board is made of a copper layer from the viewpoint of electrical characteristics and connection reliability. In this case, a nickel layer or a gold layer is preferably formed on the main conductor layer from the viewpoint of connection reliability and environmental resistance.

  It is not necessary to form the wiring conductor 3 for connecting a conductor bump or a probe directly above the through conductor 6 formed in the outermost insulating layer 2. In this case, the wiring conductor 3 is formed in the outermost insulating layer 2. A conductor bump or probe may be directly connected to the upper surface of the formed through conductor 6.

  Thus, according to the multilayer wiring board of the present invention, the semiconductor integrated circuit is formed on the top surface of the through conductor 6 exposed on the surface of the uppermost insulating layer 2 or on the wiring conductor layer 3 formed on the top surface of the through conductor 6. A semiconductor device is obtained by mounting conductor bumps and electrically connecting the multilayer wiring board to an external electric circuit.

  Alternatively, according to the multilayer wiring board of the present invention, the probe is connected to the upper surface of the through conductor 6 exposed on the surface of the uppermost insulating layer 2 or to the wiring conductor layer 3 formed on the upper surface of the through conductor 6. By fixing and fixing the multilayer wiring board electrically and mechanically to an external electric circuit, a probe card for conducting an electrical inspection of a semiconductor integrated circuit or the like is obtained.

It is a longitudinal cross-sectional view which shows an example of embodiment of the multilayer wiring board of this invention. It is a cross-sectional view of the insulating adhesive layer portion of the multilayer wiring board of FIG. It is a cross-sectional view of the insulating adhesive layer portion in another example of the embodiment of the multilayer wiring board of the present invention. (A) is a longitudinal sectional view showing another example of the embodiment of the multilayer wiring board of the present invention, (B) is a transverse sectional view of the multilayer wiring board of (A) taken along line XX, (C) is It is a cross-sectional view in the YY line of the multilayer wiring board of (A). (A) is a longitudinal sectional view showing another example of the embodiment of the multilayer wiring board of the present invention, (B) is a transverse sectional view of the multilayer wiring board of (A) taken along line XX, (C) is It is a cross-sectional view in the YY line of the multilayer wiring board of (A).

Explanation of symbols

1 ... substrate 2 ... insulating layer 3 .... wiring conductor layer 4 ... insulation Enfu Irumu layer 5 ... insulating adhesive layer 8 ....-free portion

Claims (3)

In a multilayer wiring board in which an insulating layer formed by laminating an insulating film layer and an insulating adhesive layer and a plurality of wiring conductor layers are alternately laminated, the insulating adhesive layer is not formed on the insulating layer. A multilayer wiring board characterized in that a plurality of portions are provided in a plurality of layers, and the non-formed portions adjacent to each other in the stacking direction of the insulating layers are arranged so as not to overlap each other in a plan view .   2. The multilayer wiring board according to claim 1, wherein the area occupied by the non-formed part is gradually increased from the central part to the outer peripheral part of the insulating adhesive layer. 2. The multilayer wiring board according to claim 1, wherein the central portion of the insulating adhesive layer has a reduced area occupied by the non-formed portion or is not provided with the non-formed portion.

Images