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JP4817835B2 - Wiring board - Google Patents
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JP4817835B2 - Wiring board - Google Patents

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JP4817835B2
JP4817835B2 JP2005367519A JP2005367519A JP4817835B2 JP 4817835 B2 JP4817835 B2 JP 4817835B2 JP 2005367519 A JP2005367519 A JP 2005367519A JP 2005367519 A JP2005367519 A JP 2005367519A JP 4817835 B2 JP4817835 B2 JP 4817835B2
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conductor
wiring board
layer
wiring
insulating
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JP2007173429A (en
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匡史 宮脇
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Kyocera Corp
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Kyocera Corp
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Description

本発明は配線基板に関し、より詳細には半導体集積回路素子を収容するための半導体素子収納用パッケージ等の電子部品収納用パッケージや、半導体集積回路等の電気的な検査をするためのプローブカード等に使用される配線基板に関するものである。   The present invention relates to a wiring board, and more specifically, an electronic component storage package such as a semiconductor element storage package for storing a semiconductor integrated circuit element, a probe card for electrical inspection of a semiconductor integrated circuit, etc. The present invention relates to a wiring board used in the above.

近年、半導体集積回路は半導体素子の高集積化および処理信号数の増加によって、半導体基板上に形成される端子数が増加するとともに端子の狭ピッチ化が進んでいる。これにより、半導体集積回路素子を収容する半導体素子収納用パッケージの接続端子や、半導体集積回路の電気的な検査を行なうプローブカードのプローブも狭ピッチ化が要求されている。   2. Description of the Related Art In recent years, in semiconductor integrated circuits, the number of terminals formed on a semiconductor substrate has increased and the pitch of terminals has been reduced due to higher integration of semiconductor elements and an increase in the number of processing signals. As a result, the pitch of the connection terminals of the package for housing the semiconductor element that houses the semiconductor integrated circuit element and the probe of the probe card that performs electrical inspection of the semiconductor integrated circuit is also required.

この狭ピッチ化の要求に対して、半導体素子収納用パッケージにおいては半導体素子の実装形態がワイヤボンディング接続からフリップチップ接続へ、またプローブカードは、カンチレバー方式のものからニードル状のプローブを細密に格子状に配置したものへと移り変わってきている。   In response to this demand for narrow pitches, in the package for housing semiconductor devices, the mounting form of the semiconductor devices is changed from wire bonding connection to flip chip connection, and the probe card is a cantilever type, and needle-like probes are finely latticed. It has changed to something arranged in a shape.

また、半導体の集積回路を形成するSiウエハーも歩留まり向上、コスト削減のために8インチサイズから12インチサイズのSiウエハーへの大型化が進んでおり、電気的な検査を行うプローブカードには、出来るだけ多くの数のチップを1回で測定できるように、プローブカードの測定エリアの大型化、つまりプローブカード上に搭載される測定プローブ付の配線基板の大型化が要求されている。   In addition, Si wafers forming semiconductor integrated circuits are also increasing in size from 8 inch size to 12 inch size Si wafers in order to improve yield and reduce costs. In order to be able to measure as many chips as possible at one time, it is required to increase the measurement area of the probe card, that is, to increase the size of the wiring board with the measurement probe mounted on the probe card.

また、それら半導体素子収納用パッケージやプローブカードに使われる配線基板の構成は、例えば、図4に示すように、セラミックから成る絶縁層11と配線導体層12とを交互に積層し、上下の配線導体層12同士を、絶縁層11に形成した貫通孔14に導体を充填して成る貫通導体13を介して電気的に接続したものであり、このような配線基板は、セラミックテープにAg、Cuから成るペーストをパターン形成して配線導体層12や貫通導体13を形成し、これを複数積層し、焼成することにより作製されていた。   In addition, as shown in FIG. 4, for example, as shown in FIG. 4, the structure of the wiring board used for the semiconductor element storage package or the probe card is formed by alternately laminating insulating layers 11 and wiring conductor layers 12 made of ceramic. The conductor layers 12 are electrically connected to each other through a through conductor 13 formed by filling a through hole 14 formed in the insulating layer 11 with a conductor. Such a wiring board is made of Ag, Cu, and ceramic tape. The wiring conductor layer 12 and the through conductor 13 are formed by patterning a paste made of the above, and a plurality of these are laminated and fired.

さらに近年の微細化の要求により、配線導体層12を狭ピッチ化するとともに、配線導体層12を細密な格子状に配置するために、樹脂から成る絶縁層11の上面にめっき法や気相成膜法等の薄膜形成技術およびフォトリソグラフィ技術を採用することによって薄膜の配線導体層12を形成させ、これを順次繰り返すことによって薄膜から成る配線導体層12を有する多層配線構造を形成することが提案されている。
特開2004−352547号公報 特開1999−163520号公報 特開1999−38044号公報
Furthermore, due to the recent demand for miniaturization, the wiring conductor layer 12 is narrowed in pitch, and the wiring conductor layer 12 is arranged in a fine lattice pattern so that the upper surface of the insulating layer 11 made of resin is plated or vapor-phase-formed. It is proposed to form a thin wiring conductor layer 12 by adopting a thin film forming technique such as a film method and a photolithography technique, and to form a multilayer wiring structure having the thin wiring conductor layer 12 by sequentially repeating this. Has been.
JP 2004-352547 A JP 1999-163520 A JP 1999-38044 A

しかしながら、セラミックテープを多層積層し、これを焼成してなるセラミック配線基板では、セラミック配線基板の大きさが大きくなればなるほど焼成した際に発生するセラミックの収縮によりプローブを配置する最表層の配線導体層であるパッドの位置がばらつくためプローブを一括配置することができない問題があった。   However, in a ceramic wiring board obtained by laminating ceramic tapes and firing them, the outermost wiring conductor on which the probe is arranged due to ceramic shrinkage that occurs when firing the larger the size of the ceramic wiring board There is a problem in that the probes cannot be arranged at a time because the positions of the pads as layers vary.

また、樹脂から成る絶縁層に薄膜の配線導体層を形成させ、これを順次繰り返して多層配線基板を構成使用とした場合でも、絶縁層と配線導体層とを逐次形成しているうちに絶縁層と配線導体層との収縮率が違いにより、導体部の位置ずれの影響が大きくなったり、配線基板が反るという問題があった。特に、配線基板を大きくすればするほど、その影響が大きく、大型の配線基板を形成するのは困難であった。   In addition, even when a thin wiring conductor layer is formed on an insulating layer made of resin and this is sequentially repeated to construct and use a multilayer wiring board, the insulating layer and wiring conductor layer are formed while the insulating layer and the wiring conductor layer are sequentially formed. Due to the difference in contraction rate between the wiring conductor layer and the wiring conductor layer, there has been a problem that the influence of the displacement of the conductor portion becomes large and the wiring board is warped. In particular, the larger the wiring board, the greater the effect, making it difficult to form a large wiring board.

本発明は上記のような背景技術における問題点に鑑みてなされたものであり、その目的は、配線基板の配線導体層の実装信頼性および接続信頼性が高く、配線基板の大型化と配線導体層の狭ピッチ化に対応することができる配線基板を提供することにある。   The present invention has been made in view of the problems in the background art as described above, and an object thereof is to provide high mounting reliability and connection reliability of the wiring conductor layer of the wiring board, and increase the size of the wiring board and the wiring conductor. An object of the present invention is to provide a wiring board that can cope with a narrow pitch of layers.

本発明の配線基板は、絶縁層と配線導体層とが交互に複数層積層されるとともに、上下に位置する前記配線導体層同士をそれらの間の前記絶縁層に形成した貫通導体を介して電気的に接続されて成る多層配線基板を複数個、前記絶縁に平行な方向に配列し、該複数の多層配線基板が配列されて成る多層配線基板集合体の少なくとも一方の主面に、絶縁基板の一主面から他主面にかけて導体が形成された1つの回路基板を前記複数の多層配線基板と重なるように積層し、前記各多層配線基板の前記配線導体層と前記導体とを電気的に接続したことを特徴とする。
In the wiring board of the present invention, the insulating layers and the wiring conductor layers are alternately laminated in a plurality of layers, and the wiring conductor layers positioned above and below are electrically connected via the through conductor formed in the insulating layer between them. the connected to the multilayer wiring board formed by a plurality, wherein arranged in the direction parallel to the insulating layer, on at least one major surface of the multilayer wiring board assembly said plurality of multi-layer wiring board are arrayed, the insulating substrate A circuit board having a conductor formed from one main surface to the other main surface is laminated so as to overlap the plurality of multilayer wiring boards, and the wiring conductor layer and the conductor of each multilayer wiring board are electrically connected to each other. It is connected.

本発明の配線基板において、好ましくは、前記回路基板は前記多層配線基板集合体の両主面に積層されており、一方の前記回路基板に形成された前記導体同士の前記絶縁に平行な方向の間隔が、他方の前記回路基板に形成された前記導体同士の前記絶縁に平行な方向の間隔よりも小さいことを特徴とする。
In the wiring board of the present invention, preferably, the circuit board is laminated on both main surfaces of the multilayer wiring board assembly, and the direction of the conductors formed on one of the circuit boards is parallel to the insulating layer. The distance between the conductors formed on the other circuit board is smaller than the distance between the conductors in the direction parallel to the insulating layer.

本発明の配線基板によれば、絶縁層と配線導体層とが交互に複数層積層されるとともに、配線導体層同士を貫通導体を介して電気的に接続されて成る多層配線基板を複数個、絶縁に平行な方向に配列し、この複数の多層配線基板が配列されて成る多層配線基板集合体の少なくとも一方の主面に、絶縁基板の一主面から他主面にかけて導体が形成された1つの回路基板を複数の多層配線基板と重なるように積層し、各多層配線基板の配線導体層と導体とを電気的に接続したことから、大型であるとともに狭ピッチで、反りの影響を抑えた配線基板を形成することができる。
According to the wiring board of the present invention, the insulating layers and the wiring conductor layers are alternately laminated in a plurality of layers, and a plurality of multilayer wiring boards formed by electrically connecting the wiring conductor layers to each other through the through conductors, arranged in a direction parallel to the insulating layer, on at least one major surface of the multilayer wiring board assembly the plurality of multi-layer wiring board are arrayed, the conductor is formed over the principal surface of one main surface of the insulating substrate One circuit board is stacked so as to overlap with multiple multilayer wiring boards, and the wiring conductor layers and conductors of each multilayer wiring board are electrically connected. A wiring board can be formed.

すなわち、多層配線基板のサイズを小さく形成することによって、配線基板作製時の熱収縮による反りを低減して、貫通導体の位置ズレの影響を少なくすることができるとともに、多層配線基板を複数個、絶縁に平行な方向に配列して成る多層配線基板集合体の上側および下側の少なくとも一方に、絶縁基板に精度よく導体を形成して成る回路基板を積層し、導体と配線導体とを電気的に接続することによって、導体の位置ズレの影響の非常に少ない狭ピッチ化された大型の配線基板を形成することができる。
That is, by reducing the size of the multilayer wiring board, it is possible to reduce the warp due to thermal shrinkage during the production of the wiring board, and to reduce the influence of the positional deviation of the through conductor, and a plurality of multilayer wiring boards, A circuit board formed by accurately forming a conductor on the insulating substrate is laminated on at least one of the upper side and the lower side of the multilayer wiring board assembly arranged in a direction parallel to the insulating layer , and the conductor and the wiring conductor are electrically connected. By connecting them together, it is possible to form a large-sized wiring board with a narrow pitch that is very little affected by the displacement of the conductor.

本発明の配線基板によれば、回路基板は多層配線基板集合体の両主面に積層されており、一方の回路基板に形成された導体同士の絶縁に平行な方向の間隔が、他方の回路基板に形成された導体同士の絶縁に平行な方向の間隔よりも小さいことから、配線基板に実装される部材のピッチに合わせて良好に接合することができる。
According to the wiring board of the present invention, the circuit board is laminated on both main surfaces of the multilayer wiring board assembly, and the interval in the direction parallel to the insulating layer between the conductors formed on one circuit board is the other. Since the distance in the direction parallel to the insulating layer between the conductors formed on the circuit board is smaller, it can be satisfactorily bonded according to the pitch of the members mounted on the wiring board.

すなわち、例えば半導体素子のような超微細なピッチから、プリント基板の大きいピッチなどの接続導体のピッチの違いによらず実装することができ、配線を展開することができる。   That is, for example, it can be mounted regardless of the difference in the pitch of the connecting conductors, such as a large pitch of the printed circuit board, from an ultrafine pitch such as a semiconductor element, and wiring can be developed.

よって、半導体チップやプリント配線板などの他部材との接続信頼性が高いとともにプローブの配列の狭ピッチ化に対応できる大型の配線基板となる。   Therefore, it becomes a large-sized wiring board that has high connection reliability with other members such as a semiconductor chip and a printed wiring board and can cope with a narrow pitch of the arrangement of probes.

以下、図面に基づいて本発明の多層配線基板を詳細に説明する。   Hereinafter, a multilayer wiring board of the present invention will be described in detail with reference to the drawings.

図1(a)は本発明の配線基板の実施の形態の一例を示す平面図であり、図1(b)は図1(a)のA−A’における断面図である。また、図2は図1に示す配線基板に平面方向に配列される多層配線基板の要部拡大断面図である。さらに、図3(a)は本発明の配線基板の実施の形態の他の例を示す平面図であり、図3(b)は図3(a)のB−B’における断面図である。これらの図において、1は絶縁層、2は配線導体層、3は貫通導体、4は貫通孔、5は配列される多層配線基板、6は接着層、7は上部の絶縁基板,8は下部の絶縁基板、9は回路基板、11は導体を示している。   FIG. 1A is a plan view showing an example of an embodiment of a wiring board according to the present invention, and FIG. 1B is a cross-sectional view taken along line A-A ′ of FIG. FIG. 2 is an enlarged cross-sectional view of a main part of the multilayer wiring board arranged in the plane direction on the wiring board shown in FIG. FIG. 3A is a plan view showing another example of the embodiment of the wiring board of the present invention, and FIG. 3B is a cross-sectional view taken along the line B-B ′ of FIG. In these drawings, 1 is an insulating layer, 2 is a wiring conductor layer, 3 is a through conductor, 4 is a through hole, 5 is a multilayer wiring board arranged, 6 is an adhesive layer, 7 is an upper insulating board, and 8 is a lower part Insulating substrate 9, 9 is a circuit board, and 11 is a conductor.

図2に示す本発明の配線基板に配列される多層配線基板5は、複数の絶縁層1と配線導体層2とを多層に積層し多層構造を形成しており、上下の配線導体層2同士は、貫通導体3により電気的に接続されている。   A multilayer wiring board 5 arranged on the wiring board of the present invention shown in FIG. 2 has a multilayer structure in which a plurality of insulating layers 1 and wiring conductor layers 2 are laminated in a multilayer structure. Are electrically connected by a through conductor 3.

絶縁層1は、低温焼成ガラスセラミックス,酸化アルミニウム質焼結体,ムライト質焼結体等の酸化物系セラミックス、表面に酸化物膜を有する窒化アルミニウム質焼結体,炭化珪素質焼結体等の非酸化物系セラミックス、ガラス、ポリイミド樹脂、エポキシ樹脂等の樹脂、ガラス繊維から成る基材にエポキシ樹脂を含浸させたガラスエポキシ樹脂、あるいはガラス繊維から成る基材にビスマレイミドトリアジン樹脂を含浸させたもの等の電気絶縁材料から成る。   The insulating layer 1 is made of oxide ceramics such as low-temperature fired glass ceramics, aluminum oxide sintered bodies, mullite sintered bodies, aluminum nitride sintered bodies having an oxide film on the surface, silicon carbide sintered bodies, etc. Non-oxide ceramics such as glass, polyimide resin, epoxy resin, glass epoxy resin impregnated with glass fiber base material, or glass fiber base material impregnated with bismaleimide triazine resin Made of electrically insulating material such as

絶縁層1が、例えば酸化アルミニウム質焼結体から成る場合、酸化アルミニウム,酸化珪素,酸化マグネシウム,酸化カルシウム等のセラミック原料粉末に適当な有機バインダ,溶剤を添加混合して泥漿状となすとともに、これをドクターブレード法等を採用してシート状となすことにより複数枚のセラミックグリーンシートを得て、しかる後、セラミックグリーンシートを切断加工や打ち抜き加工により適当な形状とするとともにこれを複数枚積層し、最後にこの積層されたセラミックグリーンシートを還元雰囲気中、約1600℃の温度で焼成する。   When the insulating layer 1 is made of, for example, an aluminum oxide sintered body, an appropriate organic binder and solvent are added to and mixed with ceramic raw material powders such as aluminum oxide, silicon oxide, magnesium oxide, and calcium oxide to form a slurry. A plurality of ceramic green sheets are obtained by using a doctor blade method or the like to obtain a sheet, and then the ceramic green sheets are formed into an appropriate shape by cutting or punching, and a plurality of these are laminated. Finally, the laminated ceramic green sheets are fired at a temperature of about 1600 ° C. in a reducing atmosphere.

また、絶縁層1が、例えば低温焼成ガラスセラミックスから成る場合には、例えば上述の酸化アルミニウム質焼結体から成る場合の製作法において主成分の原料粉末にアルミナ,ガラスを用い、約900℃で焼成する。   Further, when the insulating layer 1 is made of, for example, a low-temperature fired glass ceramic, alumina, glass is used as a main component raw material powder in a manufacturing method in the case of the above-described aluminum oxide sintered body, for example, at about 900 ° C. Bake.

このような絶縁層1には貫通導体3により充填された貫通孔4が形成されている。貫通孔4は、絶縁層1の一部をレーザ、ブラスト、ドリル、エッチング等で除去することにより形成される。そして、貫通孔4の内部をスパッタリング法や真空蒸着法、めっき法等を用いてあるいは金属粉末に有機溶剤,樹脂バインダ等を添加して作製した金属ペーストを、貫通孔4の内部に印刷塗布,充填することにより形成される。また、配線導体層2は絶縁層1の表面に、スパッタリング法や真空蒸着法、めっき法、印刷塗布方法等により形成される。   In such an insulating layer 1, a through hole 4 filled with a through conductor 3 is formed. The through hole 4 is formed by removing a part of the insulating layer 1 by laser, blast, drill, etching or the like. Then, a metal paste prepared by adding an organic solvent, a resin binder or the like to the metal powder using a sputtering method, a vacuum deposition method, a plating method, or the like inside the through hole 4 is printed and applied to the inside of the through hole 4. It is formed by filling. Further, the wiring conductor layer 2 is formed on the surface of the insulating layer 1 by a sputtering method, a vacuum evaporation method, a plating method, a printing application method, or the like.

このようにして、絶縁層1に配線導体層2、貫通孔4,貫通導体3を形成し、複数枚積層することにより多層配線基板5を得る。   In this way, the wiring conductor layer 2, the through hole 4, and the through conductor 3 are formed in the insulating layer 1, and a multilayer wiring board 5 is obtained by laminating a plurality of sheets.

多層配線基板5の表層の配線導体層2の形成方法は、例えば、絶縁層1の上面の全面に、クロム,モリブデン,チタン等から成る拡散防止層(バリア層)とその上に被着された主に銅から成る銅層とで構成された下地導体層を無電解めっき法やスパッタリング法等によって形成する。そして、下地導体層が形成された絶縁層1をフォトリソグラフィ法を用いて配線導体層2となる部分以外を覆うようにレジストパターンを形成した後、配線導体層2の主導体層の部分を、電解めっき法にて形成する。その後、レジストパターンを除去し、レジストパターンにより覆われていた余分な下地導体層をケミカルエッチング法やドライエッチング法等にて除去することにより配線導体層2が形成される。   The formation method of the surface wiring conductor layer 2 of the multilayer wiring board 5 is, for example, a diffusion prevention layer (barrier layer) made of chromium, molybdenum, titanium, etc., and deposited on the entire upper surface of the insulating layer 1. A base conductor layer mainly composed of a copper layer made of copper is formed by an electroless plating method, a sputtering method, or the like. Then, after forming a resist pattern so as to cover the insulating layer 1 on which the base conductor layer is formed using a photolithography method so as to cover portions other than the portion that becomes the wiring conductor layer 2, the main conductor layer portion of the wiring conductor layer 2 is It is formed by electrolytic plating. Thereafter, the resist pattern is removed, and the excess underlying conductor layer covered with the resist pattern is removed by a chemical etching method, a dry etching method, or the like, thereby forming the wiring conductor layer 2.

本発明の図1、図3に示す配線基板は、多層配線基板5を複数個、層方向(絶縁層1に平行な方向)に配列し、その上側および下側の少なくとも一方に回路基板9を接着層6により積層することにより形成される。   The wiring board shown in FIGS. 1 and 3 of the present invention has a plurality of multilayer wiring boards 5 arranged in a layer direction (a direction parallel to the insulating layer 1), and a circuit board 9 is provided on at least one of the upper side and the lower side thereof. It is formed by laminating with the adhesive layer 6.

接着層6は、例えば、シロキサン変性ポリアミドイミド樹脂,シロキサン変性ポリイミド樹脂,ポリイミド樹脂,ビスマレイミドトリアジン樹脂、シリカやアルミナ等を主成分にした無機接着剤等で接着し、Ag、Cu、Au、Su、Su−Ag、Su−Cu、Su−Ag−Cu、Au−Snなどの金属ペーストで電気的な接続する構成や、異方性導電性樹脂から成る。   The adhesive layer 6 is bonded with, for example, a siloxane-modified polyamideimide resin, a siloxane-modified polyimide resin, a polyimide resin, a bismaleimide triazine resin, an inorganic adhesive mainly composed of silica or alumina, and the like. Ag, Cu, Au, Su , Su-Ag, Su-Cu, Su-Ag-Cu, Au-Sn and other metal pastes, or an anisotropic conductive resin.

接着層6は、例えば、接続と接着を同時に行える異方性導電性樹脂でも良いが、樹脂材料ではシロキサン変性ポリアミドや、無機接着剤により接着すると耐熱性が高いものとなるため、半導体チップやプリント板を実装する際の耐半田実装性が良好なものとなる。   The adhesive layer 6 may be, for example, an anisotropic conductive resin that can be connected and bonded simultaneously. However, since the resin material has high heat resistance when bonded with siloxane-modified polyamide or an inorganic adhesive, it can be used for semiconductor chips and prints. Good solder resistance when mounting the board.

回路基板9は、絶縁基板7,8の一主面から他主面にかけて導体11が形成されている。そして、回路基板9の表面に形成された導体11の一部から成る導体層11bが、導体11の一部から成るとともに絶縁基板7,8を貫通して成るビア導体11aを介して多層配線基板5の表面に形成された配線導体層2に電気的に接続されている。   The circuit board 9 has a conductor 11 formed from one main surface to the other main surface of the insulating substrates 7 and 8. A conductor layer 11b formed of a part of the conductor 11 formed on the surface of the circuit board 9 is formed of a part of the conductor 11 and via a via conductor 11a penetrating the insulating substrates 7 and 8 to form a multilayer wiring board. 5 is electrically connected to the wiring conductor layer 2 formed on the surface of 5.

このような回路基板9は、絶縁基板7,8と導体層11bとが交互に積層されたものであってもよいが、絶縁基板7,8および導体層11bが多層になるほど、導体11の位置精度が低下するため、導体11の位置精度を向上させるという観点からは、導体層11bの層数は多層配線基板5の配線導体層2の総数よりも少ない方がよく、より好ましくは、回路基板9は多層構造ではなく、単層の絶縁基板7,8の表層に導体層11bが形成され、この導体層11bがビア導体11aを介して配線導体層2に接続されるのがよい。   Such a circuit board 9 may be one in which the insulating substrates 7 and 8 and the conductor layer 11b are alternately laminated. However, as the insulating substrates 7 and 8 and the conductor layer 11b are multilayered, the position of the conductor 11 is increased. Since the accuracy is lowered, from the viewpoint of improving the positional accuracy of the conductor 11, the number of the conductor layers 11b is preferably smaller than the total number of the wiring conductor layers 2 of the multilayer wiring board 5, and more preferably, the circuit board. 9 is not a multilayer structure, but a conductor layer 11b is formed on the surface layer of the single-layer insulating substrates 7 and 8, and this conductor layer 11b is preferably connected to the wiring conductor layer 2 via the via conductor 11a.

この1つの回路基板9を複数の多層配線基板5と重なるように積層し、各多層配線基板5の配線導体層2と導体11とをロウ材等によって電気的に接続することにより、大型であるとともに狭ピッチで、反りの影響を抑えた配線基板を形成することができる。   The one circuit board 9 is laminated so as to overlap with the plurality of multilayer wiring boards 5, and the wiring conductor layer 2 and the conductor 11 of each multilayer wiring board 5 are electrically connected by a brazing material or the like, thereby increasing the size. At the same time, it is possible to form a wiring board with a narrow pitch and suppressing the influence of warpage.

すなわち、多層配線基板5のサイズを小さく形成することによって、配線基板作製時の熱収縮による反りを低減して、貫通導体3の位置ズレの影響を少なくすることができるとともに、多層配線基板5を複数個、層方向に配列して成る多層配線基板集合体の上側および下側の少なくとも一方に、絶縁基板7,8に精度よく導体11を形成して成る回路基板9を積層し、導体11と配線導体2とを電気的に接続することによって、導体11の位置ズレの影響の非常に少ない狭ピッチ化された大型の配線基板を形成することができる。   That is, by reducing the size of the multilayer wiring board 5, it is possible to reduce warpage due to thermal shrinkage during the production of the wiring board and to reduce the influence of the positional deviation of the through conductor 3. A circuit board 9 formed by accurately forming conductors 11 on the insulating substrates 7 and 8 is laminated on at least one of the upper side and the lower side of the multilayer wiring board assembly that is arranged in the layer direction. By electrically connecting the wiring conductor 2, it is possible to form a large-sized wiring board with a narrow pitch with little influence of the positional deviation of the conductor 11.

このような回路基板9は、例えば、酸化アルミニウム焼結体である絶縁基板7,8に貫通孔10を形成後、めっきや導体11(ビア導体11aおよび導体層11b)を形成することによって形成される。この際、ビア導体11aは導体層11bと別々に形成してもよいが、これらは同時に形成した方が、工程数を少なくできる点で好ましいものとなるとともに、両者の電気的な接続信頼性の点でも良好なものとなる。また、導体層11bとビア導体11aとを一体的に形成する場合には、それぞれを所望の厚みに調整してめっき膜で形成することができるように、主として電解めっき法を用いて形成しておくのがよい。   Such a circuit board 9 is formed, for example, by forming a through hole 10 in the insulating substrates 7 and 8 which are aluminum oxide sintered bodies, and then forming a plating or a conductor 11 (via conductor 11a and conductor layer 11b). The At this time, the via conductor 11a may be formed separately from the conductor layer 11b. However, it is preferable to form these at the same time because the number of steps can be reduced, and the electrical connection reliability between the two is improved. It is also good in terms. Further, when the conductor layer 11b and the via conductor 11a are integrally formed, the conductor layer 11b and the via conductor 11a are mainly formed by using an electroplating method so that each of the conductor layers 11b and the via conductors 11a can be adjusted to a desired thickness. It is good to leave.

このように任意の位置に絶縁基板7,8の一主面から他主面にかけて形成した導体11を有する回路基板9を、複数個配列された多層配線基板集合体の上側や下側に接着層6により積層し、導体11と配線導体層2とをロウ材等で電気的な接続を行なうことで、大型であるにもかかわらず、反りや収縮の影響がきわめて少なく、狭ピッチに配列可能な大型の配線基板を形成することが可能となり、導体バンプやプローブの配列の狭ピッチ化、導体バンプやプローブの一括配列に対応することができる。   As described above, the circuit board 9 having the conductor 11 formed from one main surface to the other main surface of the insulating substrates 7 and 8 at an arbitrary position is bonded to the upper side and the lower side of the multilayer wiring board assembly in which a plurality are arranged. 6, and the conductor 11 and the wiring conductor layer 2 are electrically connected with a brazing material or the like, so that the influence of warpage and shrinkage is extremely small and the arrangement can be made at a narrow pitch despite the large size. A large-sized wiring board can be formed, and it is possible to cope with a narrow pitch of the arrangement of conductor bumps and probes and a collective arrangement of conductor bumps and probes.

なお、回路基板9の絶縁基板7に形成されたビア導体11aの直上には、図1(b)のように、導体バンプやプローブを接続するための導体層11bを形成しなくともよく、その場合、絶縁基板7に形成されたビア導体11aの上面に直接導体バンプやプローブを接続すればよい。   It is not necessary to form a conductor layer 11b for connecting a conductor bump or a probe as shown in FIG. 1 (b) immediately above the via conductor 11a formed on the insulating substrate 7 of the circuit board 9. In this case, a conductor bump or probe may be directly connected to the upper surface of the via conductor 11a formed on the insulating substrate 7.

また、配線基板の最表層となる絶縁基板7の表面に形成される導体層11bは、複数層からなっていてもよく、そのような複数層の導体層11bを構成する主導体層は、電気的な特性や接続信頼性の観点から、銅層から成るものとすることがよく、また、その場合には接続信頼性および耐環境信頼性の観点から主導体層の上にニッケル層や金層を形成するとよい。   The conductor layer 11b formed on the surface of the insulating substrate 7 which is the outermost layer of the wiring board may be composed of a plurality of layers, and the main conductor layer constituting such a plurality of layers of the conductor layers 11b From the viewpoint of general characteristics and connection reliability, it should be made of a copper layer. In that case, a nickel layer or a gold layer is formed on the main conductor layer from the viewpoint of connection reliability and environmental reliability. It is good to form.

また、本発明の配線基板は、図3(a),(b)に示すように、回路基板が多層配線基板集合体の両主面に積層されており、絶縁基板7,8および絶縁層1の熱膨張係数が、一方の絶縁基板(図3では上の絶縁基板)7、絶縁層1、他方の絶縁基板(図3では下の絶縁基板)8の順に大きくなっているのがよい。これにより、配線基板の上部や下部に実装する部材が異なっても、熱による接合部への影響を少なくすることができ、実装信頼性を向上させることができる。
Further, as shown in FIGS. 3A and 3B, the circuit board 9 of the present invention has the circuit board 9 laminated on both main surfaces of the multilayer wiring board assembly, and the insulating boards 7 and 8 and the insulating layer. thermal expansion coefficient of 1, that one of the insulating substrate (insulating substrate of the upper portion in FIG. 3) 7, the insulating layer 1 is larger in the order of the other insulating substrate (insulating substrate under portion in FIG. 3) 8 Good. Thereby, even if the member mounted on the upper part or the lower part of the wiring board is different, it is possible to reduce the influence of the heat on the joint part and to improve the mounting reliability.

すなわち、例えば上部側に半導体素子、下部側に樹脂から成るプリント基板を実装した際に発生する熱膨張による部材の伸びにそれぞれ合わせることができ、熱による接合部への影響を少なくすることができることから、実装信頼性を向上させることができる。   That is, for example, it is possible to match the expansion of the member due to the thermal expansion that occurs when the semiconductor element is mounted on the upper side and the printed circuit board made of resin is mounted on the lower side, and the influence on the joint due to heat can be reduced Therefore, the mounting reliability can be improved.

また、本発明の配線基板は、図3(a),(b)に示すように、回路基板が多層配線基板集合体の両主面に積層されており、一方の回路基板(図3では上の絶縁基板)に形成された導体11同士の層方向の間隔(図3では横方向の間隔)が、他方の回路基板(図3では下の絶縁基板)に形成された導体11同士の層方向の間隔(図3では横方向の間隔)よりも小さくなっているのがよい。これにより、配線基板に実装される部材のピッチに合わせて良好に接合することができる。
In addition, as shown in FIGS. 3A and 3B, the wiring board of the present invention has a circuit board 9 laminated on both main surfaces of a multilayer wiring board assembly, and one circuit board (in FIG. 3). insulating substrate) to form conductors 11 layer direction of the distance between the upper portion (lateral spacing in FIG. 3) is the other of the circuit board (conductor 11 formed on the insulating substrate) of the lower portion in FIG. 3 with each other It is preferable to be smaller than the interval in the layer direction (interval in the horizontal direction in FIG. 3). Thereby, it can join favorably according to the pitch of the member mounted in a wiring board.

すなわち、例えば半導体素子のような超微細なピッチから、プリント基板の大きいピッチなどの接続導体のピッチの違いによらず実装することができ、配線を展開することができる。   That is, for example, it can be mounted regardless of the difference in the pitch of the connecting conductors, such as a large pitch of the printed circuit board, from an ultrafine pitch such as a semiconductor element, and wiring can be developed.

よって、半導体チップやプリント配線板などの他部材との接続信頼性が高いとともにプローブの配列の狭ピッチ化に対応できる大型の配線基板となる。   Therefore, it becomes a large-sized wiring board that has high connection reliability with other members such as a semiconductor chip and a printed wiring board and can cope with a narrow pitch of the arrangement of probes.

かくして、本発明の配線基板によれば、最表層の絶縁基板7の表面に露出したビア導体層11aの上面に、または、ビア導体11aの上面に形成された導体層11bに半導体集積回路の導体バンプを実装するとともに、下部の絶縁基板8の表面に露出したビア導体11aの下面に、または、ビア導体11aの下面に形成された導体層11bと外部電気回路を電気的に接続することによって半導体装置となる。   Thus, according to the wiring board of the present invention, the conductor of the semiconductor integrated circuit is formed on the upper surface of the via conductor layer 11a exposed on the surface of the outermost insulating substrate 7 or on the conductor layer 11b formed on the upper surface of the via conductor 11a. A semiconductor is mounted by mounting bumps and electrically connecting a conductor layer 11b formed on the lower surface of the via conductor 11a exposed on the surface of the lower insulating substrate 8 or the lower surface of the via conductor 11a and an external electric circuit. It becomes a device.

あるいは、本発明の配線基板によれば、最表層の絶縁基板7の表面に露出したビア導体11aの上面に、または、ビア導体11aの上面に形成された導体層11bにプローブを接続し、固定するともに、下部の絶縁基板8の表面に露出したビア導体11aの下面に、または、ビア導体11aの下面に形成された導体層11bと外部電気回路を電気的および機械的に接続することによって、半導体集積回路等の電気的な検査をするためのプローブカードとなる。   Alternatively, according to the wiring board of the present invention, the probe is connected to the upper surface of the via conductor 11a exposed on the surface of the outermost insulating substrate 7 or the conductor layer 11b formed on the upper surface of the via conductor 11a and fixed. In addition, by electrically and mechanically connecting the conductor layer 11b formed on the lower surface of the via conductor 11a exposed on the surface of the lower insulating substrate 8 or the lower surface of the via conductor 11a and an external electric circuit, The probe card is used for electrical inspection of a semiconductor integrated circuit or the like.

上記本発明の配線基板の大きさは、例えば一辺が100mm〜500mmの四角形状のものに良好に適用可能であり、この配線基板を構成する多層配線基板5の大きさは、例えば一辺が50mm〜100mmの四角形状のものであり、このような多層配線基板5を層方向に縦横に配列させ、これらの多層配線基板集合体の少なくとも一方の主面に1つの回路基板9が接合されている。   The size of the wiring board of the present invention can be suitably applied to a rectangular shape having a side of 100 mm to 500 mm, for example, and the size of the multilayer wiring board 5 constituting this wiring board is, for example, 50 mm to a side. The multilayer wiring board 5 has a rectangular shape of 100 mm. Such a multilayer wiring board 5 is arranged vertically and horizontally in the layer direction, and one circuit board 9 is bonded to at least one main surface of the multilayer wiring board aggregate.

なお、本発明は、上述の実施形態に限定されるものではなく、本発明の要旨を逸脱しない範囲であれば種々の変更は可能である。   In addition, this invention is not limited to the above-mentioned embodiment, A various change is possible if it is a range which does not deviate from the summary of this invention.

(a)は本発明の配線基板の実施の形態の一例を示す平面図、(b)は(a)のA−A’における断面図である。(A) is a top view which shows an example of embodiment of the wiring board of this invention, (b) is sectional drawing in A-A 'of (a). 図1に示す配線基板に平面方向に配列される多層配線基板の要部拡大断面図である。FIG. 2 is an enlarged cross-sectional view of a main part of a multilayer wiring board arranged in a planar direction on the wiring board shown in FIG. 1. (a)は本発明の配線基板の実施の形態の他の例を示す平面透視図、(b)は(a)のB−B’における断面図である。(A) is a plane perspective view which shows the other example of embodiment of the wiring board of this invention, (b) is sectional drawing in B-B 'of (a). 従来の配線基板の断面図である。It is sectional drawing of the conventional wiring board.

符号の説明Explanation of symbols

1・・・・絶縁層
2・・・・配線導体層
3・・・・貫通導体
4・・・・貫通孔
5・・・・多層配線基板
6・・・・接着層
7・・・・上部の絶縁基板
8・・・・下部の絶縁基板
DESCRIPTION OF SYMBOLS 1 ... Insulating layer 2 ... Wiring conductor layer 3 ... Through conductor 4 ... Through hole 5 ... Multilayer wiring board 6 ... Adhesive layer 7 ... Upper part Insulating substrate 8 ··· Lower insulating substrate

Claims (2)

絶縁層と配線導体層とが交互に複数層積層されるとともに、上下に位置する前記配線導体層同士をそれらの間の前記絶縁層に形成した貫通導体を介して電気的に接続されて成る多層配線基板を複数個、前記絶縁層に平行な方向に配列し、該複数の多層配線基板が配列されて成る多層配線基板集合体の少なくとも一方の主面に、絶縁基板の一主面から他主面にかけて導体が形成された1つの回路基板を前記複数の多層配線基板と重なるように積層し、前記各多層配線基板の前記配線導体層と前記導体とを電気的に接続したことを特徴とする配線基板。   A plurality of layers in which insulating layers and wiring conductor layers are alternately stacked, and the wiring conductor layers positioned above and below are electrically connected via a through conductor formed in the insulating layer between them A plurality of wiring boards are arranged in a direction parallel to the insulating layer, and at least one main surface of the multilayer wiring board assembly formed by arranging the plurality of multilayer wiring boards is arranged from one main surface of the insulating substrate to the other main surface. One circuit board on which a conductor is formed over the surface is laminated so as to overlap the plurality of multilayer wiring boards, and the wiring conductor layer and the conductor of each multilayer wiring board are electrically connected. Wiring board. 前記回路基板は前記多層配線基板集合体の両主面に積層されており、一方の前記回路基板に形成された前記導体同士の前記絶縁層に平行な方向の間隔が、他方の前記回路基板に形成された前記導体同士の前記絶縁層に平行な方向の間隔よりも小さいことを特徴とする請求項1記載の配線基板。   The circuit board is laminated on both main surfaces of the multilayer wiring board assembly, and the distance between the conductors formed on one of the circuit boards in a direction parallel to the insulating layer is formed on the other circuit board. The wiring board according to claim 1, wherein an interval between the formed conductors in a direction parallel to the insulating layer is smaller.
JP2005367519A 2005-12-21 2005-12-21 Wiring board Expired - Fee Related JP4817835B2 (en)

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