JP4617832B2 - Semiconductor integrated circuit design method - Google Patents

Description

  The present invention relates to a method for designing a semiconductor integrated circuit using junction isolation (JI) or self-isolation (SI).

In a semiconductor integrated circuit in which a plurality of semiconductor elements are laid out on the surface layer portion of a p-conductivity type semiconductor substrate using JI or SI, a surge such as a negative input is applied to the n-conductivity type region of the semiconductor element connected to the external terminal. Then, the n conductivity type region is forward biased with respect to the p conductivity type semiconductor substrate. For this reason, electrons are injected from the n conductivity type region into the p conductivity type semiconductor substrate. Usually, since the p-conductivity type semiconductor substrate has a low impurity concentration of about 1 × 10 ¹⁵ / cm ³ , electrons injected into the p-conductivity type semiconductor substrate substrate become an electron current without recombining with holes. It diffuses into the substrate.

  Here, consider the case where there is a regular NPN transistor adjacent to the external terminal as the semiconductor element constituting the integrated circuit. When the electron current diffused into the substrate by the surge reaches the normal transistor via a parasitic bipolar transistor that is inevitably generated in a semiconductor integrated circuit using JI or SI, the normal current is normal even if the normal transistor is in an off state. Current flows through the collector of the transistor. When the collector current generated by the inflow of the electron current is large, a potential drop due to an external resistance connected to the collector occurs, the normal transistor changes from the off state to the on state, and the circuit including the normal transistor malfunctions. . Even if the normal transistor does not completely reverse from the off state to the on state, the output current of the normal transistor fluctuates, affecting the input of the next-stage transistor and further amplifying it to propagate noise. As a result, the entire circuit is adversely affected.

As a means for preventing such circuit malfunction, for example, in Proceedings of 2004 ISPSD & ICs, pp.423-426 (Non-patent Document 1), a parasitic element such as an n-conducting well is formed around a regular semiconductor element connected to an external terminal. A method of forming a guard ring for prevention is disclosed. By fixing the n conductivity type well at a high potential, the electron current injected into the semiconductor substrate by the surge can be absorbed. Japanese Patent Application Laid-Open No. 11-145308 (Patent Document 1) discloses a method of performing a design rule check (DRC) based on CAD (Computer Aided Design) data and laying out a guard ring without a gap.
Proceedings of 2004 ISPSD & ICs, pp.423-426 JP 11-145308 A

  Although the above-described method of absorbing the electron current due to the surge in the guard ring can reduce the influence of the surge to some extent, it does not necessarily guarantee the prevention of malfunction of the integrated circuit. This is because the analysis method of the parasitic bipolar transistor has not been established yet. Therefore, until now, the guard ring has been placed at places where it is likely to occur empirically, such as the input / output section, and the verification of the effect of including the guard ring has been evaluated by making a trial product chip. However, this method is very inefficient, because it is necessary to repeat layout correction that involves changing the design of all layers of the mask, such as further increasing the distance between the semiconductor elements if the malfunction is still not resolved, and this reduces the product cost. It is an obstacle.

  Therefore, the present invention is a method for designing a semiconductor integrated circuit using JI or SI, which can analyze in advance the effects of a parasitic bipolar transistor, the effect of putting a guard ring against surges, etc. by simulation, thereby reducing the product cost. It is an object of the present invention to provide a method for designing a semiconductor integrated circuit that can be used.

The invention according to claim 1 is a method for designing a semiconductor integrated circuit using junction isolation or self-isolation , wherein a plurality of semiconductor elements constituting the integrated circuit are laid out on a CAD in a surface layer portion of a semiconductor substrate. From the first step and the layout diagram on the CAD, the input / output protection element directly connected to the external terminal and the second semiconductor element adjacent to the input / output protection element among the plurality of semiconductor elements are analyzed. Of the write output protection element and the second semiconductor element, an n-type region of the input / output protection element is used as an emitter, an n-conductivity type region of the second semiconductor element is used as a collector, and the input / output protection element a second step of extracting the p conductivity type region parasitic NPN bipolar transistor based on the between the second semiconductor element, the parasitic NPN bipolar bets The circuit parameters of Njisuta, a third step of further extracting the device simulator, incorporates NPN bipolar transistor of the parasitic to the integrated circuit, the parasitic NPN bipolar when inputting a surge more the external terminals to the circuit simulator and a method of designing a semiconductor integrated circuit; and a fourth step of performing a motion analysis error due to latch-up transistor.

The method of designing a semiconductor integrated circuit, in a parasitic bipolar transistor which inevitably occur in advance semiconductor integrated circuit using a JI or SI, large parasitic bipolar transistor effect against a surge input to the external terminals, namely Among the plurality of semiconductor elements constituting the integrated circuit, an input / output protection element directly connected to an external terminal and a second semiconductor element adjacent to the input / output protection element are analyzed, and the input / output protection element and the first Among the two semiconductor elements, an n-type region of the input / output protection element is used as an emitter, an n-conductivity type region of the second semiconductor element is used as a collector, and the input / output protection element and the second semiconductor element the p-type conductivity region between and limited to a parasitic NPN bipolar transistor based quantitatively grasp the impact, the parasitic NPN bi The operation error due to latch-up of the parasitic NPN bipolar transistor when the input surge like negative input and ESD (Electro Static Discharge) to the external terminal at the integrated circuit over La transistor is incorporated, before the product chip prototype Evaluate in advance .
According to the above-described semiconductor integrated circuit design method, it is possible to efficiently perform the operation verification of the semiconductor integrated circuit without repeating prototype evaluation of a product chip, and to efficiently lay out a plurality of semiconductor elements constituting the integrated circuit. because it can be, thereby making it possible to reduce the product cost.

In the semiconductor integrated circuit design method, the analysis time can be shortened by limiting the parasitic bipolar transistors that affect the circuit operation as described above. Further, in the method of designing a semiconductor integrated circuit, with respect to malfunction analysis incorporating parasitic NPN bipolar transistor, the device simulator rather uses a circuit simulator that can be done more quickly. Therefore, the evaluation time can be shortened also by this, and the product cost can be reduced.

In the semiconductor integrated circuit design method, for example, as described in claim 2, the second semiconductor element is a logic element including a P-channel MOS transistor and an N-channel MOS transistor, and the logic element is a power supply. In the case where the p-conduction type region directly connected to the external terminal is included, in the second step, the p-conduction type region in the logic element is used as an emitter among the input / output protection element and the logic element. In the third step, a parasitic PNP bipolar transistor based on an n conductivity type region between the logic element and the input / output protection element is further extracted using the p conductivity type region in the input / output protection element as a collector, , The circuit parameters of the parasitic PNP bipolar transistor Extracted with regulator, in the fourth step, in addition to the NPN bipolar transistor of the parasitic further incorporate PNP bipolar transistor of the parasitic to the integrated circuit, the at the time of inputting the surge to the external terminals by a circuit simulator It is possible to perform a malfunction analysis by latch-up of the parasitic NPN bipolar transistor and the parasitic PNP bipolar transistor.

In the semiconductor integrated circuit, the parasitic NPN bipolar transistor and the parasitic PNP bipolar transistor are inevitably generated in a semiconductor integrated circuit using JI or SI in a malfunction analysis in which a surge is input to an external terminal. Among the parasitic bipolar transistors, it is a parasitic bipolar transistor having a large influence adjacent to the external terminal. By limiting the parasitic bipolar transistors that affect the circuit operation in this way, the analysis time can be shortened, thereby reducing the product cost.

As described in claim 3, in the method of designing a semiconductor integrated circuit, for example, the semiconductor substrate may be a p-type conductivity der Ru configuration.

As described in claim 4, in malfunction analysis enter a surge to the external terminal, for example, the input protection device is a MOS transistor, said external terminal, and the drain of the MOS transistor Can do.

As claimed in claims 5 to 7, wherein when a malfunction in the fourth step occurs, the performs voltage clamp between the input and output protection device and the second semiconductor element, and the input protection device first The malfunction can be eliminated by changing the layout such as increasing the distance between the two semiconductor elements and inserting an n-conducting guard ring between the input / output protection element and the second semiconductor element.

  In this case, by incorporating any one of the layout changes described above and performing the analysis according to claim 1 again, the effect of the layout change on the surge can be simulated without making a product chip as a prototype. Therefore, according to the above-mentioned semiconductor integrated circuit design method, it is possible to guarantee the prevention of malfunction of the semiconductor integrated circuit against a surge without producing a trial product chip, and to reduce the product cost.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

  FIG. 1 is a design flowchart relating to a method for designing a semiconductor integrated circuit according to the present invention.

  The semiconductor integrated circuit design method shown in FIG. 1 basically includes four steps S1 to S4. In the first step S1, a plurality of semiconductor elements constituting the integrated circuit are laid out on the CAD in the surface layer portion of the semiconductor substrate. That is, CAD data (position, size, shape) of each conductivity type region is input to a plurality of semiconductor elements constituting the integrated circuit, and the plurality of semiconductor elements are laid out on the CAD. In addition, the attributes (surface concentration, diffusion depth) of each conductivity type region are also input, and a three-dimensional chip model is created on the device simulator (TCAD). Note that a dummy layer (external dummy) representing the attribute is inserted on the CAD in the semiconductor element connected to the external terminal. In the second step S2, parasitic bipolar transistors other than normal semiconductor elements are extracted from the layout diagram on the CAD. In the third step S3, circuit parameters of the parasitic bipolar transistor are extracted by TCAD. That is, device calculation (for example, Ic-Ib characteristics) of a parasitic bipolar transistor is performed, and circuit parameters used for a circuit simulator (SPICE) are extracted from the obtained waveform. In the fourth step S4, the parasitic bipolar transistor is incorporated in the integrated circuit, and the circuit operation analysis is performed by SPICE. That is, the extracted parasitic bipolar transistor is incorporated into a normal circuit, and normal circuit operation verification is performed, and a surge waveform assuming a negative input is input to an external terminal, and circuit operation verification is performed.

  If it is confirmed in the fourth step S4 that no malfunction occurs, the process proceeds to a trial production of the product chip. If a malfunction occurs in the fourth step, the process returns to the first step S1, and layout corrections such as fixing the substrate potential, expanding the element spacing, and inserting a guard ring are performed, and the steps are repeated until the malfunction is resolved. .

  According to the design method of the semiconductor integrated circuit shown in FIG. 1, the influence of the parasitic bipolar transistor inevitably generated in the semiconductor integrated circuit using JI or SI is quantitatively grasped, and the parasitic bipolar transistor is incorporated. The circuit operation can be evaluated in advance before trial production of the product chip. Therefore, a plurality of semiconductor elements constituting an integrated circuit can be efficiently laid out without repeating trial evaluation of product chips, thereby reducing product costs.

  In the above-mentioned semiconductor integrated circuit design method, SPICE that can be performed in a shorter time is used instead of TCAD for circuit operation analysis incorporating a parasitic bipolar transistor. Therefore, the evaluation time can be shortened also by this, and the product cost can be reduced.

  Next, specific examples of the method for designing the semiconductor integrated circuit shown in FIG. 1 will be described.

  FIG. 2 is an example of the first step S1 and the second step in FIG. 2A is a schematic plan view showing the semiconductor integrated circuit 101 laid out on the CAD, and FIG. 2B is a cross-sectional view taken along the alternate long and short dash line AA in FIG. is there.

  In the semiconductor integrated circuit 101 of FIG. 2A, as semiconductor elements constituting the integrated circuit, an external element dummy (input / output protection diode) 11 surrounded by a broken line, a MOS transistor dummy (P channel and N channel MOS transistor) 12, A power element dummy 13 and a bipolar transistor dummy (NPN transistor) 14 are shown. In FIG. 2A, hatched mesh portions indicate contact contacts to the n conductivity type region and the p conductivity type region, and square mesh portions in the power element dummy 13 are formed with cells of the power element. Indicates the area.

  A large number of parasitic bipolar transistors can be extracted from the semiconductor integrated circuit 101 shown in FIG. In the semiconductor integrated circuit 101 of FIG. 2A, the semiconductor substrate is p-conductivity type, but when a parasitic NPN transistor is taken as an example, for example, the n-conductivity region in the external element dummy 11 directly connected to the external terminal is used as the emitter. The NPN transistor Q1 in FIG. 2B is based on the n conductivity type region in the bipolar transistor dummy 14 adjacent to the external element dummy 11 as a collector and the p conductivity type region (p conductivity type semiconductor substrate) of the external element dummy 11 as a base. Is extracted. In addition to the parasitic NPN transistor Q1, the semiconductor integrated circuit 101 in FIG. 2A also includes a parasitic NPN transistor having the n conductivity type region of the power element dummy 13 as an emitter, and an n conductivity type in the MOS transistor dummy 12. A parasitic NPN transistor having a region as a collector can be extracted.

  3 and 4 show another semiconductor integrated circuit 102. FIG. 3 is a schematic plan view showing the semiconductor integrated circuit 102 laid out on the CAD, and FIG. 4 is a cross-sectional view taken along one-dot chain line BB in FIG.

  In the semiconductor integrated circuit 102 of FIG. 3, an input / output protection element 21 and a logic element (P-channel and N-channel MOS transistor) 22 surrounded by a broken line are shown as semiconductor elements constituting the integrated circuit. The input / output protection element 21 uses a MOS transistor, and the drain of the MOS transistor is directly connected to an external terminal.

  From the semiconductor integrated circuit 102 shown in FIG. 3, as a parasitic bipolar transistor, a logic element (P-channel MOS transistor) adjacent to the input / output protection element 21 with the n conductivity type region in the input / output protection element 21 directly connected to the external terminal as an emitter. ) 22 is extracted, and the NPN transistor Q2 of FIG. 4 based on the p conductivity type region (p conductivity type semiconductor substrate) of the input / output protection element 21 is extracted. As another parasitic bipolar transistor, in the input / output protection element 21 adjacent to the logic element (P channel MOS transistor) 22, the p conductivity type region in the logic element (P channel MOS transistor) 22 directly connected to the external terminal is used as an emitter. The PNP transistor Q3 shown in FIG. 4 can be extracted based on the n conductivity type region of the logic element (P channel MOS transistor) 22 using the p conductivity type region as a collector.

  The two parasitic bipolar transistors Q2 and Q3 are adjacent to the external terminal among the parasitic bipolar transistors inevitably generated in a semiconductor integrated circuit using JI or SI in a malfunction analysis in which a surge is input to the external terminal. It is a parasitic bipolar transistor that has a great influence. The malfunction analysis when a surge is input to the external terminal using the semiconductor integrated circuit 102 shown in FIGS. 3 and 4 will be described later. By limiting the parasitic bipolar transistors that affect the circuit operation in this way, Analysis time can be shortened, thereby reducing product costs.

  As described above, the parasitic bipolar transistor can be extracted from the layout diagram on the CAD according to the designer's judgment. On the other hand, the designer's judgment material regarding this parasitic bipolar transistor is made into a database of design rules, and by using the design rule check (DRC), the extraction of the parasitic bipolar transistors in the second step S2 of FIG. 1 can be automated. Thereby, the design time of the semiconductor integrated circuit can be further shortened, and the product cost can be reduced.

  Next, the third step S3 and subsequent steps in FIG. 1 will be described by taking, as an example, a malfunction analysis when a surge is input to the external terminal of the semiconductor integrated circuit 102 in FIG.

  When a malfunction is analyzed by inputting a surge to the external terminal, an external dummy layer is assigned to the external terminal in the first step S1 of FIG. This facilitates simulation analysis using TCAD.

  FIG. 5 shows an example of the execution result of the third step S3 in FIG.

  FIG. 5A is a current amplification characteristic (Gummel plot) of a parasitic PNP transistor simulated using TCAD. FIG. 5B shows SPICE circuit parameters of the parasitic PNP transistor extracted from the Gummel plot of FIG. 5A using commercially available general-purpose software.

  FIG. 6 shows an example of the implementation result of the fourth step S4 in FIG. 1 for the semiconductor integrated circuit 102 shown in FIGS. FIG. 6A is an equivalent circuit diagram incorporating the parasitic bipolar transistor of FIG. A portion surrounded by a broken line in the figure shows an equivalent circuit of an ESD surge.

  FIG. 6B shows the result of malfunction analysis incorporating the parasitic bipolar transistor of FIG. The influence of the surge applied by ESD is reduced to about 200 ns, but then the parasitic bipolar transistor latches up, and a current of 1.4 A constantly flows.

  If it can be confirmed in the fourth step S4 of FIG. 1 that no malfunction occurs, the process proceeds to a trial production of a product chip. However, in FIG. 6B, since the parasitic bipolar transistor is latched up, the layout is corrected again by returning to the first step S1 in FIG.

  7 and 8 show the semiconductor integrated circuit 103 after layout correction. FIG. 7 is a schematic plan view showing the semiconductor integrated circuit 103 laid out on the CAD, and FIG. 8 is a cross-sectional view taken along one-dot chain line CC in FIG.

  In the semiconductor integrated circuit 103 shown in FIGS. 7 and 8, compared with the semiconductor integrated circuit 102 shown in FIGS. 3 and 4, in order to prevent latch-up of the parasitic bipolar transistor, the input / output protection element 21 and the logic element (P Between the channel MOS transistors) 22, a potential fixing 23 surrounded by a dotted line in the figure is added.

  FIG. 9 shows an implementation result of the fourth step S4 in FIG. 1 for the semiconductor integrated circuit 103 shown in FIGS. FIG. 9A is an equivalent circuit diagram incorporating the parasitic bipolar transistor of FIG.

  FIG. 9 (b) shows the result of malfunction analysis incorporating the parasitic bipolar transistor of FIG. 9 (a). The potential is fixed 23 between the input / output protection element 21 and the logic element (P-channel MOS transistor) 22, and a path through which surge current due to ESD is removed is added. In FIG. 9B, compared to FIG. 6B. The occurrence of malfunction (latch-up) due to the parasitic bipolar transistor is prevented.

  7 to 9, when a malfunction occurs in the fourth step S4 in FIG. 1, the first semiconductor element directly connected to the external terminal and the second semiconductor element adjacent to the first semiconductor element are not connected. The layout change to fix the potential 23 is shown. However, the present invention is not limited to this, and the layout is such that the interval between the first semiconductor element and the second semiconductor element is increased, and an n-conducting guard ring is inserted between the first semiconductor element and the second semiconductor element. The malfunction can be eliminated by the change.

  As described above, according to the semiconductor integrated circuit design method of the present invention shown in FIG. 1, whether or not there is a malfunction due to a surge such as a negative input or ESD (Electro Static Discharge) is evaluated in advance before the trial production of the product chip. Can do. Therefore, it is possible to efficiently verify the operation of the semiconductor integrated circuit without repeating the trial evaluation of the product chip, thereby reducing the product cost.

It is a design flowchart regarding the design method of the semiconductor integrated circuit of the present invention. FIG. 1A is a schematic plan view showing a semiconductor integrated circuit 101 laid out on a CAD, and FIG. 1B is an example of the first step S1 and the second step in FIG. It is sectional drawing in the dashed line AA. It is a typical top view which shows another semiconductor integrated circuit laid out on CAD. It is sectional drawing in the dashed-dotted line BB in FIG. FIG. 1A is an example of the implementation result of the third step S3 in FIG. 1, where FIG. 1A shows current amplification characteristics of a parasitic PNP transistor simulated using TCAD, and FIG. 1B shows a parasitic PNP transistor extracted from FIG. SPICE circuit parameters. FIG. 1A is an example of the result of the fourth step S4 in FIG. 1. FIG. 4A is an equivalent circuit diagram in which the parasitic bipolar transistor in FIG. 4 is incorporated, and FIG. It is the result of analysis. It is a typical top view which shows the semiconductor integrated circuit laid out on CAD after layout correction. It is sectional drawing in the dashed-dotted line CC in FIG. (A) is an equivalent circuit diagram incorporating the parasitic bipolar transistor of FIG. 8, and (b) is the result of malfunction analysis incorporating the parasitic bipolar transistor of (a).

Explanation of symbols

S1 to S4 Steps in design flow 101 to 103 Semiconductor integrated circuit 11 to 14, 21 and 22 (regular) semiconductor elements Q1 to Q3 Parasitic bipolar transistor 23 Potential fixing

Claims (7)

A method of designing a semiconductor integrated circuit using junction isolation or self-isolation,
A plurality of semiconductor elements constituting the integrated circuit at the surface layer of a semiconductor substrate, a first step of laying on CAD,
From the layout diagram on the CAD, an input / output protection element directly connected to an external terminal among the plurality of semiconductor elements and a second semiconductor element adjacent to the input / output protection element are analyzed.
Of the input / output protection element and the second semiconductor element, an n-type region of the input / output protection element is used as an emitter, and an n-conductivity type region of the second semiconductor element is used as a collector. A second step of extracting a parasitic NPN bipolar transistor based on a p-conductivity type region between the first and second semiconductor elements ;
The circuit parameters of the NPN bipolar transistor of the parasitic, a third step of further extracting the device simulator,
Incorporating the NPN bipolar transistor of the parasitic to the integrated circuit, to a fourth step of performing a motion analysis error due to latch-up of the parasitic NPN bipolar transistor when the input surge more the external terminals to the circuit simulator A method of designing a semiconductor integrated circuit. The second semiconductor element is a logic element including a P-channel MOS transistor and an N-channel MOS transistor;
The logic element has a p-conductivity type region directly connected to an external terminal of a power source;
In the second step, out of the input / output protection element and the logic element, the p conductivity type region in the logic element is used as an emitter, and the p conductivity type region in the input / output protection element is used as a collector, A parasitic PNP bipolar transistor based on an n-conductivity type region between the input / output protection elements is further extracted;
In the third step, circuit parameters of the parasitic PNP bipolar transistor are extracted by a device simulator,
In the fourth step, the parasitic NPN bipolar transistor when the parasitic PNP bipolar transistor is further incorporated in the integrated circuit in addition to the parasitic NPN bipolar transistor and a surge is input to the external terminal by a circuit simulator. 2. The method of designing a semiconductor integrated circuit according to claim 1, wherein malfunction analysis is performed by latch-up of the parasitic PNP bipolar transistor. The semiconductor substrate, a method of designing a semiconductor integrated circuit according to claim 1 or 2, wherein the Ru p conductivity type der. The input / output protection element is a MOS transistor;
Said external terminals, a method of designing a semiconductor integrated circuit according to any one of claims 1 to 3, characterized in that the drain of the MOS transistor. If the malfunction in the fourth step occurs, between the input and output protection device and the second semiconductor element, a semiconductor according to any one of claims 1 to 4, characterized in that the voltage clamp Integrated circuit design method. If the malfunction in the fourth step occurs, the design of the semiconductor integrated circuit according to any one of claims 1 to 4, characterized in that widening the interval of the input protection device and the second semiconductor element Method. If the malfunction in the fourth step occurs, between the input and output protection device and the second semiconductor element, any one of claims 1 to 4, characterized in that inserting the n conductivity type guard ring one A method for designing a semiconductor integrated circuit according to the item.

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