JPH0770688B2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a semiconductor integrated circuit device, and more particularly to preventing a latch-up phenomenon.

(Prior Art) In the integrated circuit market in recent years, IC memory has achieved rapid growth,
In particular, over the past few years, the market for read-only memory (EPROM), which is erasable by ultraviolet light and electrically writable, has shown a dramatic expansion. Due to the demand for large capacity, high speed, low power consumption, and low price with the expansion of this market, there has been a remarkable movement to reduce power consumption by using peripheral CMOS.

(Problems to be Solved by the Invention) Conventionally, it has been difficult to form an EPROM into CMOS. The reason is that high voltage is required for programming, and
When writing, a substrate current of about several milliamps flowed. This is because that can cause a "latch-up phenomenon", which is a problem peculiar to CMOS circuits, in which a large current is caused to flow between the power supplies and even destruction of the device occurs. In addition, the "latch-up phenomenon" may occur even when the speed is increased. Due to the increase in operating speed, rapid charging and discharging will be performed at the output terminal, and due to the capacitance, resistance, and inductor attached to the output terminal, overshoot and undershoot of the output potential, The ringing occurs, and the radical fluctuations in the ringing generate a substrate current, which induces a “latch-up phenomenon”.

The present invention has been made in view of the above problems, and an object of the present invention is to increase the latch-up resistance of a semiconductor integrated circuit device including a complementary element type circuit without increasing the pattern occupying area. It is to provide a circuit device.

[Configuration of the Invention] (Means for Solving the Problems) In order to achieve the above object, in a first aspect of the present invention, a semiconductor substrate of a first conductivity type is provided in the vicinity of one peripheral portion of the substrate. First circuit block for arranging the input circuit including the protection circuit, and at least a complementary element for arranging the peripheral circuit of the input circuit, which is provided adjacent to the first circuit block. A second circuit block including a pattern circuit, and a third circuit block provided adjacent to the second circuit block and including at least a complementary element type circuit for arranging a peripheral circuit of the memory circuit, A fourth circuit block, which is provided adjacent to the third circuit block and includes at least a memory element, for arranging the memory circuit, and a high circuit provided adjacent to the fourth circuit block. Voltage circuit A fifth circuit block including at least a complementary element type circuit and a high voltage element, and at least a complementary circuit for arranging a peripheral circuit of the output circuit provided adjacent to the fifth circuit block. A sixth circuit block including an element type circuit and the sixth circuit block
A seventh circuit including at least a complementary element type circuit for arranging the output circuit, which is provided adjacent to the circuit block in the vicinity of the other peripheral edge portion of the substrate facing the one peripheral edge portion.
Circuit block. Then, a well region of the second conductivity type for obtaining a complementary element type circuit included in the output circuit is arranged on the other peripheral edge side of the substrate, and a pad for giving output data from the output circuit to an external output terminal. Between the second conductivity type element and the second conductivity type element that form the complementary element type circuit included in the output circuit, and between the second, third, fifth, sixth, and seventh circuit blocks, The feature is that elements of the same conductivity type are arranged adjacent to each other.

According to a second aspect of the present invention, the storage circuit is provided adjacent to other sides of the fourth circuit block in which the storage circuit is arranged, other than the sides respectively adjacent to the third and fifth circuit blocks. An eighth circuit block including at least a complementary element type circuit for arranging other peripheral circuits of the circuit is further provided. Further, between the eighth circuit block including the complementary element type circuit and the fourth circuit block, elements of the same conductivity type are arranged adjacent to each other.

Further, in a third aspect of the present invention, the storage element included in the storage circuit is a non-volatile memory element capable of rewriting data, and the non-volatile memory element is at least a substrate current when rewriting data. Associated with the non-volatile memory element, the non-volatile memory element is adjacent to the fourth circuit block in which the memory circuit is disposed and the circuit block adjacent to the fourth circuit block. It is characterized by having done.

Further, in a fourth aspect of the present invention, in the high voltage system circuit, of the one conductivity type element and the other conductivity type element included in the complementary element type circuit of the high voltage system circuit, the same conductivity type as the high voltage element. This element is arranged adjacent to the high voltage element of this high voltage system circuit.

According to a fifth aspect of the present invention, when the storage element included in the storage circuit and the high voltage element included in the high voltage system circuit are both of one conductivity type, the high voltage element and the storage circuit are arranged. Another one-conductivity-type element is further arranged between the fourth circuit block and the fourth circuit block.

The sixth aspect of the present invention is characterized in that, of the peripheral circuits of the memory circuit, the decoder is arranged in at least the eighth circuit block.

(Operation) In the semiconductor integrated circuit device having the first to sixth aspects, when each circuit block having a different function includes a complementary element type circuit, adjacent circuit parts of the circuit blocks are of the same conductivity type. By arranging the elements adjacent to each other, the areas for obtaining the other conductivity type elements are separated from each other, and by separating these areas, the substrate resistance between these areas is increased, and the parasitic NPN transistor and the parasitic P
It is difficult for the NP transistor to conduct. Therefore, the latch-up phenomenon that occurs particularly in the complementary element type circuit can be suppressed.

Moreover, in the semiconductor integrated circuit device having the first to sixth aspects, since the elements of the same conductivity type are arranged adjacent to each other in the adjacent portions of the circuit blocks, in order to increase the substrate resistance, It also reduces the size of each circuit block and the need to increase the spacing between them.
Therefore, the latch-up phenomenon can be suppressed more effectively without increasing the pattern occupation area.

(Embodiment) FIG. 1A is a pattern plan view of an embodiment of the present invention in the output circuit 21. The N-channel transistor group 1 and the P-channel transistor group 2 are arranged so as to sandwich the bonding aluminum pad 22 connected to the output terminal.

In a circuit that consumes a large amount of current, such as an output circuit, and in a circuit that is easily affected by external noise as an external terminal, either in the N-channel transistor section or the P-channel transistor section. , It is easy to induce the substrate current that causes latch-up.

Therefore, as shown in FIG. 1 (a), the N-channel transistor 1 is arranged inside the chip with respect to the bonding pad 22 connected to the external output terminal, and the outside, that is, the end (termination) e of the chip. The P-channel transistor 2 is arranged on the side. By arranging the P-channel transistor 2 on the end e side of the chip in this way, the pad region 22 is separated from the internal circuit. Therefore, even when the substrate current, which is the cause of the latch-up, is generated, the substrate resistance increases due to the distance from the internal circuit, so that the base current due to the parasitic bipolar transistor is limited. By that,
It is possible to increase the resistance to up.

FIGS. 1 (b) to (g) are sectional views of FIG. 1 (a), in which 23 is a P-type substrate, 24 is an N well layer, VCC is a power supply end, VSS is a ground end, and 25 ₁ 25 ₂ and 30 are N ⁺ layer, 26 N
Polysilicon electrode of channel transistor group 1, 27 is P
Polysilicon electrodes of channel transistor group 2, 28 ₁ to 2
8 ₂ and 29 are P ⁺ layers, Tr ₁ is a P ⁺ layer 28 ₁ , N well 24, P substrate 23
Parasitic PNP bipolar transistor, Tr ₂ is P ⁺ layer 28
_2. Parasitic PNP bipolar transistor consisting of N well 24 and P substrate 23, Tr ₃ is N well 24 and P substrate 23, parasitic NPN bipolar transistor consisting of N ⁺ layer 25 ₁ , Tr ₄ is N well 24 and P substrate
23, consisting of the N ⁺ layer 25 ₂ parasitic NPN bipolar transistor, r
_{1 to} r ₃ are N well parasitic resistances, and r _{4 to} r ₇ are P substrate parasitic resistances.

A method of suppressing the latch-up phenomenon will be described below with reference to FIGS. 1 (b) to (g) based on an example of the latch-up phenomenon. In FIG. 1 (b), the power supply voltage is applied to the external output terminal 22.
The case where noise in the positive direction above VCC is mixed will be described. At this time, the base of the parasitic PNP bipolar transistor Tr ₂ remains biased to the power supply VCC through the well parasitic resistances r ₁ and r ₂ , so that Tr ₂ is turned on, and the P substrate parasitic resistances r ₅ and r ₆ , A current i ₁ flows through r ₇ to the ground terminal VSS. By the flow of this current i ₁ ,
A potential gradient is generated in the P substrate 23, and P substrate parasitic resistances r ₅ , r ₆ and r ₇
A potential difference is generated at both ends of each. Thereby, the base of the parasitic NPN bipolar transistor Tr ₄ is forward biased and Tr ₄ is turned on. Therefore, as shown in FIG. 1 (c), it passes through the well parasitic resistances r ₁ , r ₂ , r ₃ ,
Current i ₂ flows. In addition, this current i ₂ flows
Ends to the potential effects of the well parasitic resistance r ₂ in which the base of the PNP bipolar transistor Tr ₁ is connected occurs, by lower than the power supply voltage VCC, based Tr ₁ becomes forward biased, Tr ₁ is turned on, FIG. 1 as shown in (d) P substrate parasitic resistance r _4, through _{r 5, r 6, r 7} , to the ground terminal VSS, current i
₃ flows. By the flow of this current i _3, the base of the parasitic NPN bipolar transistor Tr ₄ is further forward biased, and the current i ₂ increases. By repeating the above operation, the current continues to flow from the power supply VCC to the grounding terminal VSS even if the noise mixed in the external output terminal 22 subsides, and this state continues until the power is turned off.This is the latch-up phenomenon. . In addition, the power supply voltage VCC is temporarily reduced by the influence of other external output circuits (for example, about 4,5V) and becomes the power supply voltage VCC level voltage (for example, 5V) at the external output terminal 22. In this case, the well parasitic resistances r ₁ and r ₂
Since the base of the parasitic PNP bipolar transistor Tr ₂ is forward biased and turned on, the current i ₁ flows as shown in FIG. 1B, and the same operation as described above is repeated, so that the latch-up phenomenon occurs. Next, in FIG. 1 (e),
A case where noise in the negative direction equal to or lower than the ground end voltage VSS is mixed into the external output end 22 will also be described. At this time, since the base is biased to the ground potential via the P substrate parasitic resistances r ₆ and r ₇ , the parasitic NPN bipolar transistor Tr ₃ is turned on and passes through the well parasitic resistances r ₁ , r ₂ and r ₃ , Electric current
i ₄ flows. The flow of this current i ₄ causes the N well
A potential gradient occurs in 24, a potential drop occurs at the connection point of the well resistors r ₁ and r ₂ , the base of the parasitic PNP bipolar transistor Tr ₁ becomes forward biased, and Tr ₁ turns on. As a result, a current i ₅ flows through the P substrate parasitic resistances r ₄ , r ₅ , r ₆ , r ₇ to the ground terminal VSS as shown in FIG. 1 (f). When the current i ₅ flows in the P substrate 23, a potential gradient is also generated in the P substrate 23, the base of the parasitic NPN bipolar transistor Tr ₄ is forward biased, and Tr ₄ is turned on. Therefore, well parasitic resistance
A current i ₆ flows through r ₁ , r ₂ , and r ₃ as shown in FIG. 1 (g). Since this current i ₆ flows, the potential gradient in the N well 24 becomes large, and the parasitic PNP bipolar transistor Tr ₁
The base of is further forward biased and the current i ₅ increases.
By repeating the above-described operation, similarly to the above, even when the noise is suppressed, a latch-up phenomenon occurs in which a current continues to flow between the power supplies. Also, ground end VSS
However, due to the influence of other external output circuits etc., the ground terminal voltage temporarily floats (for example, about 0.5), and when the external output terminal 22 is at the ground terminal voltage VSS level voltage (for example, OV), the P substrate Since the base of the parasitic NPN bipolar transistor Tr ₃ is forward biased and turned on via the parasitic resistances r ₆ and r ₇ , a current i ₄ flows as shown in FIG. 1 (e), and the same operation as above is repeated. , Latch-up phenomenon occurs. From the above, it is understood that the cause of the latch-up phenomenon is that the substrate current or the well current flows, and the potential gradient due to the parasitic resistance of the substrate or the well forward biases the base of the parasitic bipolar transistor. On the other hand, a method of preventing the occurrence of the latch-up phenomenon is to control the parasitic resistance, that is, the parasitic resistance is reduced by a guard ring or the like to suppress the potential gradient. There are two methods of increasing the parasitic resistance to suppress the substrate current or the well current itself. In the output circuit 21 which is an embodiment of the present invention, the distance between the N-channel transistor group 1 and the P-channel transistor group 2 is increased to increase the parasitic substrate resistance, suppress the substrate current, and suppress the occurrence of the latch-up phenomenon. To do.

Further, as shown in the present invention, on the P-type substrate 23,
Placing the N-well region having a conductivity type opposite to that of the substrate on the terminal side of the chip further makes latch-up less likely to occur. Latch-up is peculiar to CMOS integrated circuits and does not occur in NMOS or PMOS integrated circuits.
In a CMOS integrated circuit, latch-up occurs because a transistor is formed in a well region having a conductivity type opposite to that of a substrate. That is, the main cause of latch-up is the transistor on the well region, and latch-up does not occur without this well region. For this reason, the distance between the well region in which the transistor connected to the output terminal where latch-up is likely to occur and other internal circuits is further increased. As in the present invention, if the well region in which the transistor connected to the output terminal is formed is arranged on the terminal side of the chip, there is no other circuit on the terminal side, and the chip is finished. Therefore, for latch-up, only the inside of the chip, that is, only one side of the well region and the other internal circuits need to be arranged separately, and therefore, on the chip for forming the output circuit. The advantage is that the area of the well can be made small, and since other circuits are placed only on one side of the well region, latch-up is less likely to occur.

FIG. 2 shows an embodiment of the present invention in which a peripheral circuit adjacent to the output circuit 21 is arranged. The N-channel transistor group 3 in the circuit 31 of the peripheral circuit is arranged on the output circuit 21 side,
The P-channel transistor group 4 in 31 is arranged on the opposite side of the output circuit 21 with respect to the N-channel transistor group 3. This means that in the N-channel transistor group 1 in the output circuit connected to the outside, Even when the substrate current is generated by its own operation or external noise, the substrate current that directly causes the latch-up is as shown in FIG. 2 with respect to the N-channel transistor group 1 of the output circuit 21. Interposing the N-channel transistor group 3 of the internal circuit 31,
By arranging the P-channel transistor group 4 of the internal circuit 31, the substrate resistance from the N-channel transistor group 1 of the output circuit 21 to the P-channel transistor group 4 of the internal circuit 31 increases, and it becomes difficult for the substrate current to flow. That is, the N-channel transistor group 1 connected to the output terminal 22 where noise enters and the P-channel transistor group 4 are separated from each other so that the N-channel transistor group 3 is arranged. As a result, it is possible to improve the latch-up resistance without increasing the circuit occupation area.

FIG. 3 is an embodiment of the present invention in which peripheral circuits are arranged in the vicinity of the circuit 42 to which a high voltage is supplied. The N-channel transistor group 6 in the circuit 41 of the peripheral circuit is arranged on the high voltage circuit 42 side formed by the N-channel transistor group 5, and the P-channel transistor group 7 in the circuit 41 is The N-channel transistor group 6 is placed so as to be sandwiched and separated. For example, in an electrically rewritable read only memory (EPROM), when writing data to a memory element, a high voltage must be applied to its gate and drain. For that reason,
As a result, a circuit for generating a high voltage for writing must be arranged around the memory device. Therefore, there are problems such as field leakage due to the use of high voltage, field leakage due to parasitic field transistor, breakdown current due to breakdown phenomenon at PN junction, and resistance / capacitance / inductor incidental to high voltage wiring. Substrate current such as transient current due to internal chattering. Therefore, as shown in FIG. 3, the N-channel transistor group 6 in the peripheral circuit 41 is sandwiched by the N-channel transistor group 5 using the high voltage, and the P-channel transistor group 7 in the circuit 41 is arranged. As a result, even when the substrate current as described above occurs, the substrate current from the P-channel transistor region 7 of the circuit 41, which is the direct cause of latch-up, to the N-channel transistor region 5 of the high voltage circuit 42 Since the N-channel transistor group 6 of the circuit 41 is arranged in the circuit substrate, the substrate resistance increases, and it becomes difficult for the substrate current to flow. As a result, it is possible to improve the latch-up resistance. "That is, the high voltage circuit 42
Since the N-channel transistor group 5 may generate a substrate current, the N-well forming the P-channel transistor group 7 and the high-voltage N-channel transistor group 5 should be placed between the N-channel transistor group 6. By arranging them apart from each other, the substrate current in FIG. 1 (b) is increased without increasing the pattern occupying area to suppress the latch-up trigger current. FIG. 4 shows an embodiment of the present invention in which the peripheral circuit 52 is arranged close to the input circuit 51. The N-channel transistor group 9 in the peripheral circuit 52 is arranged on the input protection circuit side formed by the N-channel transistor group 8.
The P-channel transistor group 10 in the circuit 52 is arranged apart from the N-channel transistor group 9 with respect to the input protection circuit. Even if the input protection circuit is not made of MOS transistors but simply uses the junction breakdown between the N ⁺ semiconductor region and the substrate, if the N ⁺ region is arranged in this way, the same effect can be obtained. can get. In the CMOS semiconductor integrated circuit device, external noise and high voltage due to static electricity may be mixed into the input protection circuit and the input circuit 51 connected to the external input terminal. When external noise below the reference potential is supplied to the input terminal 53, or when a high voltage is applied to the input terminal and breakdown occurs in the input protection circuit, a current flows through the board and the current latches up. It will induce a phenomenon. Therefore, as shown in FIG. 4, by arranging the N-channel transistor region 9 between the P-channel transistor region 10 and the N-channel transistor region 8 of the input protection circuit, the input area can be increased without increasing the pattern occupation area. The protection circuit and the P-channel transistor region 10 can be separated from each other, increasing the substrate resistance and making it difficult for the substrate current to flow. The N-channel transistor group 8 connected to the input terminal 53 may generate a substrate current due to noise, so the P-channel transistor group 10 and the N-channel transistor group 10 are arranged apart from each other. As a result, it is possible to improve the latch-up resistance.

In addition, the input protection circuit or N connected to the input terminal 53
If the channel transistor group 8 is arranged on the terminal end side of the chip with respect to the pad, latch-up is further suppressed.

FIG. 5 shows an embodiment of the present invention in which a peripheral circuit 62 is arranged close to the semiconductor memory circuit 61. The N-channel transistor group 12 in the peripheral circuit 62 is the N-channel transistor group 11
The P-channel transistor group 13 in the circuit 62 is arranged on the side opposite to the semiconductor memory circuit 61 with respect to the N-channel transistor group 12. As described above, in EPROM, a high voltage must be applied to the gate and drain of the memory element when writing data to the semiconductor memory element. Upcoming
Due to the high integration of EPROM, the memory capacity has increased, and the time required to write data to all memory cells has become longer and longer. As a result, the conventional method of writing data at the pinch-off point of the memory element operation has come to perform writing in the avalanche region of the memory element operation in order to shorten the writing time. However, at this time, a substrate current of about several milliamperes flows through the substrate of the semiconductor memory element. This current causes the latch up. Therefore, as shown in FIG. 5, the P-channel transistor region 13 and the N-channel transistor region 11 are
And an N-channel transistor region 12 is disposed between and. As a result, the substrate resistance increases, and it becomes difficult for the substrate current to flow from the P-channel transistor region 13 to the N-channel transistor group 11 in the semiconductor memory circuit 61. As a result, it is possible to improve the latch-up resistance.

FIG. 6 shows a schematic view of a chip 81 of a semiconductor integrated circuit device made according to the embodiment of the invention. In FIG. 6, the portion surrounded by the chain line 71 is the output circuit described in FIGS. 1 and 2, and the N-channel transistor group 1
On the other hand, the bonding pad 22 is sandwiched and the P-channel transistor group 2 is arranged. The place surrounded by the chain line 72 is the second
The peripheral circuit 31 is close to the output circuit 21 described in the figure, and the N-channel transistor group 3 of the circuit 31 is sandwiched by the N-channel transistor group 1 of the output circuit and the P-channel transistor group 4 is arranged. . A portion surrounded by a chain line 73 is the peripheral circuit 41 close to the N-channel transistor group 5 to which the high voltage is supplied, which is described in FIG.
The N-channel transistor group 6 of the circuit 41 is sandwiched between the channel-transistor group 5 and the P-channel transistor group 7
Distribute. The area surrounded by the chain line 74 is the peripheral circuit 52 adjacent to the input circuit 51 described in FIG.
For the N-channel transistor group 8 in 51,
This is an embodiment of the present invention in which the channel transistor group 9 is sandwiched and the P-channel transistor group 10 is arranged. A portion surrounded by a chain line 75 is the semiconductor memory circuit 61 described in FIG.
The peripheral circuit 62 is adjacent to the N-channel transistor group 11 of the semiconductor memory circuit 61, and the P-channel transistor group 13 is arranged between the N-channel transistor group 12 of the circuit 62 and the N-channel transistor group 12 of the circuit 62. 76 is an N-channel transistor group.

The area surrounded by the solid line 91 is a row decoder. Since the circuits must be arranged in the row decoder area at the pitch of the memory cells, the respective elements are made extremely close to each other. Therefore, when the method according to the present invention is used,
Latch-up is less likely to occur, and the decoder formation area can be reduced.

According to the above-described embodiments, a circuit element that generates a substrate current is provided to a circuit that generates a substrate current in a semiconductor integrated circuit via a semiconductor element that has the same polarity as the circuit element that generates the substrate current. By arranging semiconductor elements with different polarities to increase the substrate resistance and limit the substrate current, it is possible to easily suppress the latch-up phenomenon that causes excessive current between power supplies and even damages the elements. A semiconductor integrated circuit device capable of achieving the above is obtained. Further, in particular, since the output circuit outputs data to the outside, the size of the transistor is set large. Therefore, in the related art, not only the distance between the P-channel output transistor and the N-channel output transistor is increased, but also the distance between the output transistor and the peripheral circuit is increased to some extent to prevent the latch-up. However, in the present invention, for example, as shown in FIG. 1, by arranging a P or N channel transistor forming an output circuit at the end of a chip, a P or N channel transistor forming an output circuit is formed. There is also an advantage that the chip size can be reduced by eliminating the need for a particular distance from the peripheral circuit.

The present invention is not limited to the above-mentioned embodiments, but various applications are possible. For example, in the present invention, the P-type and N-type of the embodiment may be reversed.

As described above, according to the present invention, it is possible to increase the latch-up resistance of the semiconductor integrated circuit device including the complementary element type circuit without increasing the pattern occupying area. Can be provided.

[Brief description of drawings]

1 (a) is a pattern plan view of an embodiment of the present invention, FIGS. 1 (b) to 1 (g) are sectional views of FIG. 1 (a), and FIGS. 2 to 6 are drawings of the present invention. It is a pattern top view of a different Example. 1 ... First transistor group (N-channel type), 2 ...
Second transistor group (P-channel type), 3 ... Third transistor group (N-channel type), 4 ... Fourth transistor group (P-channel type), 5 ... Fifth transistor group (N-channel) Type), 6 ... Sixth transistor group (N
Channel type), 7 ... 7th transistor group (P channel type), 8 ... 8th transistor group (N channel type), 9 ... 9th transistor group (N channel type),
10 …… 10th transistor group (P-channel type), 11 ……
11th transistor group (N channel type), 12 ... 12th transistor group (N channel type), 13 ... 13th transistor group (P channel type), 21 ... Output circuit, 22 ... Output terminal (Bonding Al pad), 51 …… Input circuit, 61
…… Semiconductor memory, 81 …… Semiconductor chip.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshiyuki Fujimoto 1-13-9 Shibuya, Shibuya-ku, Tokyo Shibuya Takugin Building Tosback Computer System Co., Ltd. (56) Reference JP-A-62-73656 (JP) , A) JP-A-63-273349 (JP, A)

Claims (6)

[Claims] 1. A semiconductor substrate of a first conductivity type, a first circuit block for arranging an input circuit including a protection circuit, which is provided in the vicinity of one peripheral edge of the substrate, and the first circuit. A second circuit block including at least a complementary element type circuit for arranging a peripheral circuit of the input circuit, which is provided adjacent to the block; and a memory provided adjacent to the second circuit block. A third circuit block including at least a complementary element type circuit for arranging a peripheral circuit of the circuit, and at least a memory element provided adjacent to the third circuit block for arranging the memory circuit And a fifth circuit block, which is provided adjacent to the fourth circuit block and includes at least a complementary element type circuit and a high voltage element for disposing a high voltage system circuit. A sixth circuit block, which is provided adjacent to the fifth circuit block and includes at least a complementary element type circuit for arranging a peripheral circuit of the output circuit, and adjacent to the sixth circuit block. A seventh circuit block, which is provided in the vicinity of the other peripheral edge portion of the substrate facing the one peripheral edge portion and includes at least a complementary element type circuit for disposing the output circuit, A well region of the second conductivity type for obtaining a complementary element type circuit included in is disposed on the other peripheral edge side of the substrate, and a pad for applying output data from the output circuit to an external output terminal is provided on the output side. It is arranged between one conductivity type element and the other conductivity type element that form a complementary element type circuit included in the circuit, and the same conductivity type is provided between the second, third, fifth, sixth and seventh circuit blocks. Elements are arranged adjacent to each other A semiconductor integrated circuit device characterized by being provided. 2. A peripheral circuit adjacent to other sides of a fourth circuit block in which the memory circuit is arranged, other than sides adjacent to the third and fifth circuit blocks, respectively. Is further provided, and an eighth circuit block including at least a complementary element type circuit is provided, and an element of the same conductivity type is provided between the eighth circuit block including the complementary element type circuit and the fourth circuit block. 2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is arranged adjacent to each other. 3. A storage element included in the storage circuit is a non-volatile memory element capable of rewriting data, and when the non-volatile memory element is accompanied by at least a substrate current when rewriting data. A fourth in which the memory circuit is arranged
The element of the same conductivity type as the non-volatile memory element is arranged adjacently between the circuit block and the circuit block adjacent to the fourth circuit block. (2) The semiconductor integrated circuit device according to any one of items. 4. In the high voltage system circuit, an element of the same conductivity type as the high voltage element among the one conductivity type element and the other conductivity type element included in the complementary element type circuit of the high voltage system circuit is the high conductivity type element. The semiconductor integrated circuit device according to any one of claims (1) to (3), wherein the semiconductor integrated circuit device is arranged adjacent to a high voltage element of a voltage system circuit. 5. A fourth element in which the high-voltage element and the memory circuit are arranged when the memory element included in the memory circuit and the high-voltage element included in the high-voltage system circuit are both of one conductivity type.
5. The semiconductor integrated circuit device according to claim 4, wherein another one-conductivity-type element is further arranged between the circuit block and the circuit block. 6. The decoder according to claim 2, wherein among the peripheral circuits of the memory circuit, a decoder is arranged in at least an eighth circuit block. Semiconductor integrated circuit device.