JP4623398B2 - Stacked duplexer - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a duplexer used in a microwave band, and more particularly to a duplexer used for band demultiplexing of a dual band mobile phone.
[0002]
[Prior art]
A circuit diagram of a conventional duplexer is shown in FIG. This conventional example has a structure in which an LPF (low pass filter) and an HPF (high pass filter) are combined. Japanese Laid-Open Patent Publication No. 3-216002 discloses a duplexer having the block diagrams shown in FIGS. 6 has a structure in which an LPF is further connected to the HPF of the circuit of FIG. 5, and the duplexer of FIG. 7 has a REJ (rejection filter) on the LPF and HPF of the duplexer of FIG. It is the structure which added each.
[0003]
These filters generally use dielectric coaxial resonators. This has a structure in which electrodes are formed on the inner and outer peripheral surfaces of a cylindrical body made of a dielectric ceramic, and is unsuitable for miniaturization in terms of shape.
[0004]
[Problems to be solved by the invention]
In recent years, there has been a remarkable spread of mobile phones, and functions of mobile terminals have been improved. For example, a dual-band mobile phone has been proposed that enables calls in two frequency bands using a single mobile terminal. In order to configure this dual-band mobile phone, a function for selecting the two frequencies is required. In addition, a small duplexer needs to be configured for use in a portable terminal.
[0005]
For example, FIG. 8 shows an insertion loss as a result of configuring a duplexer with f1 = 824 to 894 MHz and f2 = 1850 to 1990 MHz in the configuration of the conventional duplexer shown in FIG. In this conventional example, the attenuation is 5 to 10 dB, the other frequency component wraps around each frequency band, and the insertion loss characteristics are not good at the respective frequencies f1 and f2.
[0006]
Further, if the circuit configuration shown in FIG. 6 or FIG. 7 is used, the insertion loss characteristic can be improved at the respective frequencies f1 and f2, but the duplexer becomes larger due to the complexity of the circuit. For example, considering use in a mobile phone, a large-sized duplexer cannot be used, and a small and high-performance duplexer is desired.
[0007]
It is an object of the present invention to provide a duplexer having a novel structure, and to provide a small and high-performance duplexer.
[0008]
[Means for Solving the Problems]
According to the present invention, a first notch circuit including an inductance component L1 and a capacitor component C1, and a first notch circuit including an inductance component L2 and a capacitor component C2 are formed on a laminate formed by integrating and insulating layers. And a second notch circuit having a resonance frequency lower than the first notch circuit, wherein one end of the two notch circuits is connected to each other, and a circuit for demultiplexing signals having different frequencies is built in. The laminated body is divided into a region in which only the capacitor electrode pattern is formed and a region in which only the inductance electrode pattern is formed in the stacking direction, and only the capacitor electrode pattern is formed. In the region, a capacitor component C1 pattern electrode and a capacitor component C2 pattern electrode are formed on the insulating layer on the upper side of the ground electrode, A pattern electrode shared by the capacitor component C1 and the capacitor component C2 facing the respective pattern electrodes for the capacitor component C1 and the capacitor component C2 is formed on the upper insulating layer, and is formed on the upper insulating layer. Is formed in a region where a capacitor component C2 pattern electrode facing the common pattern electrode is formed and only an inductance electrode pattern located on the upper layer side of the capacitor component C2 pattern electrode facing the common pattern electrode is formed. And having a plurality of inductor line electrodes constituting the inductance component L1, which are connected in the stacking direction to form a circular structure, and having a plurality of inductor line electrodes constituting the inductance component L2. , They are connected in the stacking direction and formed into a circular structure,
Of the two frequencies to be demultiplexed, the line width of the inductor line electrode forming the inductance component L2 of the second notch circuit arranged in the path for passing the signal on the high frequency side passes the signal on the low frequency side The multilayer duplexer is characterized in that it is formed thicker than the line width of the inductor line electrode forming the inductance component L1 of the first notch circuit arranged in the path .
[0009]
In the present invention, the region where only the inductance electrode pattern is formed has an insulating layer on which inductor line electrodes constituting the inductance components L1 and L2 of the two notch circuits are formed. preferable.
[0010]
In the present invention, a capacitor component C3 for grounding the other end of the first notch circuit is provided, and the dielectric layer between the ground electrode and the capacitor component C1 pattern electrode on the upper layer side is provided with the capacitor layer C3. It is preferable to dispose a capacitor pattern electrode constituting the capacitor component C3, and further includes an inductance component L3 that grounds the other end of the second notch circuit, and the inductor line electrode of the inductance component L3 is connected to the inductance component. It is preferable to arrange in the insulating layer on the upper side of the uppermost layer of the insulating layer on which the inductor line electrodes L1 and L2 are formed.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
An equivalent circuit diagram of an embodiment according to the present invention is shown in FIG. The duplexer of this embodiment includes a notch circuit 1 in which an inductance component L1 and a capacitor component C1 are connected in parallel, and a notch circuit 2 in which an inductance component L2 and a capacitor component C2 are connected in parallel. . One end of the two notch circuits 1 and 2 is connected to form a branching circuit. In this way, the notch circuit can be configured by connecting the inductance component L1 and the capacitor component C1 in parallel. As a notch circuit, there is a configuration in which an inductance component and a capacitor component are connected in series.
[0012]
According to the circuit diagram of this embodiment, when a specific frequency f1 is passed through A to B, the insertion loss of the notch circuit 2 is maximized at the frequency f1 so that no signal is output to C. In contrast, when a specific frequency f2 is passed through A to C, the insertion loss of the notch circuit 1 is maximized at the frequency f2, and no signal is output to B. It is something to be made.
[0013]
FIG. 2 shows a laminated structure diagram of one embodiment according to the present invention, and FIG. 3 shows a perspective view thereof.
This embodiment is an embodiment of a chip-shaped stacked duplexer configured using a sheet stacking method. First, a ceramic dielectric material that can be fired at a low temperature of 950 ° C. or lower is used, and a slurry of this dielectric material is formed into a sheet by a doctor blade to prepare a ceramic green sheet. A dielectric material having a dielectric constant of 8 was used.
[0014]
A predetermined number of these ceramic green sheets are laminated. First, the insulating layer (ceramic green sheet) 11 on which the ground electrode 31 is printed is disposed in the lower layer. The ground electrode 31 is drawn out so as to be connected to the external terminal electrodes D1, D2, and D3.
On top of this, the insulating layer 12 on which the capacitor pattern electrode 32 that forms the capacitor component is formed opposite to the ground electrode 31 is laminated. The capacitor pattern electrode is connected to the external terminal electrode B.
[0015]
Two capacitor component forming pattern electrodes 33 and 34 are formed on the insulating layer 13 thereon, and the capacitor pattern electrodes 33 and 34 are connected to the external terminal electrodes C and B, respectively.
A capacitor component forming pattern electrode 35 is formed on the insulating layer 14 laminated thereon, and the capacitor pattern electrode 35 is connected to the external terminal electrode A.
A capacitor component forming pattern electrode 36 is formed on the insulating layer 15 laminated thereon, and the capacitor pattern electrode 36 is connected to the external terminal electrode C.
[0016]
Line electrodes 37, 38, 39, 40, and 41 constituting an inductance component are formed on the insulating layers 16, 17, and 18 stacked thereon, respectively. One end of the line electrode 37 is connected to the external terminal electrode C, and the other end is connected to the line electrode 38 of the upper insulating layer 17 through a through hole. The line electrode 39 of the layer 18 is connected through a through hole, and the other end of the line electrode 39 is connected to the external terminal electrode A. A line that circulates in a spiral shape is formed between the external terminal electrodes A and C to form an inductance component.
[0017]
The line electrode 40 on the insulating layer 17 has one end connected to the external terminal electrode B, the other end connected to the line electrode 41 of the upper insulating layer 18 through a through hole, and the other end of the line electrode 41 The external terminal electrode A is connected. A line that circulates in a spiral shape is formed between the external terminal electrodes A and B to form an inductance component.
[0018]
Line electrodes 42 and 43 are formed on the insulating layers 19 and 20 thereon. One end of the line electrode 42 is connected to the external terminal electrode D1, and the other end is a through hole. The other end of the line electrode 43 is connected to the external terminal electrode C. A line that spirally circulates is formed between the external terminal electrodes D1 and C to form an inductance component.
[0019]
And the insulating layer 21 in which the mark 44 was formed is laminated | stacked on it. This laminated body was integrally fired at about 900 ° C., and external terminal electrodes A, B, C, D1, D2, and D3 were formed on the side surfaces to constitute a laminated duplexer.
The pattern electrode and line electrode were formed by screen printing of Ag paste.
[0020]
In this embodiment, the laminated duplexer of the circuit diagram shown in FIG. 1 is configured. That is, C1 is constituted by the counter electrode of the capacitor pattern electrodes 34 and 35, L1 is constituted in a circular shape connecting the line electrodes 40 and 41, and C2 is two of the capacitor pattern electrodes 33, 35 and 35, 36. The counter electrode is formed, and L2 is formed in a circular shape connecting the line electrodes 37, 38, and 39. C3 is constituted by the counter electrode of the capacitor pattern electrode 32 and the ground electrode 31, and L3 is constituted by connecting the line electrodes 42 and 43.
[0021]
The line electrode forming this inductance component is constituted by a line electrode that circulates in a spiral shape. By using this spirally wound line electrode, the area constituting the line electrode can be reduced. In the present invention, an unprecedented very small duplexer of 3.2 mm × 1.6 mm × 1 mm (height) could be configured.
[0022]
In the present invention, the line width of the line electrode constituting L1 is different from that of the line electrode constituting L2. This is a line electrode that constitutes an inductance (L2 in the embodiment) that passes the high frequency when the first frequency is passed through the L1 side circuit and the second frequency is passed through the L2 side circuit. (In the embodiment, 37, 38, 39) is made thicker than the line electrodes (40, 41 in the embodiment) constituting the inductance (L1 in the embodiment) that passes the low frequency side frequency. In the example, the line electrodes 37, 38, and 39 were 0.2 mm, and the line electrodes 40 and 41 were 0.12 mm. Thus, by setting, low loss characteristics can be realized and the impedance of the input / output terminals can be adjusted to 50Ω.
[0023]
That is, in the notch circuit composed of L and C, the L value and the C value can be selected as appropriate. At this time, when the L value is increased (the C value is decreased), the width of the notch (band width) tends to be widened. Conversely, when the L value is decreased (the C value is increased), the notch becomes steep, There is a tendency that the insertion loss of the pass frequency becomes small (good). In the embodiment of the present invention, the low frequency side is 824 to 894 MHz (bandwidth 70 MHz), and the high frequency side is 1850 to 1990 MHz (bandwidth 140 MHz). Therefore, the low frequency side is cut and the L2 inductance of the notch circuit that passes the high frequency side is designed to be small, and the line width is widened. As a result, it is possible to cut on the low frequency side with a relatively narrow bandwidth, reduce the insertion loss on the high frequency side, and obtain good characteristics. On the other hand, the L1 inductance of the notch circuit that cuts the high frequency side and passes the low frequency side is designed to be large, and its line width is relatively narrow. This enables cutting on the high frequency side with a wide bandwidth. [0024]
In the duplexer according to the present invention, a notch circuit for passing a low frequency side is connected to a low pass filter circuit having a capacitor component disposed between the notch circuit and ground, and a notch for passing a high frequency side frequency. A high-pass filter circuit configured by arranging an inductance component between the circuit and the ground is connected to improve the demultiplexing characteristics.
[0025]
【Example】
The stacked duplexer shown in FIG. 2 is the same as the equivalent circuit shown in FIG. 1 except that C1 is 1.4 pF, L1 is 4.5 nH, C2 is 4.3 pF, and L2 is 7.5 nH. Configured. The insertion loss characteristic of this example is shown in FIG. In this duplexer, f1 is set to 860 MHz and f2 is set to 1920 MHz. This embodiment is used for a band wave for a dual-band mobile phone in which the frequency band of f1 is 824 to 894 MHz and the frequency band of f2 is 1850 to 1990 MHz. It should be noted that the external dimensions of this laminated duplexer were 3.2 mm × 1.6 mm and the height was 1.0 mm, and it was very small and thin.
As shown in FIG. 4, the duplexer according to the present invention has excellent characteristics as a duplexer because attenuation is 15 dB or more, and the frequency component of one frequency component is small in each frequency band.
[0026]
According to the present invention, since the duplexer is configured by the laminated structure, it is possible to configure a very small duplexer. Moreover, since it has a simple circuit configuration in which two LC notch circuits are combined, a laminated structure can be easily configured.
[0027]
【The invention's effect】
According to the present invention, it is possible to configure a small duplexer with good demultiplexing characteristics. Thereby, for example, in a small microwave product such as a mobile phone, it is possible to contribute to the miniaturization of the entire device without sacrificing the characteristics. In particular, it is effective in a dual-band mobile phone.
[Brief description of the drawings]
FIG. 1 is an equivalent circuit diagram of an embodiment according to the present invention.
FIG. 2 is a stacked structural diagram of an embodiment according to the present invention.
FIG. 3 is a perspective view of an embodiment according to the present invention.
FIG. 4 is an insertion loss characteristic of an embodiment according to the present invention.
FIG. 5 is a circuit diagram of a conventional example.
FIG. 6 is a block diagram of a conventional example.
FIG. 7 is a block diagram of a conventional example.
FIG. 8 shows a conventional insertion loss characteristic.
[Explanation of symbols]
11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21 Insulating layers 32, 33, 34, 35, 36 Capacitor component forming pattern electrodes 37, 38, 39, 40, 41, 42, 43 line electrodes

Claims (4)

Resonance lower than that of the first notch circuit including the first notch circuit including the inductance component L1 and the capacitor component C1 and the first notch circuit including the inductance component L2 and the capacitor component C2. A laminated notch including a second notch circuit having a frequency, one end of the two notch circuits being connected to each other, and a circuit for demultiplexing a signal having a different frequency.
The multilayer body is divided into a region in which only the electrode pattern for capacitors is formed and a region in which only the electrode pattern for inductance is formed in the stacking direction,
In the region where only the capacitor electrode pattern is formed, the capacitor component C1 pattern electrode and the capacitor component C2 pattern electrode are formed in the insulating layer on the upper layer side of the ground electrode, and the capacitor layer C2 is formed on the upper insulating layer. A common pattern electrode is formed for the capacitor component C1 and the capacitor component C2 facing the respective pattern electrodes for the component C1 and the capacitor component C2, and a capacitor facing the common pattern electrode is formed on the upper insulating layer. A pattern electrode for component C2 is formed;
The region where only the inductance electrode pattern located on the upper layer side of the capacitor component C2 pattern electrode facing the common pattern electrode has a plurality of inductor line electrodes constituting the inductance component L1, Are connected in the laminating direction and formed in a circular structure, and have a plurality of inductor line electrodes constituting the inductance component L2, and they are connected in the laminating direction and formed in a circular structure.
Of the two frequencies to be demultiplexed, the line width of the inductor line electrode forming the inductance component L2 of the second notch circuit arranged in the path for passing the signal on the high frequency side passes the signal on the low frequency side A laminated duplexer characterized in that it is formed to be thicker than the line width of the inductor line electrode forming the inductance component L1 of the first notch circuit arranged in the path . Only the inductance electrode patterns are formed regions claim 1, characterized in that it comprises an insulating layer inductor line electrodes are both formed of an inductance component L1, L2 of the two notches circuit A laminated duplexer as described in 1. A capacitor component C3 that grounds the other end of the first notch circuit;
3. The capacitor pattern electrode constituting the capacitor component C3 is disposed in a dielectric layer between the ground electrode and the capacitor component C1 pattern electrode on the upper layer side. Laminated duplexer. An inductance component L3 for grounding the other end of the second notch circuit;
4. The inductor line electrode having an inductance component L3 is disposed in an insulating layer on an upper layer side of the uppermost layer of the insulating layer on which the inductor line electrodes having inductance components L1 and L2 are formed . Stacked duplexer.

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