JP4630715B2 - Imaging device - Google Patents

Description

  The present invention relates to an imaging apparatus that acquires an electronic image by driving an imaging device that converts an optical image of a subject into an electrical signal.

  Usually, when displaying or recording a still image or a moving image captured by a solid-state image sensor such as a CCD, the optical black of the image sensor (optical black, hereinafter “ OB) level) is used. OB refers to a pixel output that is shielded from light in the light receiving pixel portion of the image sensor and does not depend on incident light.

  FIG. 7 shows an example of a device configuration of a feedback clamp system which is a DC component reproduction (clamp) circuit using the OB level as a black reference for an imaging signal and is generally used in a video camera or the like, and FIG. 8 shows main operation waveforms. The operation will be briefly described.

  In FIG. 7, there is a solid-state image sensor 101 such as a CCD, for example, and an image signal output from the image sensor 101 is input to a circuit 102 called a CDS (correlated double sampling) circuit to remove reset noise. After that, a predetermined offset voltage is added to the offset addition circuit 103, and the offset addition output is input to the variable amplifier (PGA) 104.

  The CDS circuit 102 forms a CDS circuit that uses the predetermined reference voltage VREF input from the terminal 106 as a reference for the feedthrough portion of the imaging signal. Similarly, the variable amplifier 104 images the reference voltage VREF. This constitutes a direct current amplifier that is used as a reference for direct current signal amplification.

  The variable amplifier 104 is a gain variable means for correcting the output sensitivity variation of the CCD 101 and switching the sensitivity setting of the image pickup apparatus. Hereinafter, in order to explain the clamping operation of the image pickup apparatus simply and clearly, the gain 1 It shall be handled simply as a double.

  The amplified output signal from the variable amplifier 104 is input to an image processing / recording / display circuit (not shown) on the one hand, and is input to the sample hold circuit 107 on the other hand and reads out the OB pixel input from the terminal 109. The OB level sampled and held by the OB clamp pulse synchronized with the timing is input to the integrating amplifier 105.

  The integrating amplifier 105 has a predetermined integration time constant by a capacitor 105b and a resistor 105c, and a differential voltage (clamp error voltage) between the sampled and held OB level and a predetermined reference voltage VREF input from the terminal 106. ) Is integrated with the integration time constant, and the output (deviation amount from the voltage VREF (error signal)) is input to the offset addition circuit 103 and subtracted and is configured to be negative feedback control.

  FIG. 8 shows how the OB level of the output signal 11C of the variable amplifier 104 is clamped to the DC voltage level VREF and converges, and the operation waveforms of the respective parts at that time.

  A signal waveform 11A is an output waveform of the CDS circuit 102, and has an OB pixel output for a predetermined period for each horizontal line read from the image sensor 101. A part of the OB pixel output period is sampled and held. The timing signal is an OB clamp pulse 11D.

The OB pixel output of the signal waveform 11A is maintained at a DC voltage that is relatively close to the reference voltage VREF by the action of the CDS (correlated double sampling) circuit 102. A difference component (CCD offset) from the signal component and a dark current component depending on the temperature of the imaging element are superimposed to have an offset error (usually several millimeters to several tens of millivolts).

  This offset error varies for each image sensor, and varies depending on the temperature. Then, this offset error is amplified by the variable amplifier 104 and finally outputted as the black level fluctuation VERR of the imaging signal.

  The black level fluctuation VERR is detected as a difference of the VREF voltage by the sample hold circuit 107 and the integrating amplifier 105, integrated and output as an integrated output signal 11B (ΔVERR) shown in FIG. 8, and from the output signal 11A of the CDS circuit 102 Subtracted.

  By repeating this operation for each output of the OB clamp pulse 11D, the integrated output ΔVERR converges to the black level fluctuation VERR as in the signal waveform 11B, and the OB pixel output of the output signal of the variable amplifier 104 is the signal waveform. It converges to the reference voltage VREF as in 11C.

  By the way, in such a feedback type OB clamp circuit, the time constant of the integration when the black level fluctuation VERR is integrated and non-feedback is very important.

  If the time constant is short, the response response to the VREF voltage of the output OB level for each horizontal line will be faster, but the amount of fluctuation (fluctuation frequency) for each clamping operation will increase accordingly, and noise on the horizontal stripes will easily occur. Become.

  Therefore, the time constant must be set to a predetermined length so that the noise on the horizontal stripe does not cause a problem in image quality.

  Patent Document 1 below discloses an imaging apparatus that performs a clamping process based on a signal from an optical black region.

JP 2003-143488 A

  In such a conventional feedback type OB clamp circuit, the offset error due to the CCD offset and dark current component of the image sensor is assumed as the main factor of the fluctuation amount of the OB, and these offset error components are corrected. The main design is made.

  Originally, these offset error components are not so large as 1/10 or less (several millimeters to several tens of millivolts) of the full range (up to 1 volt) of the imaging signal.

  By the way, when a strong light such as direct sunlight is incident on a solid-state imaging device such as a CCD, a phenomenon called so-called blooming occurs in which the electric charge overflows in the photoelectric conversion unit. When blooming occurs, the overflowed charge may flow into and accumulate in the OB pixel portion that is originally shielded in the light receiving pixel portion and does not depend on incident light.

In this case, unlike the offset error component, the OB level cannot be an accurate black reference, but also reaches a full range level change (CCD saturation level VSAT) of the imaging signal for intense blooming.

  FIG. 9 shows operation waveforms of respective parts for explaining the clamping operation when blooming occurs. The OB output of the CDS output 11A rapidly reaches the CCD saturation level VSAT as blooming occurs. The OB output of the variable amplification output 11C is gradually lowered to the reference voltage VREF with respect to the erroneous OB level that has risen to the CCD saturation level VSAT with a response time based on the time constant set by the integrating amplifier 105.

  As described above, the conventional clamp circuit configuration has a problem that when blooming occurs, it follows an erroneous black level that greatly deviates from an appropriate OB level, and the entire image pickup signal causes blackening.

  In addition, as a result of following an erroneous black level that greatly deviates from the appropriate OB level, it takes a very long time to return to the normal OB level even after the blooming of the image sensor is resolved. There was a problem that the condition continued.

  The present invention has been made in view of the above-mentioned problems, and monitors the amount of charge leakage to the reference portion (OB portion) and selects a reference portion suitable for direct current reproduction to reduce erroneous direct current reproduction. It is an object.

  An image pickup apparatus according to the present invention includes an image pickup unit that converts an optical image of a subject into an electrical signal, a vertical synchronization signal generation unit that generates a vertical synchronization signal, a horizontal synchronization signal generation unit that generates a horizontal synchronization signal, and the image pickup unit. Vertical transfer driving means for driving the vertical transfer path in the image pickup means by a vertical transfer pulse based on the vertical synchronization signal, horizontal transfer drive means for driving the horizontal transfer path in the imaging means by a horizontal transfer pulse based on the horizontal synchronization signal, and Frequency changing means for changing the frequency of a horizontal synchronizing signal, pulse number changing means for changing the number of horizontal transfer pulses, monitoring means for monitoring a reference portion of an output signal from the imaging means, and clamping the reference portion Clamping means, clamping pulse output means for outputting a clamping pulse for performing the clamping, and clamping pulse output A phase changing means for changing the phase of the clamp pulse output from the stage, and comparing the level of the reference portion with a predetermined level, and when the level of the reference portion exceeds the predetermined level, the horizontal synchronization signal The frequency changing means is controlled so as to increase the period of time, the pulse number changing means is controlled so as to increase the number of the horizontal transfer pulses, and the phase of the clamp pulse is changed. Control means for controlling the changing means to output a clamp pulse whose phase has been changed by the phase changing means after the level of the reference portion has converged within the predetermined level.

  According to the present invention, the amount of charge leakage to the reference portion (OB portion) can be monitored, and a reference portion suitable for clamping (DC regeneration) can be selected, and erroneous DC regeneration can be reduced. .

  In addition, when the level of the reference portion (OB portion) exceeds a predetermined level, it is possible to perform clamping while avoiding the reference portion, and it is possible to reproduce a signal with little image quality degradation.

(First embodiment)
FIG. 3 is a block configuration diagram of the electronic imaging apparatus according to the first embodiment of the present invention.
In FIG. 3, 1 is a photoelectric conversion element for converting light into an electrical signal (here, “CCD” is taken as an example), and 2 is a correlated double sampling circuit (hereinafter referred to as “CCD”) for converting the output signal of the CCD 1 into a video signal. 3 is an analog-digital conversion circuit (hereinafter referred to as “AD”) for converting an analog signal output from the CDS 2 into a digital signal, 4 is a color signal process, a luminance signal process, and A digital signal processing circuit (hereinafter referred to as “DSP”) for performing various signal processing such as monitoring the signal of the OB unit and comparing it with an error level set in advance to generate an error signal of the OB unit. A CCD horizontal transfer drive circuit (hereinafter referred to as “HDr”) for driving the horizontal transfer unit, and 6 a CCD vertical transfer drive circuit for driving the vertical transfer unit of the CCD 1 (Hereinafter referred to as “VDr”), 7 inputs a pulse phase change command from the CPU based on the reference synchronization signal and the error signal of the OB unit, and various pulses necessary for driving the CCD 1 and for signal processing by these reference signals. Timing generator (hereinafter referred to as “TG”) to be generated, 8 is a CPU for controlling the entire system, 9 is a lens driving circuit for driving the focus lens and zoom lens, and 10 is a focus lens and zoom lens 11 is an aperture driving circuit for driving an aperture with a shutter function, 12 is an aperture with a shutter function for controlling the amount of light incident on the CCD 1, and 13 is a release switch having a two-stage stroke. Has a crystal oscillation circuit, horizontal synchronization signal (hereinafter referred to as "HD signal") and vertical synchronization signal Hereinafter, a reference signal generation circuit for generating a referred) to as "VD signal".

Next, the operation of the electronic imaging device in the present embodiment will be described.
The subject image is focused on the CCD 1 through the taking lens 10 with the amount of light adjusted by the diaphragm 12. Then, the photoelectric conversion is performed by the CCD 1 and is output to the CDS 2 as a CCD output signal. Further, the main clock, HD signal, and VD signal generated by the reference signal generation circuit 14 are output to the TG 7, and the CCD horizontal transfer pulse, the CCD vertical transfer pulse, the CCD field shift pulse, An electronic shutter pulse and an OB clamp pulse are generated. The CCD horizontal transfer pulse is output to HDr5, the CCD vertical transfer pulse, CCD field shift pulse and electronic shutter pulse are output to VDr6, and the OB clamp pulse is output to CDS2.

  The VDr6 receives the CCD vertical transfer pulse and the CCD field shift pulse output from the TG7, and combines them to obtain a ternary value (H (high potential) that retains signal amplitude and frequency characteristics that can sufficiently drive the vertical transfer unit of the CCD. ), M (medium potential), L (low potential) level) signals and output to the vertical transfer drive unit of the CCD 1. The CCD 1 receives these signals, and outputs an electric charge accumulated in the photodiode of the CCD 1 to the vertical transfer section when an “H” level signal corresponding to a field shift pulse is input. The charges output to the vertical transfer unit are transferred in order on the vertical transfer path to the horizontal transfer path by four-phase binary (M, L level) driving of a CCD vertical transfer pulse.

  The electronic shutter pulse is converted into a signal amplitude that can sufficiently drive the CCD 1 in the VDr 6 and then output to the CCD 1 to control the charge accumulation time (exposure amount) in the CCD 1. The CCD 1 continues to clear the charge of the photodiode during the period when the electronic shutter pulse is input, and enters the exposure state after the electronic shutter pulse stops.

  In HDr5, the CCD horizontal transfer pulse output from TG7 is input, converted into a signal having signal amplitude and frequency characteristics that can sufficiently drive the horizontal transfer unit of CCD1, and output to the horizontal transfer unit of CCD1. The reset gate pulse is directly output from the TG 7 to the CCD 1, and charge potential conversion is performed by fixing the output gate portion of the CCD 1 to a constant potential. In the CCD 1, when these horizontal transfer pulse and reset gate pulse signals are input, electric charges are output from the horizontal transfer unit to the CDS 2 through the output amplifier as a CCD output signal.

  In CDS2, the CCD output signal is input, the level difference between the feedthrough part (reference part) of the CCD output signal and the data part is converted as a video signal, thereby removing low frequency noise contained in the CCD output signal, The video signal is amplified so that a desired sensitivity can be obtained by the variable gain amplification function. Then, the reference portion of this signal (light-shielded photodiode portion in the CCD 1 (hereinafter referred to as “OB portion”), photodiode may not be formed) is converted back to a new DC bias (DC). Reproduction, hereinafter referred to as “clamp”) and output to AD3.

  In AD3, the video signal output from CDS2 is input, this signal is converted from an analog signal to a digital signal (for example, 10-bit signal), and output to DSP4. The output of AD3 is set so that the above-described OB portion is always fixed to a constant value (for example, 32LSB in the full range 1024LSB).

  The DSP 4 receives the video signal converted into a digital signal by the AD 3 and reproduces a luminance signal and a color signal by signal processing. Also, a reference signal for performing exposure control using a video signal, a reference signal for performing white balance control, and a reference signal for performing focus control are generated. Further, the OB section signal is monitored, and the level of the OB section signal is compared with a preset error level to determine whether or not the OB section is damaged. And outputs this signal to the CPU 8.

Next, a process until a signal is output from the CCD 1 will be described with reference to schematic diagrams of the CCD 1 shown in FIGS.
In FIG. 4A, 41 is a vertical transfer path for sending out charges transferred from each photodiode to the horizontal transfer path, 42 is a gate for sending charges on the photodiode to the vertical transfer path, and 43 is photoelectric. A first photodiode for conversion, 44 (shaded portion) is a second photodiode for shielding the sensor portion to form an OB signal, 45 is an output amplifier for outputting a CCD output signal to the outside, and 46 is a vertical line This is a horizontal transfer path for sending the charge transferred from the transfer path 41 to the output amplifier 45.

  An on-chip filter is formed on the first photodiode 43 and generates a charge that is sensitive to the filter color. Here, a description will be given by taking a pure color filter of RGB (R = red, G = green, B = blue) as an example. The “R” symbol is a photodiode in which an R color filter is formed, and the “G” symbol and the “B” symbol have the same meaning. As shown by 51 to 54 in the vertical transfer path 41, electrodes to which vertical transfer pulses of φV1, φV2, φV3, and φV4 are applied are repeatedly arranged adjacent to each other, and 47-50 in the vertical transfer path 46. As described above, every two electrodes to which the horizontal transfer pulses of φH1 and φH2 are applied are repeatedly arranged adjacent to each other.

  In the CCD 1 having the above-described configuration, when exposure is started, the first photodiode 43 forming the RGB color filter generates electric charges according to the color and luminance of the subject (FIG. 4-2). When the exposure is completed, the gate 42 connected between the electrode 53 of the φV3 and the photodiodes 43 and 44 is opened during the ternary H level period by the field shift pulse superimposed on the vertical transfer pulse φV3, and RG Charges corresponding to the columns are output from the photodiodes 43 and 44 to the vertical transfer path 41 (FIG. 4-3).

  Next, due to the four-phase driving by the vertical transfer pulses φV1 to φV4, the charge on the vertical transfer path 41 moves in the direction of the horizontal transfer path by four electrodes in one HD period (FIG. 4-4). That is, the charge on the φV3 electrode passes through the φV4 → φV1 → φV2 electrode and moves onto the φV3 electrode. The charges on the φV3 electrode closest to the horizontal transfer path 46 pass through the φV4 electrode and move to the horizontal transfer path 46. As a result, one column of charge is sent to the horizontal transfer path 46 every 1 HD period.

  As shown in FIG. 6, electrodes 47 and 48 connected to φH1 and electrodes 49 and 50 connected to φH2 are formed on the horizontal transfer path. The electrodes 47 and 48 and the electrodes 49 and 50 are given a slight potential difference, and a potential gradient as shown by J3 in FIG. 6 is formed. The charge sent from the vertical transfer path to the horizontal transfer path is held at a high potential position (below the electrode 48), as indicated by J3 (time t1, J6 & J7) in FIG. At this time, a reverse bias of the electrode 48 is applied to the electrode 49, and a barrier is formed between the electrode 48 and the electrode 49. Since the electrode 47 is set in advance so as to form a potential gradient with respect to the electrode 48, a slight barrier is formed with respect to the electrode 48, and the electric charge remains below the electrode 48.

  Next, the charge held under the electrode 48 at the moment when the horizontal transfer pulses φH1 and φH2 are applied in the opposite direction of “L” and “H”, that is, J4 (time t2, J6 & J7) in FIG. As the bias with the electrode 49 begins to reverse, the barriers that have occurred during this period are gradually eliminated, and the charge held under the electrode 48 starts to move sequentially under the electrode 49 and under the electrode 50. In J5 of FIG. 6 (time t3, J6 & J7), the horizontal transfer pulses φH1 and φH2 are applied with a pulse having a polarity opposite to that at time t1, and the electric charge is at the highest potential (under the electrode 50). Move and hold here. This operation is repeatedly performed within 1 HD period, and the charges on the horizontal transfer path are sequentially moved to the output amplifier 45 side one by one, and all charges on the horizontal transfer path are sent out from the output amplifier 45 to the outside. In one HD period, one line of RG train is output from the CCD 1 (FIG. 4-4 → FIG. 4-5 → FIG. 4-6 → FIG. 4-7), and these operations are performed in one vertical synchronization period (hereinafter referred to as “1VD period”). (Refer to FIG. 4-8 → FIG. 4-9 →...), And all the charges on all lines of the RG column are output.

  The horizontal transfer pulse is output within the 1 HD period during the period excluding the horizontal blanking period, the horizontal transfer pulse during the horizontal blanking period is paused, and no charge movement occurs in the horizontal transfer path. Then, vertical transfer pulses (φV1, φV2, φV3, φV4) are output only in the horizontal blanking period, and charges in the vertical transfer path are sequentially transferred in the horizontal transfer path direction. The horizontal transfer pulse and the vertical transfer pulse are not output at the same time, and the charge in the horizontal transfer path and the charge in the vertical transfer path are not mixed.

  On the other hand, the GB column is read in the next 1VD period following the 1VD period in which the RG column is read. The readout method is almost the same as the readout of the RG row, and is connected between the electrode 51 of φV1 and each of the photodiodes 43 and 44 during a ternary H level period by a field shift pulse superimposed on φV1 of the vertical transfer pulse. The gate 42 is opened, and charges corresponding to the GB column are output from the photodiodes 43 and 44 to the vertical transfer path 41. Next, by the four-phase driving by the vertical transfer pulses φV1 to φV4, the charge on the vertical transfer path 41 moves in the direction of the horizontal transfer path 46 by four electrodes in one HD period. That is, the electric charge existing on the φV1 electrode passes through the φV2 → φV3 → φV4 electrode and moves onto the next φV1 electrode. The electric charge existing at the electrode of φV1 closest to the horizontal transfer path 46 moves to the horizontal transfer path 46 through the electrode of φV2 → φV3 → φV4.

  As a result, one column of charge is sent to the horizontal transfer path 46 every 1 HD period. The charges on the horizontal transfer path 46 move in the direction of the output amplifier 45 every clock by the horizontal transfer pulses of φH1 and φH2, and are all output to the outside of the CCD 1 through the output amplifier 45 within one HD period. These operations are repeated within the 1VD period, and all the charges in the GB column can be output within this period. As a result, all the charges in the CCD 1 can be output in a continuous 2VD period.

  Here, how the electronic image pickup apparatus of the present embodiment controls the CCD 1 when shooting a scene where a dark building in the center and sunlight in the corners of the background exist is described. Here, as an example, the charge holding capacity is small in the order of horizontal transfer path> photodiode> vertical transfer path. A process of overflowing charges in the vertical transfer path and leaking out to the horizontal transfer path will be described with reference to FIG. 5 (the charge transfer method and the horizontal transfer method are the same as described above). Note that FIGS. 5A and 5B are the same as FIGS. 4A and 4B.

The following phenomenon occurs in a pixel or transfer path that is supersaturated capacitively.
As shown in FIG. 5C, when the capacity of the vertical transfer path 41 is smaller than the storage capacity of the first photodiode 43, when charge is sent from the first photodiode 43 to the vertical transfer path 41, Charges overflow on the vertical transfer path 41 and move toward the horizontal transfer path 46. Minimally generated supersaturated charge on the vertical transfer path 46 can be prevented by flowing into this electrode if there is an acceptable capacity on the neighboring electrode. However, as the portion of supersaturation spreads, the amount of charge that overflows on the vertical transfer path 41 increases, and this charge cannot be received in the vertical transfer path 41 and overflows to the horizontal transfer path 46.

  Extremely, when all the photodiodes in the vertical direction of one screen are saturated, the charge overflows when the charge is sent to the vertical transfer path 41, and the charge moves to the horizontal transfer path 46 ( Fig. 5-3). The charges sent to the vertical transfer path 41 are sequentially moved to the horizontal transfer path 46 by the vertical transfer pulse output in the horizontal blanking period every 1 HD period (FIG. 5-4). The overflowed charges continue to flow toward the horizontal transfer path 46 until all of the overflowed charges converge on the neighboring electrodes. When the vertical transfer pulse stops and the horizontal blanking period ends, the horizontal transfer pulse starts to be output, and the charge on the horizontal transfer path 46 starts to move toward the output amplifier 45. At this time, the charges that continue to overflow from the vertical transfer path 41 flow into the horizontal transfer path 46 even during the period in which the horizontal transfer path 46 is operating. Are added (FIGS. 5-5 to 5-6) and output (FIGS. 5-7). These operations are repeated within a 1VD period (FIGS. 5-8 → FIG. 5-9 →...), And all the charges on all the lines in the RG column are output. When the first photodiode 43 is supersaturated at a position close to the OB portion (second photodiode 44), as a result, charges overflow to the OB portion during horizontal transfer.

  In the electronic imaging apparatus of the present embodiment, the DSP 4 monitors a part of the signal of the OB unit at this time, compares this signal level with an error level that can be arbitrarily set in advance, and the fluctuation of the OB level is detected. When it is within this error level, normal clamping is performed. On the other hand, if the fluctuation of the OB level exceeds a preset error level, it is determined that the OB part has been damaged, and an error signal (here, OB part) as indicated by A12 in FIG. In the case of “L” signal, there is no damage, and in the case of “H” signal, there is damage), the DSP 4 generates the signal and outputs this signal to the CPU 8.

  When the error signal of the OB portion is input, the CPU 8 determines that the OB portion is not damaged when this signal is “L”, and sends a clamp pulse for clamping the OB portion with a normal phase. An instruction is issued to the TG 7 to output it. On the other hand, when the error signal of the OB section is “H”, a command is issued so as not to output the clamp pulse to the TG 7, and when the error signal of the OB section is switched from “H” to “L”, A command is issued to the TG 7 so as to output a clamp pulse for clamping the OB section at a predetermined phase to be described later. At this time, the TG 7 sets and outputs a clamp pulse at a predetermined phase based on a command from the CPU 8.

Next, the phase of the clamp pulse will be described in detail with reference to FIG.
When the CPU 8 determines that the OB section is damaged (when the error signal of the OB section from the DSP 4 is “H”), the output of the horizontal transfer pulse is stopped and the next horizontal transfer pulse is output. A command is issued to the TG 7 so as to temporarily clamp a part of the horizontal blanking period until the first time. In response to this, the TG 7 changes the phase of the clamp pulse to a predetermined phase. However, when a vertical transfer pulse (C4, C5, C6, C7 in FIG. 2) or an electronic shutter pulse is output, noise due to the pulse is superimposed on the CCD output signal (C9 in FIG. 2). The pulse phase is changed so as to clamp the position avoiding this timing.

  Specifically, as indicated by D10 in FIG. 2, the horizontal transfer pulse stops and the pulse signal that appears next in the horizontal blanking period (in FIG. 2, it becomes the horizontal synchronizing signal of C1, but depending on the system, When the vertical transfer pulse signals indicated by C4 to C7 are output earlier than the HD signal, the phase of the clamp pulse is changed and output so as to clamp the period until the signal is output. Alternatively, as shown at E10 in FIG. 2, in a period from when the vertical transfer pulse is stopped until the next horizontal transfer pulse is output, clamping is performed so as to clamp a portion where a pulse synchronized with the horizontal synchronization signal is not output. Change the pulse phase and output. Alternatively, as indicated by F10 in FIG. 2, the phase of the clamp pulse is changed and output so as to clamp the period (dummy part) until the next horizontal transfer pulse starts to be output and the signal component appears. However, this dummy portion may not exist depending on the CCD.

  If no horizontal transfer pulse is output, no video signal is output from the CCD 1 and only a DC bias component substantially the same as the signal in the OB portion is output. Therefore, the OB portion clamp is not adversely affected.

(Second Embodiment)
The block configuration diagram in the electronic imaging device according to the second embodiment of the present invention is also the same as that shown in FIG. 3, similarly to the block configuration diagram in the electronic imaging device according to the first embodiment.

  In FIG. 3, 1 is a photoelectric conversion element for converting light into an electrical signal (here, “CCD” is taken as an example), and 2 is a correlated double sampling circuit (hereinafter referred to as “CCD”) for converting the output signal of CCD 1 into a video signal. 3 is an analog-digital conversion circuit (hereinafter referred to as “AD”) for converting an analog signal output from the CDS 2 into a digital signal, 4 is a color signal process, a luminance signal process, and A digital signal processing circuit (hereinafter referred to as “DSP”) for performing various signal processing such as monitoring the signal of the OB unit and comparing it with an error level set in advance to generate an error signal of the OB unit. A CCD horizontal transfer drive circuit (hereinafter referred to as “HDr”) for driving the horizontal transfer unit, and 6 a CCD vertical transfer drive circuit for driving the vertical transfer unit of the CCD 1 (Hereinafter referred to as “VDr”), 7 inputs a pulse phase change command from the CPU based on the reference synchronization signal and the error signal of the OB unit, and various pulses necessary for driving the CCD 1 and for signal processing by these reference signals. Timing generator (hereinafter referred to as “TG”) to be generated, 8 is a CPU for controlling the entire system, 9 is a lens driving circuit for driving the focus lens and zoom lens, and 10 is a focus lens and zoom lens 11 is an aperture driving circuit for driving an aperture with a shutter function, 12 is an aperture with a shutter function for controlling the amount of light incident on the CCD 1, and 13 is a release switch having a two-stage stroke. Has a crystal oscillation circuit, horizontal synchronization signal (hereinafter referred to as "HD signal") and vertical synchronization signal Hereinafter, a reference signal generation circuit for generating a referred) to as "VD signal". The reference signal generation circuit 14 for generating the HD signal and the VD signal is configured to be able to arbitrarily change the cycle by a pulse phase change command from the CPU 8 based on the error signal of the OB unit.

Next, the operation of the electronic imaging device in the present embodiment will be described.
The subject image is focused on the CCD 1 through the taking lens 10 with the amount of light adjusted by the diaphragm 12. Then, the photoelectric conversion is performed by the CCD 1 and is output to the CDS 2 as a CCD output signal. Further, the main clock, HD signal, and VD signal generated by the reference signal generation circuit 14 are output to the TG 7, and the CCD horizontal transfer pulse, the CCD vertical transfer pulse, the CCD field shift pulse, An electronic shutter pulse and an OB clamp pulse are generated. The CCD horizontal transfer pulse is output to HDr5, the CCD vertical transfer pulse, CCD field shift pulse and electronic shutter pulse are output to VDr6, and the OB clamp pulse is output to CDS2.

  The VDr6 receives the CCD vertical transfer pulse and the CCD field shift pulse output from the TG7, and combines them to obtain a ternary value (H (high potential) that retains signal amplitude and frequency characteristics that can sufficiently drive the vertical transfer unit of the CCD. ), M (medium potential), L (low potential) level) signals and output to the vertical transfer drive unit of the CCD 1. The CCD 1 receives these signals, and outputs an electric charge accumulated in the photodiode of the CCD 1 to the vertical transfer section when an “H” level signal corresponding to a field shift pulse is input. The charges output to the vertical transfer unit are transferred in order on the vertical transfer path to the horizontal transfer path by four-phase binary (M, L level) driving of a CCD vertical transfer pulse.

  The electronic shutter pulse is converted into a signal amplitude that can sufficiently drive the CCD 1 in the VDr 6 and then output to the CCD 1 to control the charge accumulation time (exposure amount) in the CCD 1. The CCD 1 continues to clear the charge of the photodiode during the period when the electronic shutter pulse is input, and enters the exposure state after the electronic shutter pulse stops.

  In HDr5, the CCD horizontal transfer pulse output from TG7 is input, converted into a signal having signal amplitude and frequency characteristics that can sufficiently drive the horizontal transfer unit of CCD1, and output to the horizontal transfer unit of CCD1. The reset gate pulse is directly output from the TG 7 to the CCD 1, and charge potential conversion is performed by fixing the output gate portion of the CCD 1 to a constant potential. In the CCD 1, when these horizontal transfer pulse and reset gate pulse signals are input, electric charges are output from the horizontal transfer unit to the CDS 2 through the output amplifier as a CCD output signal.

  In CDS2, the CCD output signal is input, the level difference between the feedthrough part (reference part) of the CCD output signal and the data part is converted as a video signal, thereby removing low frequency noise contained in the CCD output signal, The video signal is amplified so that a desired sensitivity can be obtained by the variable gain amplification function. Then, the reference portion of this signal (light-shielded photodiode portion in the CCD 1 (hereinafter referred to as “OB portion”), photodiode may not be formed) is converted back to a new DC bias (DC). Reproduction, hereinafter referred to as “clamp”) and output to AD3.

  In AD3, the video signal output from CDS2 is input, this signal is converted from an analog signal to a digital signal (for example, 10-bit signal), and output to DSP4. The output of AD3 is set so that the above-described OB unit is always fixed to a constant value (for example, 32LSB in the full range 104LSB).

  The DSP 4 receives the video signal converted into a digital signal by the AD 3 and reproduces a luminance signal and a color signal by signal processing. Also, a reference signal for performing exposure control using a video signal, a reference signal for performing white balance control, and a reference signal for performing focus control are generated. Further, the signal of the OB unit is monitored, the level of the signal of the OB unit is compared with a preset error level, and the result is output to the CPU 8.

Next, a process until a signal is output from the CCD 1 will be described with reference to schematic diagrams of the CCD 1 shown in FIGS.
In FIG. 4A, 41 is a vertical transfer path for sending out charges transferred from each photodiode to the horizontal transfer path, 42 is a gate for sending charges on the photodiode to the vertical transfer path, and 43 is photoelectric. A first photodiode for conversion, 44 (shaded portion) is a second photodiode for shielding the sensor portion to form an OB signal, 45 is an output amplifier for outputting a CCD output signal to the outside, and 46 is a vertical line This is a horizontal transfer path for sending the charge transferred from the transfer path 41 to the output amplifier 45.

  An on-chip filter is formed on the first photodiode 43 and generates a charge that is sensitive to the filter color. Here, a description will be given by taking a pure color filter of RGB (R = red, G = green, B = blue) as an example. The “R” symbol is a photodiode in which an R color filter is formed, and the “G” symbol and the “B” symbol have the same meaning. As shown by 51 to 54 in the vertical transfer path 41, electrodes to which vertical transfer pulses of φV1, φV2, φV3, and φV4 are applied are repeatedly arranged adjacent to each other, and 47-50 in the vertical transfer path 46. As described above, every two electrodes to which the horizontal transfer pulses of φH1 and φH2 are applied are repeatedly arranged adjacent to each other.

  In the CCD 1 having the above-described configuration, when exposure is started, the first photodiode 43 forming the RGB color filter generates electric charges according to the color and luminance of the subject (FIG. 4-2). When the exposure is completed, the gate 42 connected between the electrode 53 of the φV3 and the photodiodes 43 and 44 is opened during the ternary H level period by the field shift pulse superimposed on the vertical transfer pulse φV3, and RG Charges corresponding to the columns are output from the photodiodes 43 and 44 to the vertical transfer path 41 (FIG. 4-3).

  Next, due to the four-phase driving by the vertical transfer pulses φV1 to φV4, the charge on the vertical transfer path 41 moves in the direction of the horizontal transfer path by four electrodes in one HD period (FIG. 4-4). That is, the charge on the φV3 electrode passes through the φV4 → φV1 → φV2 electrode and moves onto the φV3 electrode. The charges on the φV3 electrode closest to the horizontal transfer path 46 pass through the φV4 electrode and move to the horizontal transfer path 46. As a result, one column of charge is sent to the horizontal transfer path 46 every 1 HD period.

  As shown in FIG. 6, electrodes 47 and 48 connected to φH1 and electrodes 49 and 50 connected to φH2 are formed on the horizontal transfer path. The electrodes 47 and 48 and the electrodes 49 and 50 are given a slight potential difference, and a potential gradient as shown by J3 in FIG. 6 is formed. The charge sent from the vertical transfer path to the horizontal transfer path is held at a high potential position (below the electrode 48), as indicated by J3 (time t1, J6 & J7) in FIG. At this time, a reverse bias of the electrode 48 is applied to the electrode 49, and a barrier is formed between the electrode 48 and the electrode 49. Since the electrode 47 is set in advance so as to form a potential gradient with respect to the electrode 48, a slight barrier is formed with respect to the electrode 48, and the electric charge remains below the electrode 48.

  Next, the charge held under the electrode 48 at the moment when the horizontal transfer pulses φH1 and φH2 are applied in the opposite direction of “L” and “H”, that is, J4 (time t2, J6 & J7) in FIG. As the bias with the electrode 49 begins to reverse, the barriers that have occurred during this period are gradually eliminated, and the charge held under the electrode 48 starts to move sequentially under the electrode 49 and under the electrode 50. In J5 of FIG. 6 (time t3, J6 & J7), the horizontal transfer pulses φH1 and φH2 are applied with a pulse having a polarity opposite to that at time t1, and the electric charge is at the highest potential (under the electrode 50). Move and hold here. This operation is repeatedly performed within 1 HD period, and the charges on the horizontal transfer path are sequentially moved to the output amplifier 45 side one by one, and all charges on the horizontal transfer path are sent out from the output amplifier 45 to the outside. In one HD period, one line of RG train is output from the CCD 1 (FIG. 4-4 → FIG. 4-5 → FIG. 4-6 → FIG. 4-7), and these operations are performed in one vertical synchronization period (hereinafter referred to as “1VD period”). (Refer to FIG. 4-8 → FIG. 4-9 →...), And all the charges on all lines of the RG column are output.

  The horizontal transfer pulse is output within the 1 HD period during the period excluding the horizontal blanking period, the horizontal transfer pulse during the horizontal blanking period is paused, and no charge movement occurs in the horizontal transfer path. Then, vertical transfer pulses (φV1, φV2, φV3, φV4) are output only in the horizontal blanking period, and charges in the vertical transfer path are sequentially transferred in the horizontal transfer path direction. The horizontal transfer pulse and the vertical transfer pulse are not output at the same time, and the charge in the horizontal transfer path and the charge in the vertical transfer path are not mixed.

  On the other hand, the GB column is read in the next 1VD period following the 1VD period in which the RG column is read. The readout method is almost the same as the readout of the RG row, and is connected between the electrode 51 of φV1 and each of the photodiodes 43 and 44 during a ternary H level period by a field shift pulse superimposed on φV1 of the vertical transfer pulse. The gate 42 is opened, and charges corresponding to the GB column are output from the photodiodes 43 and 44 to the vertical transfer path 41. Next, by the four-phase driving by the vertical transfer pulses φV1 to φV4, the charge on the vertical transfer path 41 moves in the direction of the horizontal transfer path 46 by four electrodes in one HD period. That is, the electric charge existing on the electrode of φV1 moves through the electrode of φV2 → φV3 → φV4 and moves onto the next electrode of φV1. The electric charge existing at the electrode of φV1 closest to the horizontal transfer path 46 passes through the electrode of φV2 → φV3 → φV4 and moves to the horizontal transfer path 46.

  As a result, one column of charge is sent to the horizontal transfer path 46 every 1 HD period. The charges on the horizontal transfer path 46 move in the direction of the output amplifier 45 every clock by the horizontal transfer pulses of φH1 and φH2, and are all output to the outside of the CCD 1 through the output amplifier 45 within one HD period. These operations are repeated within the 1VD period, and all the charges in the GB column can be output within this period. As a result, all the charges in the CCD 1 can be output in a continuous 2VD period.

  Here, how the electronic image pickup apparatus of the present embodiment controls the CCD 1 when shooting a scene where a dark building in the center and sunlight in the corners of the background exist is described. Here, as an example, the charge holding capacity is small in the order of horizontal transfer path> photodiode> vertical transfer path. A process of overflowing charges in the vertical transfer path and leaking out to the horizontal transfer path will be described with reference to FIG. 5 (the charge transfer method and the horizontal transfer method are the same as described above). Note that FIGS. 5A and 5B are the same as FIGS. 4A and 4B.

The following phenomenon occurs in capacitively supersaturated pixels or transfer paths.
As shown in FIG. 5C, when the capacity of the vertical transfer path 41 is smaller than the storage capacity of the first photodiode 43, when charge is sent from the first photodiode 43 to the vertical transfer path 41, Charges overflow on the vertical transfer path 41 and move toward the horizontal transfer path 46. Minimally generated supersaturated charge on the vertical transfer path 46 can be prevented by flowing into this electrode if there is an acceptable capacity on the neighboring electrode. However, as the portion of supersaturation spreads, the amount of charge that overflows on the vertical transfer path 41 increases, and this charge cannot be received in the vertical transfer path 41 and overflows to the horizontal transfer path 46.

  Extremely, when all the photodiodes in the vertical direction of one screen are saturated, the charge overflows when the charge is sent to the vertical transfer path 41, and the charge moves to the horizontal transfer path 46 ( Fig. 5-3). The charges sent to the vertical transfer path 41 are sequentially moved to the horizontal transfer path 46 by the vertical transfer pulse output in the horizontal blanking period every 1 HD period (FIG. 5-4). The overflowed charges continue to flow toward the horizontal transfer path 46 until all of the overflowed charges converge on the neighboring electrodes. When the vertical transfer pulse stops and the horizontal blanking period ends, the horizontal transfer pulse starts to be output, and the charge on the horizontal transfer path 46 starts to move toward the output amplifier 45. At this time, the charges that continue to overflow from the vertical transfer path 41 flow into the horizontal transfer path 46 even during the period in which the horizontal transfer path 46 is operating. Are added (FIGS. 5-5 to 5-6) and output (FIGS. 5-7). These operations are repeated within a 1VD period (FIGS. 5-8 → FIG. 5-9 →...), And all the charges on all the lines in the RG column are output. When the first photodiode 43 is supersaturated at a position close to the OB portion (second photodiode 44), as a result, charges overflow to the OB portion during horizontal transfer.

  In the electronic imaging apparatus of the present embodiment, the DSP 4 monitors a part of the signal of the OB unit at this time, compares this signal level with an error level that can be arbitrarily set in advance, and the fluctuation of the OB level is detected. When it is within this error level, normal clamping is performed. On the other hand, if the fluctuation of the OB level exceeds a preset error level, it is determined that the OB part has been damaged, and an error signal (here, B12) as indicated by B12 in FIG. In the case of “L” signal, there is no damage, and in the case of “H” signal, there is damage), the DSP 4 generates the signal and outputs this signal to the CPU 8.

  When the error signal of the OB portion is input, the CPU 8 determines that the OB portion is not damaged when this signal is “L”, and sends a clamp pulse for clamping the OB portion with a normal phase. An instruction is issued to the TG 7 to output it. On the other hand, when the error signal of the OB portion is “H”, the following processing is performed.

  When the error signal of the OB portion is “H”, the CPU 8 determines that the OB portion is damaged, and until the error signal of the OB portion switches to “L” (“α” in FIG. 1-2). ”Period), that is, until the damage of the OB portion is recovered, the OB portion clamping is controlled to stop, and the error signal of the OB portion switches from“ H ”to“ L ”. The TG 7 is controlled so as to continue to output the horizontal transfer pulses (φH1, φH2) in the above period (“β” period in FIG. 1-2) (“β” period in FIG. 1-2). Further, when the error signal of the OB section is “H” at the same time, the CPU 8 controls the reference signal generation circuit 14 for the HD signal and the VD signal so as to change the rate of the HD signal (extend the HD cycle). To do. However, the period from when the horizontal transfer pulse is stopped until the HD signal pulse is output ("γ" period in FIG. 1-2) is always the same interval when the HD signal cycle is changed or not changed. To control.

The control performed on the CCD 1 by the CPU 8 when it is determined that the OB portion is damaged will be described in more detail with reference to FIG.
When the photodiode of the CCD 1 is oversaturated and electric charge leaks to the OB portion (B9 in FIG. 1-2), the error signal in the OB portion is switched to “H” during this period (B12 in FIG. 1-2). This signal is transmitted from the DSP 4 to the CPU 8, and the CPU 8 stops the OB clamp pulse during this period (B10 in FIG. 1-2) and continues to output the horizontal transfer pulse (B2 in FIG. 1-2). , B3). Further, the CPU 8 instructs the reference signal generation circuit 14 to extend the period of the HD signal (B1 in FIG. 1-2).

  When the leaked charge converges and the OB portion of the CCD output signal falls within the error range, the error signal in the OB portion switches from “H” to “L” (B12 in FIG. 1-2). Thereafter, the CPU 8 controls the TG 7 so as to continue outputting the horizontal transfer pulse (B2 and B3 in FIG. 1-2) during the period necessary for the clamp pulse (the “β” period in FIG. 1-2). The TG 7 is controlled so that a clamp pulse is output during the “β” period in FIG. 1-2 (B10 in FIG. 1-2).

  Then, the CPU 8 stops the horizontal transfer pulse after the “β” period in FIG. 1-2 has elapsed (B2 and B3 in FIG. 1-2), and the HD signal pulse after the “γ” period in FIG. 1-2 has elapsed. Is output (B1 in FIG. 1-2), the reference signal generation circuit 14 is controlled. The control after the output of the HD signal pulse is the same as the control of the normal CCD 1 shown in FIG. Further, when the error signal of the OB portion is “L”, that is, when the OB portion is not damaged, the control of the normal CCD 1 is not changed.

3 is a timing chart for explaining the operation of the electronic imaging apparatus according to the first embodiment of the present invention. It is a timing chart for demonstrating operation | movement of the electronic imaging device which concerns on the 2nd Embodiment of this invention. 3 is a timing chart for explaining the operation of the electronic imaging apparatus according to the first embodiment of the present invention. It is a block block diagram in the electronic imaging device which concerns on the 1st Embodiment of this invention. It is a schematic diagram of CCD. It is the schematic diagram which showed the drive of CCD. FIG. 4 is a schematic diagram illustrating driving of the CCD following FIG. FIG. 4 is a schematic diagram illustrating driving of the CCD following FIG. 4-3. FIG. 4 is a schematic diagram showing CCD drive following FIG. 4-4. FIG. 5 is a schematic diagram showing CCD drive following FIG. 4-5. FIG. 7 is a schematic diagram illustrating driving of the CCD following FIG. 4-6. FIG. 8 is a schematic diagram illustrating driving of the CCD following FIG. FIG. 9 is a schematic diagram showing CCD drive following FIG. 4-8. It is a schematic diagram of CCD. It is the schematic diagram which showed the drive of CCD. FIG. 5 is a schematic diagram illustrating driving of the CCD following FIG. FIG. 5 is a schematic diagram showing CCD drive following FIG. FIG. 5 is a schematic diagram showing CCD drive following FIG. 5-4. FIG. 5 is a schematic diagram illustrating driving of the CCD following FIG. FIG. 7 is a schematic diagram illustrating driving of the CCD following FIG. 5-6. FIG. 8 is a schematic diagram illustrating driving of the CCD following FIG. FIG. 9 is a schematic diagram illustrating driving of the CCD following FIG. It is a schematic diagram in the horizontal transfer path of CCD. It is a block block diagram of an electronic imaging device showing a conventional example. It is each part operation | movement waveform diagram explaining the normal operation | movement of the electronic imaging device which shows a prior art example. It is each part operation | movement waveform diagram explaining the operation | movement at the time of the problem occurrence of the electronic imaging device which shows a prior art example.

Explanation of symbols

1 CCD (photoelectric conversion device)
2 CDS (Correlated Double Sampling Circuit)
3 AD (analog-digital conversion circuit)
4 DSP (digital signal processing circuit)
5 HDr (CCD horizontal transfer drive circuit)
6 VDr (CCD vertical transfer drive circuit)
7 TG (timing generator)
8 CPU
DESCRIPTION OF SYMBOLS 9 Lens drive circuit 10 Shooting lens 11 Aperture drive circuit 12 Aperture with shutter function 13 Release switch 14 Reference signal generation circuit

Claims (3)

Imaging means for converting an optical image of a subject into an electrical signal;
Vertical synchronization signal generating means for generating a vertical synchronization signal;
Horizontal synchronization signal generating means for generating a horizontal synchronization signal;
Vertical transfer driving means for driving a vertical transfer path in the imaging means by a vertical transfer pulse based on the vertical synchronization signal;
Horizontal transfer driving means for driving a horizontal transfer path in the imaging means by a horizontal transfer pulse based on the horizontal synchronization signal;
Frequency changing means for changing the frequency of the horizontal synchronizing signal;
Pulse number changing means for changing the number of horizontal transfer pulses;
Monitoring means for monitoring a reference portion of an output signal from the imaging means;
Clamping means for clamping the reference portion;
Clamp pulse output means for outputting a clamp pulse for performing the clamping;
Phase changing means for changing the phase of the clamp pulse output from the clamp pulse output means;
Comparing the level of the reference unit with a predetermined level, and when the level of the reference unit exceeds the predetermined level, and controlling the frequency changing means to lengthen the period of the horizontal synchronization signal, The pulse number changing means is controlled to increase the number of the horizontal transfer pulses, and further, the phase changing means is controlled to change the phase of the clamp pulse, so that the level of the reference portion is the predetermined level. An imaging apparatus comprising: control means for outputting a clamp pulse whose phase has been changed by the phase changing means after convergence within a level.   The imaging apparatus according to claim 1, wherein the horizontal transfer pulse is output until the output of the clamp pulse whose phase is changed by the phase changing unit is stopped.   The imaging apparatus according to claim 2, wherein after the output of the horizontal transfer pulse is stopped, the horizontal synchronization signal is output, and a signal synchronized with the horizontal synchronization signal is output.

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