JP4700855B2 - Imaging device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an imaging device that captures a subject image.
[0002]
[Prior art]
An example of a circuit block in a conventional imaging apparatus is shown in FIG. In the figure, reference numeral 1 denotes a solid-state imaging device in which photoelectric conversion units for converting light into an electrical signal are arranged in the vertical and horizontal directions (here, a CCD is taken as an example), and 2 is for converting an output signal of the CCD into a video signal. Correlated double sampling circuit (hereinafter referred to as CDS), 3 is an analog / digital conversion circuit (hereinafter referred to as AD) for converting an analog signal of CDS output into a digital signal, and 4 is a digital that performs various signal processing such as color signal processing and luminance signal processing. A signal processing circuit (hereinafter referred to as DSP), 5 is a CCD horizontal drive circuit (hereinafter referred to as HDr) for driving the horizontal transfer section of the CCD, 6 is a CCD vertical drive circuit (hereinafter referred to as VDr) for driving the vertical transfer section of the CCD, 7 is a timing generator (hereinafter referred to as TG) that receives a reference synchronization signal and generates various pulses necessary for driving the CCD and performing signal processing based on the reference signal. CPU for controlling the entire system, 9 a lens drive circuit for driving the focus lens and zoom lens, 10 a photographing lens composed of the focus lens and zoom lens, and 11 for driving the aperture and shutter A diaphragm driving circuit, 12 is a diaphragm / shutter for controlling the amount of light incident on the CCD, 13 is a release switch composed of a two-stage stroke, and 14 has a crystal oscillation circuit and has a horizontal synchronizing signal (hereinafter referred to as HD) and a vertical synchronizing signal. (Hereinafter referred to as VD).
[0003]
Next, the operation of the circuit block described above will be described. The subject image passes through 10 photographing lenses, and the amount of light is adjusted by 12 apertures, and is formed on 1 CCD. Here, photoelectric conversion is performed, and the result is output to the second CDS as a CCD signal. The main clocks HD and VD generated by the 14 reference signal generation circuits are output to 7 TG. With these signals as a reference, the TG uses a CCD horizontal transfer pulse, a CCD vertical transfer pulse, a CCD field shift pulse, and an electronic shutter pulse. Is generated. The CCD horizontal transfer pulse is output to 5 HDr, and the CCD vertical transfer pulse, CCD field shift pulse and electronic shutter pulse are output to 6 VDr. The 6 VDr receives the CCD vertical transfer pulse and the CCD field shift pulse output from the 7 TG, and combines them to convert the signal to a signal that has sufficient signal amplitude and frequency characteristics to drive the CCD vertical transfer unit sufficiently. And output to the vertical transfer drive unit of the CCD. The CCD of 1 receives these signals, and when the field shift pulse is input, the charge accumulated in the photodiode of the CCD is output to the vertical transfer unit. The charges that have moved to the vertical transfer section are transferred in order on the vertical transfer path to the horizontal transfer path by CCD vertical transfer pulses. The electronic shutter pulse is converted into a signal amplitude that can sufficiently drive the CCD with VDr, and then output to the CCD to control the charge accumulation time (exposure amount) in the CCD. The CCD continues to clear the charge of the photodiode during the period when the electronic shutter pulse is being input, and enters the exposure state after the electronic shutter pulse stops. In HDr 5, a CCD horizontal transfer pulse output from the TG is input, converted into a signal having signal amplitude and frequency characteristics that can sufficiently drive the horizontal transfer unit of the CCD, and output to the horizontal transfer unit of the CCD. The reset gate pulse is directly output from the TG to the CCD, and charge potential conversion is performed by fixing the output gate portion of the CCD at a constant potential. In the CCD, when these horizontal transfer pulse and reset gate pulse signal are input, the electric charge is output from the horizontal transfer unit to the CDS through the output amplifier as a CCD signal.
[0004]
2 CDS inputs the CCD output signal, converts the level difference between the feed-through part of the CCD output signal and the data part as a video signal, thereby removing low-frequency noise contained in the CCD signal, variable gain amplification function Thus, the video signal is amplified so as to obtain a desired sensitivity, and the black level is fixed by performing direct current reproduction and output to 3 AD.
[0005]
3 AD inputs a video signal of CDS output, converts this signal from an analog signal to a digital signal, and outputs it to a DSP 4.
[0006]
The 4 DSP receives a digital video signal and reproduces a luminance signal and a color signal by signal processing. Further, a part of the video signal is integrated to generate a reference signal for performing exposure control, a reference signal for performing white balance control, and a reference signal for performing focus control.
[0007]
Next, an image sensor driving method in a conventional camera will be described with reference to FIGS. When the shutter button having a two-step stroke is pressed one step (hereinafter SW1 is turned on), a preparatory operation for photographing is performed in the camera. First, exposure control of the CCD is performed by a combination of an aperture, an electronic shutter, and a field shift pulse, and a part of the CCD signal obtained by thinning out the vertical direction is read. For example, in the case of a CCD in which RGB filters as shown in FIG. 2 are arranged, the R / G column and the G / B column are output in order for each horizontal period within one field (1 / By reading out the column marked with ○ in the 4 thinning column, the pixels in the vertical direction are thinned out, and the CCD signal is output so that the VD rate is suitable for signal processing. In this example, as shown in the first half ((1) to (2)) of FIG. 12, the first field field shift pulse (from (1) to (1) in FIG. 12) is set so that the signal read from the CCD is the same in all fields. Only the first field signal (FIG. 12, (1) to (2), I7) is read using only (2), H7). Furthermore, since only two of the eight vertical directions are read out, the field rate for reading out the signal is twice as fast as the field rate for reading out all the lines at the time of photographing.
[0008]
During this photographing preparation operation, the CCD is driven by a predetermined VD and outputs a CCD signal for one field during this 1 VD period. As described above, signals thinned out to two out of eight in the vertical direction in the CCD are always read out. The electric charge accumulated in the photodiode of the CCD moves to the vertical transfer path by the field shift pulse for the first field synchronized with VD.
[0009]
The signal output from the CCD is converted into a video signal suitable for signal processing by CDS, and converted from an analog signal to a digital signal by AD. The DSP generates a reference signal for exposure control (hereinafter referred to as AE evaluation value) from this signal. The CPU determines the aperture value and the shutter speed by calculation so that the AE evaluation value is within a predetermined value (appropriate level), changes the aperture so that the appropriate aperture value is obtained, and also uses the electronic shutter. Change the speed to an appropriate value. Normally, when the SW1 is kept ON, this operation is repeated, and control is performed so that an appropriate exposure amount is always obtained.
[0010]
In addition, focusing control is performed simultaneously, and a reference signal (hereinafter referred to as AF evaluation value) for focusing control is also generated by the DSP. The CPU controls the movement of the focus lens so that the AF evaluation value falls within a predetermined value (focus level). That is, a clear subject image can be obtained by setting the AF evaluation value within the focus level. If the normal SW1 is kept in the ON state, the focus lens is fixed at the position once in focus.
[0011]
Further, white balance control is performed, and a reference signal (hereinafter referred to as WB evaluation value) for color balance control is also generated by the DSP. The color balance is determined by calculating the amount of white shift from this WB evaluation value. This is a color balance correction for reproducing white to a faithful white even under different light sources or in the shade of the sun.
[0012]
Next, when the shutter button having a two-stage stroke is pressed in two stages (hereinafter, SW2 is turned on), the camera shifts to a main photographing operation.
[0013]
First, exposure control is performed by combining an electronic shutter, an aperture, and a mechanical shutter so as to meet the shooting conditions determined during the shooting preparation operation. The exposure starts when the electronic shutter is stopped and the clearing of the photodiode is stopped, and the exposure ends by closing the mechanical shutter. Therefore, exposure is started by outputting the electronic shutter (FIG. 12, (3), D7) for a certain period in synchronism with VD (FIG. 12, (3)) that shifts from preparation for shooting to actual shooting. Next, a shutter close control signal is output from the CPU (FIG. 12, (3), E7), and the shutter is closed within an instant by the aperture / shutter control circuit (FIG. 12, (3), F7), and the exposure is completed. Let However, since a certain amount of time is actually required until the shutter is fully closed, the CPU outputs a shutter close control signal so that the exposure time is appropriate in consideration of this period in advance. Therefore, the exposure period is a period shown in FIG. 12, (3), G7.
[0014]
The CPU outputs a shutter close control signal, closes the mechanical shutter, and then instructs the TG to output a first field field shift pulse synchronized with the next VD (FIG. 12, (4)). As a result, the field shift pulse for the first field (FIG. 12, (4), H7) synchronized with the VD is output from the TG, and the charge of the first field is output to the vertical transfer path. At this time, a part of the video signal thinned out by one line in the vertical direction is read from the CCD. In the case of the CCD in which the RGB filters shown in FIG. 1 are arranged, the signals are divided into R / G columns and G / B columns, and the respective signals are read out sequentially in one field. A column with a circle in the first field readout column is read out in the first 1 VD period by the field shift pulse for the first field (FIG. 12, (4), I7). Further, the CPU issues a command to the TG to output the second field shift pulse synchronized with the next successive VD (5). As a result, the field shift pulse for the second field synchronized with the next continuous VD is output from the TG (FIG. 12, (5), J7), and the charge of the second field is output to the vertical transfer path. The column with a circle in the second field readout column in FIG. 2 is read out in the next VD period following the first field by the field shift pulse for the second field (FIG. 12, (5), K7). As a result, a signal thinned out by one line in the vertical direction within 1 VD period is read out, and all the pixels in the CCD are read out during continuous 2 VD periods. Since the number of lines read from the CCD is determined, the 1VD rate is determined by the number of HDs depending on the number of read lines.
[0015]
That is, the CCD is driven with a predetermined HD and VD cycle, and outputs one line of CCD signal in this 1HD period and outputs one field of CCD signal in 1VD period. During normal shooting, the video thinned out for each vertical line in the CCD is taken as one field, the first one field (first field) is read out with the first 1 VD, and thinned out in the CCD with the next consecutive VD. The next one field (second field) is read out. All electric charges (complete one image) in the CCD can be read out in a continuous 2VD period.
[0016]
For this purpose, the CPU counts the number of HDs generated by the reference signal generation circuit, and instructs the output of the VD signal after counting the prescribed number. Therefore, HD and VD can always be supplied to the TG in the same cycle. Since the TG generates various pulses based on the VD, it starts counting the number of HDs from the time when the VD is input, and outputs a series of pulses according to the counted number. For example, TG is programmed to output a field shift pulse after 8 counts of HD after VD input. After inputting the VD pulse, the counter is reset and recounted.
[0017]
On the other hand, the charges output to the vertical transfer path are sequentially sent to the horizontal transfer path every 1 HD period by a 4-phase vertical transfer pulse (FIG. 11, P7, Q7, R7, S7) synchronized with HD in VD. Further, the two-phase horizontal transfer pulse (FIG. 11, N7, O7) output from the TG is output to the horizontal transfer path via HDr, and all charges in the horizontal direction are output from the CCD to the CDS within the 1H period. As a result, all charges for one field can be output from the CCD within a 1V period.
[0018]
Next, the state when the shutter speed changes according to the exposure conditions will be described. As described above from the exposure to the charge readout, the period until the electronic shutter pulse is stopped, the shutter close command is output from the CPU, and the mechanical shutter is closed is the exposure period (FIG. 12, (3), G7). From this point in time until the next readout pulse is output, this is the period during which charges are held in the photodiode of the CCD (FIG. 12, (3), L7). When the high-speed shutter is used, the exposure period is shortened, but the charge holding period in the CCD is lengthened. On the other hand, when a low shutter speed that can be accommodated within 1 VD period is used, the electronic shutter pulse stops, the shutter close command is output from the CPU (FIG. 12, (3), E8), and the mechanical shutter is closed. Is the exposure period (FIG. 12, (3), G8), and from this point until the next readout pulse is output, this is the period during which charge is held in the photodiode of the CCD (FIG. 12, (3), L8). Conversely, the exposure period becomes longer, but the charge retention period of the CCD becomes shorter. Further, when the shutter speed is longer than 1 VD, the electronic shutter pulse stops, the shutter close command is output from the CPU (FIG. 12, (3), E9), and the mechanical shutter is closed. Is the exposure period (FIG. 12, (3), G9), and the period from this point until the next readout pulse is output is the period in which the charge is held in the CCD photodiode (FIG. 12, (3), L9). When the timing of closing the mechanical shutter is close to the next appearing VD, the charge holding period of the CCD is shortened. Conversely, when the timing of closing the mechanical shutter is far from the next appearing VD, the charge holding period of the CCD is lengthened. In the case shown in FIG. 12, the period in which charge is held in the photodiode of the CCD becomes longer in the order of using the low-speed shutter, the high-speed shutter, and the long-time shutter, and this period is not always constant, and the shutter speed Variations occur depending on the conditions.
[0019]
As is generally known, when the charge holding period of the CCD becomes longer, the charge on the photodiode decreases exponentially with the holding period, and even if the charge amount is made constant by exposure, the charge holding of the CCD If the period is different, the amount of charge output to the vertical transfer path is different, resulting in an image having a different D range.
[0020]
In addition, since a dark voltage is always generated in the CCD, if the charge retention period of the CCD becomes long, the dark voltage increases accordingly, and noise increases. This also depends on the temperature change, and the dark voltage increases about twice as much as 8 degrees. If the CCD is kept in the charge holding state, it is clearly disadvantageous against the dark voltage due to the temperature rise of the device itself. .
[0021]
[Problems to be solved by the invention]
However, as described above, the conventional example has the following problems depending on the timing of closing the shutter.
[0022]
First, it is necessary to keep the charge in a photodiode or the like for a long period of time, resulting in an increase in dark current and a noticeable image. If the charge is held in the photodiode or the like for a long period of time, the charge in the photodiode is reduced by the holding period, and an image with a small D range is obtained.
[0023]
Further, when the exposure time is made different, the period in which the charge is kept in the photodiode or the like is different, and the dark current is uneven. In addition, the period during which the photodiode continues to hold charges is different, and unevenness occurs in the D range.
[0024]
In view of the above problems, it is an object to prevent an increase in dark current by shortening the time from the end of an exposure time until the start of reading of a signal generated by exposure.
[0025]
Another object is to reduce dark current unevenness by making the time from the end of the exposure time to the start of reading of the signal generated by the exposure the same even when the exposure time is different.
[0026]
[Means for Solving the Problems]
  The present invention has been made to solve the above-described problems, and includes an imaging unit in which photoelectric conversion units that convert light into an electrical signal are arranged in a vertical direction and a horizontal direction, and a light shielding unit for shielding the imaging unit. A driving means for driving the imaging means; a reference signal generating means for generating a horizontal synchronizing signal and a vertical synchronizing signal; and an exposure period from when the imaging means is reset until the imaging means is shielded by the light shielding means Thereafter, the reference period is set such that the period of the horizontal synchronization signal is shorter than that in the case of reading out the optical signal during at least a part of the period until the reading of the optical signal generated in the photoelectric conversion unit is started during the exposure period. Control means for controlling the signal generating means.
[0027]
DETAILED DESCRIPTION OF THE INVENTION
First, the configuration of the entire block diagram of the imaging apparatus common to Embodiments 1 to 3 is the same as that of the imaging apparatus of FIG.
[0028]
(Embodiment 1)
This embodiment will be described with reference to the circuit block of FIG. 3 and the timing chart of FIG.
[0029]
First, when SW1 is turned on, a preparatory operation for photographing is performed in the camera. First, exposure of a CCD as an imaging means is controlled by a combination of an aperture, an electronic shutter, and a field shift pulse, and a part of the CCD signal thinned out in the vertical direction is read out. For example, in the case of a CCD in which the RGB filters as shown in FIG. 2 are arranged as in the conventional example, the R / G column and the G / B column are output in order in each horizontal period within one field. The pixels in the vertical direction are thinned out by reading out the data (the column with a circle in the 1/4 thinning column), and the CCD signal is output at a rate suitable for signal processing. In this example, as shown in the first half ((1) to (2)) of FIG. 4, the first field field shift pulse (from (1) to (1) in FIG. 4) is set so that the signal read from the CCD is the same in all fields. Only the first field signal (FIG. 4, (1) to (2), I1) is read using only (2), H1). Furthermore, since only two of the eight vertical directions are read out, the field rate for reading out signals is twice as fast as the field rate for reading out all lines during shooting.
[0030]
During this photographing preparation operation, the CCD is driven by a predetermined VD and outputs a CCD signal for one field during this 1 VD period. As described above, a thinning signal obtained by reading out two of the eight vertical directions in the CCD is always read out. The electric charge accumulated in the photodiode of the CCD moves to the vertical transfer path by the field shift pulse for the first field synchronized with VD.
[0031]
The signal output from the CCD is converted into a video signal suitable for signal processing by CDS, and converted from an analog signal to a digital signal by AD. From this signal, the DSP generates an AE evaluation value for exposure control. The CPU determines the aperture value and the shutter speed by calculation so that the AE evaluation value falls within a predetermined value (appropriate level), changes the aperture so as to obtain an appropriate aperture value, and electronic shutter speed. Change to the appropriate value. Normally, when the SW1 is kept ON, this operation is repeated, and control is performed so that an appropriate exposure amount is always obtained.
[0032]
Further, focusing control is performed at the same time, and an AF evaluation value for focusing control is also generated by the DSP. The CPU controls the movement of the focus lens so that the AF evaluation value falls within a predetermined value (focus level). That is, a clear subject image can be obtained by setting the AF evaluation value within the focus level. If the normal SW1 is kept in the ON state, the focus lens is fixed at the position once in focus.
[0033]
Further, white balance control is performed, and a WB evaluation value for color balance control is also generated by the DSP. The color balance is determined by calculating the amount of white shift from this WB evaluation value. This is a color balance correction for reproducing white to a faithful white even under different light sources or in the shade of the sun.
[0034]
Next, when SW2 is turned on, the camera shifts to a main photographing operation.
[0035]
First, exposure control is performed by combining an electronic shutter, an aperture, and a mechanical shutter so as to meet the shooting conditions determined during the shooting preparation operation. The exposure starts when the electronic shutter is stopped and the clearing of the photodiode is stopped, and the exposure ends by closing the mechanical shutter. Therefore, exposure is started by outputting the electronic shutter (FIG. 4, (3), D1) for a certain period in synchronism with VD (FIG. 4, (3), A1) which shifts from preparation for shooting to actual shooting. Next, a shutter close control signal is output from the CPU (FIG. 4, (3), E1), and the shutter is closed within a moment by the aperture / shutter control circuit (FIG. 4, (3), F1), and the exposure is completed. Let However, since a certain amount of time is actually required until the shutter is fully closed, the CPU outputs a shutter close control signal so that the exposure time is appropriate in consideration of this period in advance. Therefore, the exposure period is the period shown in (FIG. 4, (3), G1).
[0036]
The CPU that is the control means outputs a shutter close control signal, and after closing the mechanical shutter, the HD rate is increased (FIG. 10, B4) until the next VD (FIG. 4, (4), A1). The reference signal generation circuit is instructed to supply HD to the TG. For example, if 1VD is composed of 525 HDs, the CPU counts 525 HDs from the output of VD to the output of the next VD, and generates the reference signal after counting this specified number Instructs the circuit to output a new VD. Then, after detecting that the shutter is closed, a period until a new VD is output after the prescribed number of HDs (FIG. 4, (4), C1), the CPU is sent to the reference signal generation circuit so as to increase the HD rate. Issues an order.
[0037]
Since the TG generates various pulses based on the VD, it starts counting the number of HDs when a new VD is input, and outputs a series of pulses according to this count. For example, TG is programmed to output a field shift pulse after 8 counts of HD after VD input. After inputting the VD pulse, the counter is reset and recounted.
[0038]
As described above, the CPU sets the reference so that the HD is driven at high speed in the HD change period after the exposure period ends and until the field shift pulse (FIG. 4, (4), H1) is output. By controlling the signal generation circuit, the period during which charges are held in the photodiode can be shortened as much as possible.
[0039]
Here, the operation state of the horizontal transfer pulse and the vertical transfer pulse when the HD rate is high will be described with reference to FIG.
[0040]
When the HD rate is set to high speed (FIG. 10, B4), it is continuously output (FIG. 10, N4, O4), or output other than the horizontal blanking period (period in which the vertical transfer pulse is stopped) (FIG. 10, N5, O5) or not output at all (FIG. 10, N6, O6). As for the vertical transfer pulse, a pulse with four phases may be output as usual (FIG. 10, P5, Q5, R5, S5), or not output at all (FIG. 10, P4, Q4, R4, S4). Keep it.
[0041]
When the vertical transfer pulse and the horizontal transfer pulse are stopped, current consumption for driving the CCD can be suppressed.
[0042]
Next, reading of photoelectric charges generated in the photodiode of the CCD during the exposure period will be described.
[0043]
Since the CCD is designed to be driven with a predetermined HD cycle, it is expected that charge transfer will not be performed correctly if the HD rate is changed. If charges remain in the vertical transfer path, they overlap when the next field shift pulse is input and charges are transferred from the photodiode.
[0044]
In order to prevent this, a command is issued from the CPU to the TG so as not to output a field shift pulse synchronized with the first VD that has shifted to the main photographing. Thereby, in order to obtain the CCD output, the first field field shift pulse is outputted, and when the charge of the first field is outputted to the vertical transfer path, the vertical transfer path is empty.
[0045]
When the count of HD reaches the specified count (FIG. 4, (4)), the CPU instructs the reference signal generation circuit to output VD, and from this point on, the HD rate is set to the normal rate. To return to TG and output to TG. A command is issued to the TG so as to output a field shift pulse for the first field synchronized with the VD. As a result, the TG outputs a field shift pulse for the first field synchronized with the VD, and the CCD moves the charge of the first field to the vertical transfer path. At this time, a part of the video signal thinned out by one line in the vertical direction is read from the CCD. In the case of the CCD in which the RGB filters shown in FIG. 1 are arranged, the signals are divided into R / G columns and G / B columns, and the respective signals are read out sequentially in one field. A column with a circle in the first field readout column is read out in the first 1 VD period by a field shift pulse for the first field (FIG. 4, (4), H1) (FIG. 4, (4), I1). Further, the CPU issues a command to the TG to output a field shift pulse for the second field synchronized with the next successive VD. As a result, a field shift pulse for the second field synchronized with the next successive VD (FIG. 4, (5), A1) is output from the TG (FIG. 4, (5), J1), and the charge in the second field is reduced. Output to the vertical transfer path. The column with a circle in the second field readout column in FIG. 2 is read out in the next VD period following the first field by the field shift pulse for the second field (FIG. 4, (5), K1). As a result, a signal thinned out by one line in the vertical direction within 1 VD period is read out, and all the pixels in the CCD are read out during continuous 2 VD periods.
[0046]
The charges output to the vertical transfer path are sequentially sent to the horizontal transfer path every 1H by four-phase vertical transfer pulses (FIG. 11, P7, Q7, R7, S7) synchronized with HD. Further, the two-phase horizontal transfer pulse (N7, O7 in FIG. 11) output from the TG is output to the horizontal transfer path by HDr, and all charges in the horizontal direction are output from the CCD to the CDS within the 1H period. As a result, all charges for one field can be output from the CCD within a 1V period.
[0047]
(Embodiment 2)
The imaging device according to the present embodiment will be described with reference to FIGS. First, when SW1 is turned on, a preparatory operation for photographing is performed in the camera. First, exposure control of the CCD is performed by a combination of an aperture, an electronic shutter, and a field shift pulse, and a part of the CCD signal obtained by thinning out the vertical direction is read out. For example, in the case of a CCD in which RGB filters as shown in FIG. 2 are arranged as in the first embodiment, the R / G column and the G / B column are output in order for each horizontal period within one field. In such a manner (by reading the column with a circle in the 1/4 thinning column), the pixels in the vertical direction are thinned out, and the CCD signal is output at a rate suitable for signal processing. In this example, as shown in the first half ((1) to (2)) of FIG. 5, the first field field shift pulse (from (1) to (1) in FIG. 5) is set so that the signal read from the CCD is the same in all fields. Using only (2), H2), only the first field signal (FIG. 5, (1) to (2), I2) is read. Furthermore, since only two of the eight vertical directions are read out, the field rate for reading out signals is twice as fast as the field rate for reading out all lines during shooting.
[0048]
During this photographing preparation operation, the CCD is driven by a predetermined VD and outputs a CCD signal for one field during this 1 VD period. As described above, a thinning signal obtained by reading out two of the eight vertical directions in the CCD is always read out. The electric charge accumulated in the photodiode of the CCD moves to the vertical transfer path by the field shift pulse for the first field synchronized with VD.
[0049]
The signal output from the CCD is converted into a video signal suitable for signal processing by CDS, and converted from an analog signal to a digital signal by AD. From this signal, the DSP generates an AE evaluation value for exposure control. The CPU determines the aperture value and the shutter speed by calculation so that the AE evaluation value falls within a predetermined value (appropriate level), changes the aperture so as to obtain an appropriate aperture value, and electronic shutter speed. Change to the appropriate value. Normally, when the SW1 is kept ON, this operation is repeated, and control is performed so that an appropriate exposure amount is always obtained.
[0050]
Further, focusing control is performed at the same time, and an AF evaluation value for focusing control is also generated by the DSP. The CPU controls the movement of the focus lens so that the AF evaluation value falls within a predetermined value (focus level). That is, a clear subject image can be obtained by setting the AF evaluation value within the focus level. If the normal SW1 is kept in the ON state, the focus lens is fixed at the position once in focus.
[0051]
Further, white balance control is performed, and a reference signal (hereinafter referred to as WB evaluation value) for color balance control is also generated by the DSP. The color balance is determined by calculating the amount of white shift from this WB evaluation value. This is a color balance correction for reproducing white to a faithful white even under different light sources or in the shade of the sun.
[0052]
Next, when SW2 is turned on, the camera shifts to a main photographing operation.
[0053]
First, exposure control is performed by combining an electronic shutter, an aperture, and a mechanical shutter so as to meet the shooting conditions determined during the shooting preparation operation. The exposure starts when the electronic shutter is stopped and the clearing of the photodiode is stopped, and the exposure ends by closing the mechanical shutter. Therefore, the exposure is started by outputting the electronic shutter (FIG. 5, (3), D2) for a certain period in synchronism with VD (FIG. 5, (3), A2) which shifts from the preparation for photographing to the actual photographing. Next, a shutter close control signal is output from the CPU (FIG. 5, (3), E2), the shutter is closed within a moment by the aperture / shutter control circuit (FIG. 5, (3), F2), and the exposure ends. Let However, since a certain amount of time is actually required until the shutter is fully closed, the CPU outputs a shutter close control signal so that the exposure time is appropriate in consideration of this period in advance. Therefore, the exposure period is the period shown in (FIG. 5, (3), G2).
[0054]
The CPU outputs a shutter close control signal, and after closing the mechanical shutter, the reference signal generator circuit outputs the VD signal to the TG immediately (FIG. 5, (4), A2) without observing the continuous VD cycle. This resets the TG. It is assumed that 1VD at the time of the main photographing operation is composed of 525 HDs. The CPU detects that the shutter is closed, and instructs the reference signal generation circuit to output the next VD after elapse of k * horizontal period (HD) time (k is variable from 1 to 525).
[0055]
Since TG generates various pulses based on VD, when VD is input, a new series of pulses can be output from that point. The TG is programmed to count the number of HD pulses after the VD pulse is input, and output a field shift pulse after 8 counts, for example.
[0056]
After inputting the VD pulse, the counter is reset and recounted, so that the phase relationship between VD and the field shift pulse is always kept the same. With this configuration, the VD pulse is input and a field shift pulse is output after a certain period (8 HD in this case) without being captured by the periodicity of the VD, and the charge can be read from the photodiode of the CCD.
[0057]
Therefore, the CPU detects or predicts that the mechanical shutter is closed, and always outputs VD to the TG at the same interval from that point, so that the signal from the CCD is always sent at regular intervals after the mechanical shutter is closed regardless of the shutter speed. Can be read out.
[0058]
On the other hand, the CCD is driven by a predetermined VD cycle, and a video signal of one field is output by this 1VD. Therefore, if the VD cycle is shortened, all charges output to the vertical transfer path cannot be output to the horizontal transfer path. The charges left in the vertical transfer path overlap each other when the next field shift pulse is input and the charges are transferred from the photodiode. In order to prevent this and to remove smear leaking into the vertical transfer path and dark voltage generated on the vertical transfer path, vertical transfer pulses are continuously output to the vertical transfer path within several H periods. .
[0059]
Since the maximum effect is obtained by performing these operations immediately before outputting charges to the vertical transfer path, the vertical transfer pulses must be continuously output at high speed immediately before the field shift pulse is output.
[0060]
For example, by outputting a pulse so that this high-speed transfer can be transferred for about 32 stages in 1H period and repeating high-speed transfer for 23H period, a total of 736 stages can be transferred. Although the number of vertical transfer lines is 525, it is usually set to be larger than the total number of vertical lines in consideration of insufficient charge transfer efficiency for high-speed transfer. Therefore, at least the high-speed transfer pulse must be output 23H before the field shift pulse is output.
[0061]
Since the 8H period is from VD to the field shift pulse now, the vertical transfer transfer pulse must be output at a high speed from 15H before VD. An output from around 20H with a margin of several H may be used.
[0062]
If 1VD is set to 1/525 times HD during the main photographing operation (525 HD pulses exist in 1VD), a high-speed vertical transfer pulse is output at 510H.
[0063]
TG starts counting HD after being reset by VD, and outputs a high-speed transfer pulse after counting 510H (FIG. 5, (4), M2). Therefore, the charge must be held in the CCD during this VD period (FIG. 5, (4), L2). In order to shorten this period, in this embodiment, the 510H period from the VD to the output of the high-speed transfer pulse is set to a rate higher than the normal HD rate, and the period up to 510H is shortened. (FIG. 5, (4), B2).
[0064]
When the HD rate is about 10 times the normal speed, the reference signal generation circuit outputs the HD pulse to the TG with the HD rate increased at a high speed in the 51H period at the normal HD rate, and then returns to the normal HD rate and the high speed. Output a vertical transfer pulse. As a result, when 1VD requires 525 HDs, it can be accelerated to a period of about 74 HD (normal rate).
[0065]
As a result, even if the main shooting is started and the first field field shift pulse (FIG. 5, (3), H2) synchronized with the first VD is output, all the charges output to the vertical transfer path at this time are CCD. Can be spit out of.
[0066]
However, as described in the first embodiment, the field shift pulse synchronized with VD may be prohibited.
[0067]
In addition, the CPU controls the reference signal generation circuit so that the HD is driven at high speed during the HD change period from the end of the exposure period to the high-speed sweep (FIG. 5, (5), M2). Thus, the period during which charges are held in the photodiode can be shortened as much as possible.
[0068]
Here, the operation state of the horizontal transfer pulse and the vertical transfer pulse when the HD rate is high will be described with reference to FIG.
[0069]
When the HD rate is set to high speed (FIG. 10, B4), it is continuously output (FIG. 10, N4, O4), or output other than the horizontal blanking period (period in which the vertical transfer pulse is stopped) (FIG. 10, N5, O5) or not output at all (FIG. 10, N6, O6). As for the vertical transfer pulse, a pulse with four phases may be output as usual (FIG. 10, P5, Q5, R5, S5), or not output at all (FIG. 10, P4, Q4, R4, S4). Keep it.
[0070]
When the vertical transfer pulse and the horizontal transfer pulse are stopped, current consumption for driving the CCD can be suppressed.
[0071]
Next, the operation when the HD rate is returned to the normal rate and the vertical transfer pulse is increased will be described with reference to FIG.
[0072]
Normally, the vertical transfer pulse operates so as to output the charge for one line per 1HD (FIG. 11, B1) to the horizontal transfer path (FIG. 11, P7, Q7, R7, S7). However, in the case of high-speed vertical transfer, in this example, the vertical transfer pulse operates so as to output charges for 32 lines per HD to the horizontal transfer path (FIG. 11, P8, Q8, R8, S8).
[0073]
Next, reading of photoelectric charges generated in the photodiode of the CCD during the exposure period will be described.
[0074]
The CPU outputs a shutter close control signal (FIG. 5, (3), E2), and then detects or predicts that the mechanical shutter is closed, and then outputs a VD signal to the TG after a certain period of time. An instruction is issued to the signal generation circuit, and TG is reset by outputting VD from the reference signal generation circuit to the TG.
[0075]
During the period from this VD to the next VD, a high-rate HD and a normal-rate HD (for high-speed transfer) are combined, and after a prescribed HD count (here, 525), a VD pulse is output to the TG (FIG. 5, (5), A2). The TG outputs a field shift pulse for the first field synchronized with the VD (FIG. 5, (5), H2), and the CCD moves the charge of the first field to the vertical transfer path. At this time, a part of the video signal thinned out by one line in the vertical direction is read from the CCD. In the case of the CCD in which the RGB filters shown in FIG. 1 are arranged, the signals are divided into R / G columns and G / B columns, and the respective signals are read out sequentially in one field. A column with a circle in the first field readout column is read out in the first 1 VD period by the field shift pulse for the first field (FIG. 5, (5), H2) (FIG. 5, (5), I2). Further, the CPU issues a command to the TG so as to output the field shift pulse for the second field synchronized with the next successive VD (FIG. 5, (6), A2). As a result, the field shift pulse for the second field synchronized with the next continuous VD is output from the TG (FIG. 5, (6), J2), and the charge of the second field is output to the vertical transfer path. The column with a circle in the second field readout column in FIG. 2 is read out in the next VD period following the first field by the field shift pulse for the second field (FIG. 5, (6), K2). As a result, a signal thinned out by one line in the vertical direction within 1 VD period is read out, and all the pixels in the CCD are read out during continuous 2 VD periods.
[0076]
The charges output to the vertical transfer path are sequentially sent to the horizontal transfer path every 1H by four-phase vertical transfer pulses (FIG. 11, P7, Q7, R7, S7) synchronized with HD. Further, the two-phase horizontal transfer pulse (N7, O7 in FIG. 11) output from the TG is output to the horizontal transfer path by HDr, and all charges in the horizontal direction are output from the CCD to the CDS within the 1H period. As a result, all charges for one field can be output from the CCD within a 1V period.
[0077]
Next, the state when the shutter speed changes according to the exposure conditions will be described.
[0078]
FIG. 5 is a timing chart when the high shutter speed is used, FIG. 6 is a timing chart when the low shutter speed is used, and FIG. 7 is a timing chart when the long shutter speed is used.
[0079]
In either case, the electronic shutter pulse is stopped and a shutter close command is output from the CPU (FIG. 5, (3), E2) (FIGS. 6, (3), E2) (FIGS. 7, (3), E2). The period until the mechanical shutter is closed is the exposure period (Fig. 5, (3), G2) (Fig. 6, (3), G2) (Fig. 7, (3) and (4), G2). The period until the next readout pulse is output is a period in which charges are held in the photodiode of the CCD (FIG. 5, (4), L2) (FIGS. 6, (4), L2) (FIG. 7, (5) ▼, L2).
[0080]
As described above, under each condition, the timing of VD after completion of exposure is the same under all conditions, and the next 1 VD period can be set to the same time. The period from when it is closed to when the field shift pulse for the first field is output is equal.
[0081]
(Embodiment 3)
The imaging apparatus of this embodiment will be described with reference to FIGS. Below, a different part from Embodiment 2 is demonstrated, and it abbreviate | omits about the same part.
[0082]
First, the operation of FIG. 8 will be described.
[0083]
In the present embodiment, all the HDs are driven at a high rate for a 1 VD period for discharging the dark voltage (FIG. 8, (4)), and vertical transfer is performed by a normal vertical transfer pulse. That is, when driving at a normal HD rate, the period during which the vertical transfer pulse was output is left as it is, and the other periods are shortened to increase the HD rate.
[0084]
Since all the 1VD periods are transferred at a high-speed HD rate, the period during which the photodiode holds the charge is shortened. In addition, since this period is always a constant period, there is no variation even when the shutter speed is different.
[0085]
The operation when the HD is set to a high rate will be described with reference to FIGS.
[0086]
For example, a high-speed HD is used so that 10 HD pulses are output within a normal HD (FIG. 10, B1) period, and a vertical transfer pulse synchronized with this HD is output (FIG. 10, P5, Q5). , R5, S5), to play the same role as high-speed transfer. At this time, since the dark voltage signal is sent to the horizontal transfer path at a high speed, the horizontal transfer pulse is operated (FIG. 10, N4, O4, or FIG. 10, N5, O5), and this signal is moved outside the CCD. It is necessary to exhale.
[0087]
After the VD output, the horizontal transfer pulse is returned to the normal transfer (FIG. 11, N7, Q7). However, when the vertical transfer is performed at high speed, the charges overflow on the horizontal transfer path and not all charges can be transferred. Therefore, after high-speed transfer, it is necessary to return to the normal HD rate for a period of at least 1 HD and discharge all charges on the horizontal transfer path.
[0088]
Next, with reference to FIG. 9, another operation regarding charge reading will be described.
[0089]
After the first field is read (FIG. 9, (5), I3), until the second field field shift pulse is output (FIG. 9, (7), J3), the vertical transfer path A 1VD period (FIG. 9, (6), A3) for discharging the dark voltage is provided, and all HDs are driven at a high rate during the 1VD period before the field shift pulse for the second field is output. Performed by vertical transfer pulse. That is, when driving at a normal HD rate, the period during which the vertical transfer pulse was output is left as it is, and the other periods are shortened to increase the HD rate. After the discharge of the dark voltage is completed, a field shift pulse for the second field is output (FIG. 9, (7), J3), and the charge is moved from the CCD photodiode to the vertical transfer path to obtain the CCD output (FIG. 9). , (7), K3). Therefore, the 1VD period for discharging the dark voltage immediately before the first field field shift pulse and the second field field shift pulse is in the same state, and this period is always a constant period and there is no variation. The field shift pulse synchronized with the 1VD period for discharging the dark voltage is prohibited in advance.
[0090]
As described above, the first to third embodiments have the following effects.
[0091]
The period during which charges are held in the photodiode can be controlled, and this period can be set short, so that dark current can be suppressed and noise can be suppressed as much as possible. In addition, a reduction in the charge of the photodiode can be suppressed as much as possible, and a reduction in the D range can be prevented.
[0092]
Regardless of the shutter speed, the period during which charges are held in the photodiode can be made constant, so that dark current is not uneven. In addition, the shutter speed does not cause unevenness in the D range.
[0093]
Regardless of the timing at which the shutter closes, such as continuous shooting, the shooting interval can always be constant and the shooting interval can be shortened.
[0094]
Even when a CCD having a large total number of pixels is used, -pixels can be read out at high speed without being caught by the VD rate.
[0095]
Current consumption when driving the CCD can be suppressed.
[0096]
【The invention's effect】
In the present invention, it is possible to obtain a high-quality video.
[Brief description of the drawings]
FIG. 1 is a diagram showing a pixel array of a CCD for explaining an embodiment and a conventional example.
FIG. 2 is a diagram illustrating a pixel array of a CCD for explaining an embodiment and a conventional example.
FIG. 3 is a block diagram of an image pickup apparatus for explaining an embodiment and a conventional example.
FIG. 4 is a timing chart for explaining Embodiment 1;
FIG. 5 is a timing chart for explaining the second embodiment;
FIG. 6 is a timing chart for explaining the second embodiment;
FIG. 7 is a timing chart for explaining the second embodiment;
FIG. 8 is a timing chart for explaining Embodiment 3;
FIG. 9 is a timing chart for explaining the third embodiment;
FIG. 10 is a timing chart for explaining the first to third embodiments.
FIG. 11 is a timing chart for explaining the first to third embodiments.
FIG. 12 is a timing chart for explaining a conventional example.
[Explanation of symbols]
1 CCD
2 CDS
3 AD
4 DSP
5 HDr
6 VDr
7 TG
8 CPU
9 Lens drive circuit
10 Shooting lens
11 Aperture drive circuit
12 Aperture
13 Release switch
14 Reference signal generation circuit

Claims (3)

Imaging means in which photoelectric conversion units that convert light into electrical signals are arranged in the vertical and horizontal directions ;
A light shielding means for shielding the imaging means;
Driving means for driving the imaging means;
Reference signal generating means for generating a horizontal synchronizing signal and a vertical synchronizing signal ;
After the exposure period from the reset of the imaging unit to the time when the imaging unit is shielded by the light shielding unit , at least part of the time from the start of reading of the optical signal generated in the photoelectric conversion unit during the exposure period Control means for controlling the reference signal generating means such that the period of the horizontal synchronization signal is shorter than the period when the optical signal is read out ,
An imaging device comprising: Wherein, according to said synchronization with the next of said vertical synchronizing signal after the exposure period, and controlling said drive means so as not to output a pulse for starting the reading of the optical signal Item 2. The imaging device according to Item 1 . It said control means, characterized in that the period of the horizontal synchronizing signal when is shorter than the case of reading the optical signal is controlled so as to stop the vertical transfer driving and / or horizontal transfer driving of the image pickup means The imaging apparatus according to claim 1 or 2 .

Images