JP4639687B2 - Voltage variation suppression method for voltage-driven semiconductor devices - Google Patents

Description

  The present invention relates to a control method for suppressing variations in device voltage of a plurality of voltage-driven semiconductor devices connected in series.

In a power conversion device including voltage-driven semiconductor elements (also simply referred to as elements) connected in series, several methods for suppressing element voltage imbalance that occurs during switching are known. FIG. 10 shows an example of the element 2 series connection circuit.
In FIG. 10, Q1 and Q2 are IGBTs (insulated gate bipolar transistors) which are one of voltage driven semiconductor elements. The collector-emitter voltages of the elements are VCE1 and VCE2, respectively, and the gate voltages are VGE1. , VGE2.

  In FIG. 10, when Q1 and Q2 are switched, the delay time of the gate drive circuit and the element characteristics are the same, and if the switching timing is the same, the voltage sharing of the two elements becomes equal. However, in practice, these delay times vary and change with temperature, so that the switching timing of the elements is usually different. Therefore, as shown in FIG. 11, a high voltage is applied to an element that is turned off quickly or an element that is turned on late as compared with the case where the voltage sharing is equal, and if the switching timing difference is large, the element may be overvoltaged and destroyed. There is.

As a conventional means for suppressing this voltage sharing imbalance, there is a method as shown in Patent Document 1, for example, in which a snubber circuit is connected in parallel with the element. An example is shown in FIG.
This circuit is for one phase of a two-level inverter, and two IGBTs are connected in series per arm. Here, Q1 to Q4 are IGBTs, and snubber circuits each including a resistor R, a capacitor C, and a diode D are connected in parallel. GDU1 to GDU4 are gate drive circuits, and Ed is a power supply voltage.

In the circuit of FIG. 12, when the upper arm, that is, Q1 and Q2 are turned off and Q1 is turned off at a timing earlier than Q2, the operation waveform when there is no snubber circuit is shown in FIG. The waveform is shown in FIG.
Δt is a switching timing difference between Q1 and Q2, and here shows a case where Q1 is turned off at a timing earlier than Q2.

  In FIG. 13, since Q1 is off and Q2 is on during the period of Δt, only the element voltage VCE (Q1) of Q1 rises and voltage imbalance occurs. When a snubber circuit is connected to each element under this condition, the voltage increase rate (dv / dt) of the element voltage can be reduced as compared with the case where the snubber circuit is not connected. As a result, voltage imbalance during the period of Δt. Can be reduced. This dv / dt depends on the capacitance of C of the snubber circuit, and the voltage unbalance reduction effect can be increased as the capacitance is increased.

  As another system other than the above-mentioned patent document 1, there is a system in which gate lines of respective elements are magnetically coupled to each other as in, for example, patent document 2. In other words, when the gate lines are magnetically coupled, if the current value flowing through each gate line differs when the element is turned on or off, the gate line impedances instantly change according to the difference, thereby matching the gate currents. Variation in switching timing is suppressed. Since the components to be magnetically coupled, such as the core, are very small, the circuit is miniaturized.

Japanese Patent Laid-Open No. 04-125071 (page 2-3, FIG. 1) JP 2002-204578 A (3rd page, FIG. 1)

As described above, by using the snubber circuit method or the magnetic coupling method of the gate line, it is possible to suppress variations in device voltage connected in series or to reduce the circuit size. However, when the external circuit conditions of each element vary, for example, when a capacitance having a different capacitance is connected between the collector and emitter of each element due to, for example, a stray capacitance between the element and the ground, the rise of the element voltage, Since the falling time constants are different, the device voltage is unbalanced. This can be improved by connecting a snubber circuit, but it is necessary to increase the capacitor capacity of the snubber circuit, which increases the size of the circuit. Further, in the magnetic coupling method, variations in switching timing and element characteristics can be suppressed, but voltage variations due to an external circuit cannot be suppressed.
Accordingly, an object of the present invention is to suppress variations in device voltage with a simple circuit even when there are variations in switching timing, device characteristics, or voltage variations due to external circuits.

In order to solve such a problem, in the invention of claim 1, in a drive circuit for driving on / off a plurality of voltage-driven semiconductor elements connected in series for each arm of the power converter,
Between each collector and gate of each of the voltage-driven semiconductor elements, an equivalent circuit is formed of a series circuit of a capacitor and a winding, and a balance circuit in which the winding is magnetically coupled between adjacent driving circuits is connected, respectively. It is characterized by suppressing variations in voltage.
In the first aspect of the invention, adjacent voltage-driven semiconductor elements connected in series are sequentially magnetically coupled to each other via the balance circuit, so that the element voltage is controlled regardless of the number of elements connected in series. It is possible to suppress the variation of the above (invention of claim 2).

  According to the present invention, by connecting a balance circuit composed of a series circuit of a capacitor and a magnetic coupling circuit between each collector and gate of a voltage-driven semiconductor element, any variation in switch timing, element characteristics, and external circuit conditions can be obtained. Even under conditions, it becomes possible to balance element voltages.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention, and shows one phase of a two-level inverter as in FIG. This is an example in which each arm is constituted by an IGBT two-series connection circuit, Q _{11 to} Q ₂₂ are IGBTs, and GDU _{11 to} GDU ₂₂ are gate drive circuits of the respective elements.
This circuit is characterized in that connection lines of capacitors C _{cg11 to} C _cg22 are magnetically coupled between the collector and gate of each element. As shown in the figure, cores T _r1 and T _r2 having two windings are used as magnetic coupling means.

FIG. 2 shows an example of the core structure. It comprises primary windings a ₁ and b ₁ and secondary windings a ₂ and b ₂ . The winding direction is the same direction, and the turn ratio is 1: 1.
A simple equivalent circuit of the core is shown in FIG. For simplicity, the leakage inductance is ignored.
FIG. 4 shows an equivalent circuit for one arm in FIG. The device voltage balance during the turn-off operation will be described using this circuit. In the figure, V _i1 and V _i2 indicate input signals from the control circuit, and C _res1 and C _res2 indicate feedback capacities of the respective elements.

First, consider the operation when the conditions of the two elements are the same, that is, there is no variation in the element voltage. FIG. 5 shows a waveform diagram in that case.
Now, when the off signals V _i1 and V _i2 are input, the gate voltages V _g1 and V _g2 start to decrease as shown in FIG. When the gate threshold value is reached, as shown by the dotted line in FIG. 4, most of the gate current becomes currents I _res1 and I _res2 for charging the feedback capacitors C _res1 and C _res2 and is clamped to a constant value ( (Refer FIG.5 (c)). By this operation, the element voltages V _cg 1 and V _cg 2 start to rise as shown in FIG. 5D. In this case, since the element voltages are the same, a potential difference is generated between the primary and secondary of the core _Tr1. Does not work because there is no. Thereafter, when the sum of the collector-emitter voltages Vce of the two elements reaches Ed, the element current is cut off.

Next, consider the operation when the rate of increase in element voltage differs due to variations in external circuits. Also in this case, the operation until the gate voltage reaches the threshold voltage is the same as in FIG. Thereafter, the device voltage is increased by the currents I _res1 and I _res2 , and it is assumed that V _cg 1> V _cg 2 in the period t1 as shown in FIG. Then, a potential difference is generated between the primary and secondary of the core Tr1, and a current It shown by a thick solid line in FIG. 7 flows. This current increases the gate voltage of Q _11, occurs in a direction to decrease the gate voltage of Q _12, each element active regions, i.e. in order to be controllable region for both voltage and current, the static characteristic of the device Accordingly, the element voltage changes (the element current can be regarded as a constant current in a transient manner, so only the voltage changes). FIG. 8 schematically shows the static characteristics of the device.

As described above, the device voltage is determined by the device current and the gate voltage value Vge. If the device current is constant as shown by the dotted line in FIG. 8, when the gate voltage Vge is increased, Vce (Vcg) is decreased and Vge is decreased. Then, Vce increases. Therefore, V _cg 1 decreases and V _cg 2 increases due to the current It shown in FIG. Thus, when V _cg 1 = V _cg 2, the operation of T _r1 ends. On the other hand, when V _cg 1 <V _cg 2, the device voltage can be balanced by operating until V _cg 1 = V _cg 2 in the same manner.

  FIG. 9 shows an example in which n elements are connected in series. Even with this configuration, the operation is the same, that is, the device voltage can be balanced regardless of the number of series per arm.

Circuit diagram showing an embodiment of the present invention Configuration diagram showing an example of the core used in FIG. Equivalent circuit diagram of the core of FIG. Equivalent circuit diagram for one arm in FIG. Operation explanatory diagram of FIG. Explanation of operation when circuit conditions of each element are different Equivalent circuit diagram corresponding to FIG. Illustration of static characteristics of element Circuit diagram showing an example of multiple elements connected in series 2 series connection diagram of elements Voltage waveform diagram of each element when switching timing varies Circuit diagram showing a conventional example using a snubber circuit Explanatory drawing explaining the element voltage variation suppression principle by a snubber circuit

Explanation of symbols

Q _{11 to} Q ₂₂ ... IGBT (voltage driven semiconductor element), GDU11 to GDU22, GDU1 to GDUn ... gate drive circuit, Ed ... power supply, _Ccg11 to _Ccg22 ... capacitor.

Claims (2)

In a drive circuit for driving on / off of voltage-driven semiconductor elements connected in series for each arm of a power converter,
Between each collector and gate of each of the voltage-driven semiconductor elements, an equivalent circuit is formed of a series circuit of a capacitor and a winding, and a balance circuit in which the winding is magnetically coupled between adjacent driving circuits is connected, respectively. A voltage variation suppression method for a voltage-driven semiconductor element, characterized by suppressing variation in voltage. Adjacent ones of the voltage-driven semiconductor elements connected in series are sequentially magnetically coupled via the balance circuit, thereby making it possible to suppress variations in element voltage regardless of the number of elements connected in series. The voltage variation suppression method for a voltage-driven semiconductor element according to claim 1.

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