JP4648170B2 - Solid-state imaging module - Google Patents

Description

  The present invention relates to a solid-state imaging module, and more particularly to a solid-state imaging module for resetting a photoelectric conversion element included in a charge coupled device solid-state imaging element by an electronic shutter.

  A charge coupled device (CCD) area sensor is used as a solid-state imaging device. In the CCD area sensor, for example, a p-type well region (p-well) is formed on an n-type semiconductor substrate, and an n-type photoelectric conversion element (photodiode) or an n-type charge transfer path is formed in the p-well. It is produced by this. The photoelectric conversion element accumulates an amount of charge corresponding to the amount of incident light.

  The maximum amount of charge that can be accumulated in the photoelectric conversion element is controlled by an overflow drain (OFD) voltage applied to the substrate. The lower the OFD voltage, the larger the accumulated maximum charge amount, and the higher the OFD voltage, the smaller the accumulated maximum charge amount. The OFD voltage is set to about 10V, for example.

  By making the potential of the substrate extremely high (for example, by setting it to 30 to 40 V), it is possible to discharge all charges accumulated in the photoelectric conversion element to the substrate (electronic shutter). At the start of exposure, the photoelectric conversion element is reset by the electronic shutter. During the electronic shutter operation, a high voltage obtained by superimposing a voltage pulse on the OFD voltage (referred to as a shutter voltage) is applied to the substrate. The amplitude of the superimposed voltage pulse is set to about 20V, for example.

  FIG. 7 shows an example of a circuit of a solid-state imaging module that applies an OFD voltage and a shutter voltage to the CCD area sensor. The circuit shown in FIG. 7 includes a resistance bleeder B for generating a direct current (DC) bias, a diode D1, a capacitor C1 for alternating current (AC) coupling, and a clock driver circuit CD. A diode D1 is inserted between the resistance bleeder B and the substrate NSUB so that an anode is disposed on the resistance bleeder B side and a cathode is disposed on the substrate NSUB side.

  During the exposure, the output voltage of the clock driver CD is at a low level, and the OFD voltage determined by the resistors R1 and R2 of the resistor bleeder B is applied to the substrate NSUB.

  After the charge is read from the photoelectric conversion element, immediately before the next exposure is started, the output voltage of the clock driver CD becomes a high level. Due to capacitive coupling, the output voltage of the clock driver CD is superimposed on the OFD voltage to generate a shutter voltage.

  During the electronic shutter operation, a reverse bias voltage is applied to the diode D1, the diode D1 is turned off, and the resistance bleeder B and the substrate NSUB are electrically separated.

  The level of the OFD voltage applied to the substrate NSUB from the resistance bleeder determines the saturation output charge amount of the photoelectric conversion element. Since the relationship between the OFD voltage level and the amount of saturated output charge changes due to variations in the manufacturing process, a resistance bleeder and a fuse are built in the same chip as the area sensor in the manufacture of a CCD area sensor. In many cases, adjustment is performed so as to obtain a unique OFD voltage.

JP 2002-262186 A

  In the above-described solid-state imaging module, it is necessary to set the DC voltage in consideration of the voltage drop (Vf) of the diode D1. However, the voltage drop of the diode D1 varies from individual to individual, and also varies depending on the temperature. Due to this, it is difficult to improve the accuracy of the OFD voltage level. Increasing the accuracy of the bleeder resistance does not necessarily increase the accuracy of the output voltage.

  During the electronic shutter operation, a high voltage reaching 30-40V is used. In some cases, the solid-state imaging module may be configured using MOS transistors.

  An object of the present invention is to provide a solid-state imaging module that can be manufactured without using a diode.

  Another object of the present invention is to provide a solid-state imaging module that can be manufactured without using a MOS transistor with a particularly high breakdown voltage.

  Still another object of the present invention is to provide a solid-state imaging module having a novel configuration.

According to the first aspect of the present invention, an overflow drain voltage control circuit for a solid-state imaging device that supplies an overflow drain voltage maintained at a voltage value corresponding to an input voltage, and a voltage pulse superimposed on the overflow drain voltage The overflow drain voltage control circuit includes an operational amplifier for maintaining the overflow drain voltage at a voltage value corresponding to the input voltage, and the operational amplifier is connected to the pull-up side. 1 PMOS transistor, the drain of the first PMOS transistor supplies the overflow drain voltage, the overflow drain voltage control circuit further includes a shutter operation time control circuit, the shutter operation time control circuit, The voltage pulse to the overflow drain voltage During a normal operation that is not superimposed, a voltage for turning on the first PMOS transistor is applied to the gate of the first PMOS transistor, and during the shutter operation in which the voltage pulse is superimposed on the overflow drain voltage, the first PMOS transistor is turned on. A solid-state imaging module is provided that applies a shutter voltage in which the voltage pulse is superimposed on the overflow drain voltage to the gate of the PMOS transistor to turn off the first PMOS transistor.

  According to a second aspect of the present invention, in the solid-state imaging module according to the first aspect, there is provided the solid-state imaging module in which the bulk potential of the first PMOS transistor increases toward the shutter voltage during the shutter operation. Provided.

  According to a third aspect of the present invention, an overflow drain voltage control circuit for a solid-state imaging device that supplies an overflow drain voltage maintained at a voltage value corresponding to an input voltage, and a voltage pulse superimposed on the overflow drain voltage The overflow drain voltage control circuit includes an operational amplifier that maintains the overflow drain voltage at a voltage value corresponding to the input voltage, and the operational amplifier is connected to the pull-up side. 1, the source of the first NMOS transistor supplies the overflow drain voltage, and the voltage pulse is not superimposed on the overflow drain voltage during normal operation, the gate of the first NMOS transistor Turn on the first NMOS transistor In the shutter operation in which a voltage is applied and the voltage pulse is superimposed on the overflow drain voltage, a voltage difference between the gate voltage of the first NMOS transistor and the shutter voltage in which the voltage pulse is superimposed on the overflow drain voltage is set. When the voltage of the source of the first NMOS transistor rises due to the voltage having a value equal to or lower than the withstand voltage and the voltage pulse is superimposed on the overflow drain voltage, the source operates. There is provided a solid-state imaging module to which a voltage equal to or lower than a value at which the first NMOS transistor is turned on is applied.

  According to a fourth aspect of the present invention, in the solid-state imaging module according to the third aspect, the overflow drain voltage control circuit applies the first power supply voltage to the bulk of the first NMOS transistor during the shutter operation. A solid-state imaging module including a shutter operation control circuit is provided.

  The solid-state imaging module according to the first aspect applies a shutter voltage to the gate of the first PMOS transistor during the shutter operation to turn off the first PMOS transistor. Thereby, it is possible to suppress the current from flowing back to the operational amplifier during the shutter operation.

  During the shutter operation, the shutter voltage is applied to the drain of the first PMOS transistor that supplies the overflow drain voltage. By applying a shutter voltage to the gate of the first PMOS transistor during the shutter operation, the voltage difference between the drain and gate of the first PMOS transistor is almost eliminated, and the first PMOS transistor is caused by the voltage difference between the drain and gate. This prevents the PMOS transistor from being destroyed.

  In the solid-state imaging module according to the second aspect, the bulk potential of the first PMOS transistor increases toward the shutter voltage during the shutter operation. Thereby, during the shutter operation, the voltage difference between the gate and the bulk of the first PMOS transistor becomes small, and the destruction of the first PMOS transistor due to the voltage difference between the gate and the bulk is suppressed.

  The solid-state imaging module according to the third aspect turns off the first NMOS transistor during the shutter operation. Thereby, it is possible to suppress the current from flowing back to the operational amplifier during the shutter operation.

  During the shutter operation, the shutter voltage is applied to the source of the first NMOS transistor that supplies the overflow drain voltage, and the gate voltage that makes the voltage difference from the shutter voltage equal to or lower than the withstand voltage is applied to the gate. By applying such a gate voltage, for example, the voltage difference between the source and the gate of the first NMOS transistor becomes smaller than when the gate voltage is set to the ground potential, which is caused by the voltage difference between the source and the gate. The destruction of the first NMOS transistor is suppressed.

  The solid-state imaging module according to the fourth aspect applies the first power supply voltage to the bulk of the first NMOS transistor during the shutter operation. Accordingly, during the shutter operation, for example, the voltage difference between the source and the bulk of the first NMOS transistor becomes smaller than when the bulk is set to the ground potential, and the first NMOS transistor is caused by the voltage difference between the source and the bulk. The destruction of the NMOS transistor is suppressed.

  FIG. 1 is a block diagram illustrating a solid-state imaging device including a solid-state imaging module 101 according to an embodiment of the present invention and a solid-state imaging device (CCD area sensor) 102 driven by the solid-state imaging module 101. The solid-state imaging module 101 includes an OFD control circuit 103 and a pulse generation circuit 104.

  The OFD control circuit 103 is composed of a current output type operational amplifier. An analog output signal OFDI from the CCD area sensor 102 is input to the OFD control circuit 103, and an OFD voltage OFDO is output from the OFD control circuit 103. The potential of OFDI (this is referred to as Vofdi) is normally set to about 10-12V. The OFD control circuit 103 controls OFDO so as to have the same potential as OFDI.

  The pulse generation circuit 104 outputs a voltage pulse SUBO. A capacitor 106 is inserted between the output OFDO of the OFD control circuit 103 and the output of the pulse generation circuit 104, and the voltage pulse SUBO can be superimposed on the OFDO by capacitive coupling. The shutter voltage is generated by superimposing the voltage pulse SUBO on OFDO. A value obtained by adding the amplitude of the voltage pulse SUBO to the potential Vofdi of OFDO is defined as VHH.

  The pulse generation circuit 104 includes an inverter 105. The power supply voltage of the inverter 105 is a high power supply voltage VH and a low power supply voltage VL. The high power supply voltage VH is set to about 15V, for example, and the low power supply voltage VL is set to about -10V to -6V, for example.

  During normal operation (in a state other than during electronic shutter operation), the input A of the inverter 105 is set to the high level, and the output becomes the low power supply voltage VL. During the electronic shutter operation, the input A of the inverter 105 is set to a low level, and the output becomes the high power supply voltage VH.

  The amplitude of the voltage pulse SUBO output from the pulse generation circuit 104 during the electronic shutter operation is the difference between the high power supply voltage VH and the low power supply voltage VL. When the high power supply voltage VH is, for example, 15V and the low power supply voltage VL is, for example, −10V, the amplitude of the voltage pulse SUBO is 25V. The values of the high power supply voltage VH and the low power supply voltage VL are selected so that the amplitude of the voltage pulse SUBO is 20V or more.

  The shutter voltage VHH is set, for example, in the range of 30 to 40V. Since the shutter voltage VHH is expressed as VHH = Vofdi + (VH−VL), for example, when Vofdi is 12V and the amplitude of the voltage pulse SUBO is 25V, the shutter voltage VHH is 37V.

  Next, a specific configuration and operation of the OFD control circuit 103 will be described. First, the OFD control circuit 103A of the first embodiment will be described with reference to FIG.

  The PMOS transistors P5, P6, P10 to P12, the NMOS transistors N10, N11, N16 to N19, and the PMOS transistor P1 constitute an operational amplifier. The PMOS transistors P2 to P4 and the NMOS transistors N10 to N15 constitute a shutter operation time control circuit.

  OFDI is input to the gate of the NMOS transistor N18 corresponding to the positive input of the operational amplifier. The interconnection point between the drain of the PMOS transistor P1 and the drain of the NMOS transistor N10 provides the output OFDO. The output OFDO is input to the gate of the NMOS transistor N17 corresponding to the negative input of the operational amplifier, thereby forming a feedback loop.

  The PMOS transistors P6 and P5 are cascode-connected to the high power supply voltage VH with the source of the PMOS transistor P6 as the high power supply voltage VH side. A constant bias voltage VCP for operating in the saturation region is applied to the gate of the PMOS transistor P5. A node 20 connected to the drain of the PMOS transistor P5 is connected to the source of the PMOS transistor P1.

  The gate of the PMOS transistor P1 is connected to the drain of the NMOS transistor N12 via the node 21. An n well serving as a bulk of the PMOS transistor P1 is connected to the bulk node nw.

  The gate of the NMOS transistor N12 is connected to the high power supply voltage VH, and the source and bulk of the NMOS transistor N12 are connected to the node 24. Node 24 is connected to the drain of NMOS transistor N13. The switch signal RST is input to the gate of the NMOS transistor N13, and the source of the NMOS transistor N13 is grounded.

  The source of the PMOS transistor P2 is connected to the high power supply voltage VH. The drain and bulk of the PMOS transistor P2 are connected to the bulk node nw to which the bulk of the PMOS transistor P1 is connected. The gate of the PMOS transistor P 2 is connected to the node 22. Node 22 is connected to the drain of NMOS transistor N14.

  The gate of the NMOS transistor N14 is connected to the high power supply voltage VH, and the source and bulk of the NMOS transistor N14 are connected to the node 25. Node 25 is connected to the drain of NMOS transistor N15. The switch signal RST is input to the gate of the NMOS transistor N15, and the source of the NMOS transistor N15 is grounded.

  A PMOS transistor P3 is arranged between the output OFDO and the node 21, and a PMOS transistor P4 is arranged between the output OFDO and the node 22. The gates of the PMOS transistors P3 and P4 are connected to the high power supply voltage VH, and the bulks of the PMOS transistors P3 and P4 are connected to the bulk node nw to which the bulk of the PMOS transistor P1 is connected.

  The NMOS transistor N10 and the NMOS transistor N11 are cascode-connected to the ground potential with the source of the NMOS transistor N11 as the ground potential side. The node 23 is connected to the drain of the NMOS transistor N11, and the source and bulk of the NMOS transistor N10 are connected to the node 23. The gate of the NMOS transistor N10 is connected to the switch S2, and the switch S2 switches the voltage applied to the gate of the NMOS transistor N10 between the constant bias voltage VCN2 and the high power supply voltage VH. The bias voltage VCN2 operates the NMOS transistor N10 in the saturation region.

  NMOS transistors N17 and N18 form a differential pair, and NMOS transistor N16 supplies current to the differential pair. The gate of the NMOS transistor N16 is connected to the switch S1, and the switch S1 switches the voltage applied to the gate of the NMOS transistor N16 between the constant bias voltage VCN1 and the ground potential. The bias voltage VCN1 operates the NMOS transistor N16 in the saturation region, and the ground potential turns off the NMOS transistor N16.

  The control device 150A controls the switches S1 and S2. Control device 150A also controls switch signal RST.

  Regarding the normal operation, the description of the OFD control circuit 103A will be continued. During normal operation, the switch signal RST input to the gates of the NMOS transistors N13 and N15 is set to a high level, and the NMOS transistors N13 and N15 are turned on. As a result, the nodes 21 and 22 become the ground potential, the PMOS transistors P1 and P2 are turned on, the output OFDO and the node 20 become conductive, and the bulk node nw becomes the high power supply voltage VH.

  In the PMOS transistor P3, the source / drain is at the ground potential and the OFDO potential, and the gate is at VH, which is a higher potential than OFDO, and is turned off. Similarly, in the PMOS transistor P4, the source / drain becomes the ground potential and the OFDO potential, and the gate becomes VH having a higher potential than OFDO, and the PMOS transistor P4 is turned off.

  The switch S2 applies the bias voltage VCN2 to the gate of the NMOS transistor N10, and the switch S1 applies the bias VCN1 to the gate of the NMOS transistor N16. The NMOS transistor N16 is turned on in the saturation region and allows a constant current to flow. This current is distributed according to the gate voltage applied to each of the NMOS transistors N17 and N18.

  The PMOS transistor P6 that pulls up the output forms a current mirror with the PMOS transistor P11. A current common to the NMOS transistor N18 flows through the PMOS transistor P11. Therefore, the current flowing through the PMOS transistor P6 is proportional to the current flowing through the NMOS transistor N18.

  The NMOS transistor N11 that pulls down the output forms a current mirror with the NMOS transistor N19. A common current flows through the NMOS transistor N19 and the PMOS transistor P12. The PMOS transistor P12 forms a current mirror with the PMOS transistor P10. A current common to the NMOS transistor N17 flows through the PMOS transistor P10. Therefore, the current flowing through the NMOS transistor N11 is proportional to the current flowing through the NMOS transistor N17.

  With this configuration, if the potential of the output OFDO fed back to the NMOS transistor N17 is lower than the potential of OFDI input to the NMOS transistor N18, more current flows through the NMOS transistor N18 than the NMOS transistor N17. A large amount of current flows through the pull-up side and a small amount of current flows through the pull-down side, and the potential of OFDO is raised.

  When the magnitude relationship between OFDO and OFDI is reversed, the operation is reversed and the potential of OFDO is lowered. By such push-pull operation, the output OFDO is maintained at the same potential as the input OFDI.

  The potential of the node 20 connected to the source of the PMOS transistor P1 is close to the potential Vofdi of the output OFDO but is higher than that. The potential of the node 23 connected to the source of the NMOS transistor N10 is lower than the gate bias voltage VCN2 of the NMOS transistor N10 by about the transistor threshold Vth and the saturation voltage.

  Next, regarding the electronic shutter operation, the description of the OFD control circuit 103A will be continued. During the electronic shutter operation, the input switch signal RST is set to a low level, the switch S1 is set to the ground potential side, and the switch S2 is set to the high power supply voltage VH side.

  By setting the switch S1 to the ground potential side, the NMOS transistor N16 is turned off and no current flows, so the PMOS transistor P6 and the NMOS transistor N11 are turned off, and the respective gate voltages are approximately the high power supply voltage VH and approximately ground potential. It becomes.

  By setting the input switch signal RST to a low level, the NMOS transistors N13 and N15 are turned off. When the shutter voltage substantially exceeds the high power supply voltage VH with the rise of the voltage pulse SUBO (more precisely, when the high power supply voltage VH exceeds the threshold of the PMOS transistor), the PMOS transistors P3 and P4 are turned on, and the potentials of the nodes 21 and 22 Becomes equal to the shutter voltage. As a result, the PMOS transistors P1 and P2 are turned off.

  While the bulk node nw is cut off from the high power supply voltage VH, a forward voltage is applied between the drain connected to the OFDO and the bulk in the PMOS transistors P1, P3, and P4, so that it is almost equal to the shutter voltage. Rise to potential. The node 20 is in a high impedance state while maintaining a potential substantially equal to the high power supply voltage VH.

  In this way, even when a high shutter voltage is applied to the drain of the PMOS transistor P1, it is possible to prevent a forward current from flowing from the drain of the PMOS transistor P1 (current flows backward). The shutter voltage can be increased to a desired high voltage VHH.

  Note that when a shutter voltage is applied to the drain of the PMOS transistor P1, the source side (node 20 side) has a lower potential than the drain side, and the drain and source are reversed from the viewpoint of transistor operation. In this specification, the side that outputs OFDO is called the drain of the PMOS transistor P1.

  Since the output OFDO of the operational amplifier is directly connected to the external coupling capacitor 106, it is not necessary to separately provide a capacitor for phase compensation.

  Since no current flows through the NMOS transistors N10, N12, and N14 to which the shutter voltage VHH is applied to the drain and the gate voltages are all the high power supply voltage VH, the potentials of the nodes 23, 24, and 25 are lower than the VH by the threshold Vth. Value.

  In addition, since no current flows in the differential pair composed of the NMOS transistor N17 to which the output OFDO is input, the PMOS transistor P10 has the gate and drain potentials connected to each other substantially equal to the high power supply voltage VH. Turn off. Similarly, the PMOS transistor P11 is also turned off because the potentials of the gate and drain connected to each other are substantially equal to the high power supply voltage VH. The NMOS transistor N17 is turned on with a low resistance when a shutter voltage is applied to its gate, and the source-side node 26 has a potential substantially equal to the high power supply voltage VH, similarly to the drain side.

  Transistors to which a shutter voltage is applied in accordance with the electronic shutter operation are PMOS transistors P1 to P4 and NMOS transistors N10, N12, N14, and N17.

  In the PMOS transistors P1 and P2, a voltage difference of about VHH−VH occurs between the source and gate, between the source and drain, and between the source and bulk. In the PMOS transistors P3 and P4, a voltage difference of about VHH-VH occurs between the gate and source, between the gate and drain, and between the gate and bulk.

  In the NMOS transistors N10, N12, and N14, a voltage difference of about VHH− (VH−Vth) is generated between the drain and the source and between the drain and the bulk. Further, a voltage difference of about VHH-VH is generated between the gate and source of the NMOS transistor N17 and between the gate and drain.

  That is, the maximum voltage difference generated between the terminals is about VHH−VH in the PMOS transistors P1 to P4 and the NMOS transistor N17. The NMOS transistors N10, N12, and N14 have a maximum voltage difference between the terminals of about VHH− (VH−Vth).

  By switching the gate voltage of the NMOS transistor N10 to VH higher than VCN2 during normal operation, the voltage difference between the drain and gate (and between the drain and source and between the drain and bulk) of the NMOS transistor N10 is reduced. The

  For example, when the potential Vofdi of OFDO is 12V, the high potential power supply VH is 15V, VHH is 37V, and the threshold value Vth is 1V, it is applied between the terminals of the PMOS transistors P1 to P4 and the NMOS transistor N17. The maximum voltage difference is 22V (VHH37V-VH15V), and the maximum voltage difference applied between the terminals of the NMOS transistors N10, N12, and N14 is 23V (VHH37V- (VH15V-Vth1V)). If the breakdown voltage of each transistor is, for example, 30 V or more, the transistor is not destroyed due to the application of the shutter voltage.

  During the electronic shutter operation, a shutter voltage is applied to the drain and gate of the PMOS transistor P1, and the bulk potential of the PMOS transistor P1 rises to almost the shutter voltage. Therefore, the voltage difference between these terminals is very small.

  Next, with reference to FIG. 3, the voltage difference generated between the terminals will be described by taking as an example the case where the PMOS transistor P1 and the NMOS transistor N10 that supply the output OFDO are formed on a p-type substrate.

Two n-type wells 2A and 3A are formed apart from each other on the p-type substrate 1A. On the surface of the n-well 2A, a p ⁺ type region 4A serving as a source of the PMOS transistor P1 and a p ⁺ type region 5A serving as a drain of the PMOS transistor P1 are formed. A gate electrode 6A of the PMOS transistor P1 is formed on the n well 2A via an insulating film.

A p-type well 7A is formed in the n-well 3A, and an n ⁺ -type region 8A serving as a source of the NMOS transistor N10 and an n ⁺ -type region 9A serving as a drain of the NMOS transistor N10 are formed on the surface of the p-well 7A. ing. A gate electrode 10A of the NMOS transistor N10 is formed on the p-well 7A via an insulating film.

N well 2A is connected to bulk node nw via n ⁺ type region 11A, p ⁺ type region 4A is connected to node 20, and gate electrode 6A is connected to node 21. P well 7A is connected to node 23 through p ⁺ type region 12A, n ⁺ type region 8A is connected to node 23, and gate electrode 10A is connected to switch S2. The p ⁺ type region 5A and the n ⁺ type region 9A supply the output OFDO. N well 3A is connected to high power supply voltage VH via n ⁺ type region 13A, and p type substrate 1A is connected to the ground potential.

During the electronic shutter operation, the shutter voltage VHH is applied to the n well 2A, the gate electrode 6A, the p ⁺ type region 5A, and the n ⁺ type region 9A, and the high power supply voltage VH is applied to the p ⁺ type region 4A and the gate electrode 10A. A difference VH−Vth between the high power supply voltage and the threshold is applied to the n ⁺ -type region 8A and the p-well 7A.

  When VHH is 37 V, VH is 15 V, and Vth is 1 V, the voltage difference between the source and gate of the PMOS transistor P1, between the source and drain, and between the source and bulk during the electronic shutter operation is VHH−VH. = 22V.

  Further, the voltage difference between the drain and source of the NMOS transistor N10 and between the drain and bulk is VHH− (VH−Vth) = 23V. The voltage difference between the drain and the gate of the NMOS transistor N10 is VHH−VH = 22V, which is smaller than the voltage difference between the drain and the source and between the drain and the bulk. Both the PMOS transistor P1 and the NMOS transistor N10 can have a withstand voltage of 30 V or less.

  However, in such a configuration, a voltage of maximum VHH (= 37 V) is applied between the n-well 2A and the p-type substrate 1A during the electronic shutter operation. The withstand voltage of VHH must be higher than VHH.

  Next, the OFD control circuit 103B according to the second embodiment will be described with reference to FIG. In the solid-state imaging module 101 shown in FIG. 1, the OFD control circuit 103B of the second embodiment can be used instead of the OFD control circuit 103A of the first embodiment.

  The OFD control circuit 103B of the second embodiment has a configuration in which the PMOS transistors P1 to P4 and the NMOS transistors N10 to N15 are removed from the OFD control circuit 103A of the first embodiment, and NMOS transistors N1 to N4 are added.

  The PMOS transistors P5, P6, P10 to P12, the NMOS transistors N10, N11, N16 to N19, and the NMOS transistors N1 and N4 constitute an operational amplifier. The NMOS transistors N2 and N3 constitute a shutter operation control circuit. Note that the control device 150B controls the switch S1.

  An NMOS transistor N1 is provided at the pull-up side node of the output OFDO, and the potential of the bulk node pw connected to the p-well serving as the bulk of this transistor is switched between the normal operation and the electronic shutter operation. The pull-down side node is provided with an NMOS transistor N4 whose gate is connected to the high power supply voltage VH between the NMOS transistor N10 constituting the cascode and the output OFDO, and the bias voltage applied to the gate of the NMOS transistor N10 is There is no need to switch between normal operation and electronic shutter operation.

  This will be described in detail below. The drain of the NMOS transistor N1 is connected to the node 20 on the pull-up side that is connected to the drain of the PMOS transistor P5. A constant bias voltage VHA is input to the gate of the NMOS transistor N1, the source of the NMOS transistor N1 supplies the output OFDO, and the source follower is configured.

  The sources and bulks of the NMOS transistors N2 and N3 are connected to the bulk node pw of the NMOS transistor N1 to which the bulk made of the p well is connected. The drain of the NMOS transistor N2 is connected to the output OFDO, and a constant bias voltage VHA is applied to the gate of the NMOS transistor N2. The drain of the NMOS transistor N3 is connected to the high power supply voltage VH, and the output OFDO is applied to the gate of the NMOS transistor N3.

  The maximum voltage of the output OFDO supplied from the source of the NMOS transistor N1 is limited by the bias voltage VHA, and is a value that is lowered from the bias voltage VHA by the threshold Vth. In order to increase the maximum voltage of the output OFDO as much as possible, the bias voltage VHA is set to about the high power supply voltage VH or higher. Note that the maximum voltage of OFDO when VHA is equal to or higher than VH + Vth is limited by the high power supply voltage VH.

  Further, in order to prevent both NMOS transistors N2 and N3 from being turned on when the output OFDO is higher than the high power supply voltage VH, the bias voltage VHA needs to be set to VH + Vth or less.

  The drain of the NMOS transistor N10 that is cascode-connected to the ground potential together with the NMOS transistor N11 is connected to the node 30. The node 30 is connected to the source and bulk of the NMOS transistor N4. The gate of the NMOS transistor N4 is connected to the high power supply voltage VH, and the drain of the NMOS transistor N4 supplies the output OFDO.

  Regarding the normal operation, the description of the OFD control circuit 103B will be continued. During normal operation, the bias voltage VCN1 is applied to the gate of the NMOS transistor N16 by the switch S1. As long as the potential of the output OFDO does not reach the maximum output voltage of the NMOS transistor N1, the NMOS transistor N1 is turned on. At this time, a predetermined current flows through the PMOS transistor P6 and the NMOS transistor N11 as described for the OFD control circuit 103A of the first embodiment, and the output OFDO has the same potential as the input OFDI.

  Further, the NMOS transistor N2 is also turned on, the bulk node pw becomes equipotential with the output OFDO, and the NMOS transistor N1 does not have a substrate bias effect that is a change in threshold value due to a change in the output OFDO.

  The potential of the node 20 connected to the drain of the NMOS transistor N1 is close to the potential Vofdi of the output OFDO but is higher than that. Since the NMOS transistor N4 is turned on by applying the high power supply voltage VH to the gate, the potential of the node 30 is close to the potential Vofdi of the output OFDO but is lower than that.

  Regarding the electronic shutter operation, the description of the OFD control circuit 103B will be continued. During the electronic shutter operation, the switch S1 is set to the ground potential side. As a result, the NMOS transistor N16 is turned off and no current flows. The PMOS transistor P6 and the NMOS transistor N11 are also turned off, and the respective gate voltages are substantially the high power supply voltage VH and the ground potential.

  When the shutter voltage exceeds the maximum output voltage VHA-Vth of the NMOS transistor N1 with the rise of the voltage pulse SUBO, the NMOS transistors N1 and N2 are turned off, and the node 20 and the bulk node pw are disconnected from the output OFDO. When the shutter voltage exceeds VH + Vth, the NMOS transistor N3 is turned on, and the bulk node pw becomes equipotential with the high power supply voltage VH. Since a forward voltage is applied to the PN junction between the bulk node pw and the drain of the NMOS transistor N1, a voltage substantially equal to the high power supply voltage VH is applied to the node 20.

  In this way, the shutter voltage can be raised to a desired high voltage VHH without causing a current to flow backward.

  Note that when a shutter voltage is applied to the source of the NMOS transistor N1, the drain side (node 20 side) has a lower potential than the source side, and the source and drain are reversed from the viewpoint of transistor operation. In this specification, the side that outputs OFDO is called the source of the NMOS transistor N1.

  If the gate voltage VHA of the NMOS transistor N1 is too high, when the source voltage of the NMOS transistor N1 rises with the application of the shutter voltage, the source turns to the drain in operation and the NMOS transistor N1 is turned on. The gate voltage VHA needs to be equal to or lower than a value at which the NMOS transistor N1 is turned on during the electronic shutter operation.

  In the NMOS transistor N4 to which the shutter voltage VHH is applied to the drain, no current flows because the NMOS transistor N11 is turned off, and the potential of the node 30 is lower than the high power supply voltage VH by the threshold Vth.

  Further, in the NMOS transistor N17 to which the output OFDO is input, the potential on the source side node 26 and the drain is substantially equal to the high power supply voltage VH, as described for the OFD control circuit 103A of the first embodiment. Become.

  Even during the electronic shutter operation, a voltage exceeding the high power supply voltage VH is not applied to the node 30, so that the gate of the NMOS transistor N10 is always set to the constant bias voltage VCN2, and the bulk is set to the ground potential. can do.

  In this embodiment, transistors in which a high voltage difference occurs between the terminals are NMOS transistors N1 to N4 and N17. In the NMOS transistor N1, a voltage difference of about VHH−VH occurs between the source and drain and between the source and bulk. In the NMOS transistor N2, a voltage difference of about VHH−VH is generated between the drain and the source and between the drain and the bulk. In the NMOS transistor N3, a voltage difference of about VHH-VH occurs between the gate and source, between the gate and drain, and between the gate and bulk. In the NMOS transistor N4, a voltage difference of about VHH− (VH−Vth) is generated between the drain and source and between the drain and bulk. Further, a voltage difference of about VHH-VH is generated between the gate and source of the NMOS transistor N17 and between the gate and drain.

  That is, the NMOS transistors N1 to N3 and N17 have a maximum voltage difference between the terminals of about VHH−VH. In addition, the NMOS transistor N4 has a maximum voltage difference between the terminals of about VHH− (VH−Vth). For example, when VHH is 37V, VH is 15V, and Vth is 1V, VHH-VH is 22V and VHH- (VH-Vth) is 23V. If the breakdown voltage of each transistor is, for example, 30 V or more, the transistor is not destroyed due to the application of the shutter voltage.

Next, with reference to FIG. 5, the voltage difference generated between the terminals will be described by taking as an example the case where the NMOS transistors N1 and N4 that supply the output OFDO are configured on an n-type substrate. Two p-type wells 2B and 3B are formed apart from each other on the n-type substrate 1B. On the surface of the p-well 2B, an n ⁺ -type region 4B that becomes the source of the NMOS transistor N1 and an n ⁺ -type region 5B that becomes the drain of the NMOS transistor N1 are formed. A gate electrode 6B of the NMOS transistor N1 is formed on the p well 2B via an insulating film.

In the p-well 3B, an n ⁺ type region 7B serving as a source of the NMOS transistor N4 and an n ⁺ type region 8B serving as a drain of the NMOS transistor N4 are formed. A gate electrode 9B of the NMOS transistor N4 is formed on the p-well 3B via an insulating film.

P well 2B is connected to bulk node pw via p ⁺ type region 10B, n ⁺ type region 5B is connected to node 20, and gate electrode 6B is connected to bias voltage VHA. P well 3B is connected to node 30 through p ⁺ type region 11B, n ⁺ type region 7B is connected to node 30, and gate electrode 9B is connected to high power supply voltage VH. The n ⁺ type region 4B and the n ⁺ type region 8B supply the output OFDO. N-type substrate 1B is connected to high power supply voltage VH via n ⁺ -type region 12B.

During the electronic shutter operation, the shutter voltage VHH is applied to the n ⁺ type region 4B and the n ⁺ type region 8B, the bias voltage VHA is applied to the gate electrode 6B, and the high voltage is applied to the p well 2B, the n ⁺ type region 4B, and the gate electrode 9B. The power supply voltage VH is applied, and the difference VH−Vth between the high power supply voltage and the threshold is applied to the n ⁺ type region 7B and the p well 3B.

  When VHH is 37V, VH is 15V, Vth is 1V, and VHA is 15V, during the electronic shutter operation, between the source and the drain of the NMOS transistor N1, between the source and the bulk, and between the source and the gate The voltage difference is VHH−VH = VHH−VHA = 22V.

  Further, the voltage difference between the drain and source of the NMOS transistor N4 and between the drain and bulk becomes VHH− (VH−Vth) = 23V. The voltage difference between the drain and gate of the NMOS transistor N4 is VHH−VH = 22V, which is smaller than the voltage difference between the drain and source and between the drain and bulk. Both the NMOS transistor N1 and the NMOS transistor N4 can have a withstand voltage of 30 V or less.

  Since the potentials of the p wells 2B and 3B are at most about the high power supply voltage VH, the voltage difference between the p well and the n-type substrate 1B during the electronic shutter operation can be set to 30 V or less, for example. . Therefore, the breakdown voltage between the p-well and the n-type substrate 1B can be set to 30 V or less, for example.

  As a modification of the OFD control circuit of the second embodiment, the value of the bias voltage VHA can be switched between the normal operation and the electronic shutter operation. FIG. 6 shows a switch S3 for switching the bias voltage VHA.

  During normal operation, the bias voltage VHA is set to VH0. VH0 may be a value that is higher than the sum VH + Vth of the high power supply voltage and the threshold and does not exceed the breakdown voltage of the transistor. For example, when VH is 15V and Vth is 1V, VH0 can be about 18V. By applying the bias voltage VH0, the maximum output voltage is not limited by the NMOS transistor N1, and the output OFDO can be increased to the high power supply voltage VH. Also, the NMOS transistor N2 is always on as long as this output voltage is within the range, and the bulk node pw is kept at the same potential as the output OFDO.

  During the electronic shutter operation, the bias voltage VHA is set to the high power supply voltage VH. When the potential of OFDO exceeds VH−Vth, the NMOS transistors N1 and N2 are turned off. In the second embodiment in which VHA is constant, it is necessary to accurately adjust the bias voltage VHA to a value from VH to VH + Vth, but in this modification, such fine adjustment of VHA is not necessary. By switching the value of VHA between the normal operation and the electronic shutter operation, a through current caused by turning on both of the NMOS transistors N2 and N3 can be easily prevented.

  Note that the bias voltage VHA applied to the gate of the NMOS transistor N1 during the electronic shutter operation can be made lower than the high power supply voltage VH. The bias voltage VHA may be applied so that the voltage difference between the source and gate of the NMOS transistor N1 to which the shutter voltage is applied does not exceed the breakdown voltage.

  As described above, the solid-state imaging module according to the embodiment does not need to use a diode in order to suppress a current from flowing backward to the OFD control circuit due to the shutter voltage.

  If the MOS transistor to which the shutter voltage VHH is applied during the electronic shutter operation has a terminal connected to the ground potential, the breakdown voltage of the MOS transistor needs to be VHH or higher (for example, the breakdown voltage is 40 V or higher). In the solid-state imaging module according to the embodiment, during the electronic shutter operation, a voltage equal to or higher than the high power supply voltage VH−the threshold value Vth is applied to each terminal of the MOS transistor to which the shutter voltage VHH is applied. Thereby, it becomes easy to manufacture a solid-state imaging module using a MOS transistor with a particularly high breakdown voltage (for example, a breakdown voltage of about 30 V).

  Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

It is a block diagram which shows the structure of the solid-state image sensor by the Example of this invention, and the solid-state image sensor driven by the solid-state image sensor of an Example. 1 is a circuit diagram schematically showing an OFD control circuit according to a first embodiment. FIG. 3 is a schematic cross-sectional view of a PMOS transistor P1 and an NMOS transistor N10 included in the OFD control circuit according to the first embodiment. FIG. It is a circuit diagram which shows schematically the OFD control circuit by a 2nd Example. It is a schematic sectional drawing of NMOS transistor N1 and N4 which the OFD control circuit by a 2nd Example has. The switch which switches VHA with the OFD control circuit by the modification of a 2nd Example is shown. It is a circuit diagram which shows the conventional solid-state imaging module schematically.

Explanation of symbols

101 Solid-state imaging module 102 CCD area sensor 103 OFD control circuit 104 Pulse generation circuit 105 Inverter 106 Capacitance OFDO Overflow drain voltage SUBO Voltage pulse

Claims (10)

An overflow drain voltage control circuit for a solid-state imaging device that supplies an overflow drain voltage maintained at a voltage value corresponding to an input voltage;
A pulse generation circuit for generating a voltage pulse superimposed on the overflow drain voltage,
The overflow drain voltage control circuit includes an operational amplifier that maintains the overflow drain voltage at a voltage value corresponding to the input voltage, the operational amplifier including a first PMOS transistor on a pull-up side, The drain of the PMOS transistor supplies the overflow drain voltage,
The overflow drain voltage control circuit further includes a shutter operation control circuit, and the shutter operation control circuit is connected to the gate of the first PMOS transistor during a normal operation in which the voltage pulse is not superimposed on the overflow drain voltage. A voltage for turning on the first PMOS transistor is applied, and the voltage pulse is applied to the gate of the first PMOS transistor and to the overflow drain voltage during a shutter operation in which the voltage pulse is superimposed on the overflow drain voltage. A solid-state imaging module that applies a shutter voltage on which is superimposed to turn off the first PMOS transistor.   The shutter operation control circuit includes a second PMOS transistor, one of the source / drain of the second PMOS transistor is connected to the gate of the first PMOS transistor, and the source of the second PMOS transistor 2. The solid-state imaging module according to claim 1, wherein the other of the drains is connected to the drain of the first PMOS transistor, and the second PMOS transistor is turned on during the shutter operation.   3. The solid-state imaging module according to claim 1, wherein a bulk potential of the first PMOS transistor rises toward the shutter voltage during the shutter operation. The operational amplifier includes a differential pair and a current source MOS transistor serving as a current source for supplying current to the differential pair,
The current source control device according to claim 1, further comprising a current source control device that turns on the current source MOS transistor during the normal operation and turns off the current source MOS transistor during the shutter operation. Solid-state imaging module. The operational amplifier includes a first NMOS transistor on the pull-down side, and
5. The solid-state imaging module according to claim 1, further comprising a control device that applies a voltage higher than that during the normal operation to the gate of the first NMOS transistor during the shutter operation. 6. An overflow drain voltage control circuit for a solid-state imaging device that supplies an overflow drain voltage maintained at a voltage value corresponding to an input voltage;
A pulse generation circuit for generating a voltage pulse superimposed on the overflow drain voltage,
The overflow drain voltage control circuit includes an operational amplifier that maintains the overflow drain voltage at a voltage value corresponding to the input voltage, the operational amplifier including a first NMOS transistor on a pull-up side, The source of the NMOS transistor supplies the overflow drain voltage,
During normal operation in which the voltage pulse is not superimposed on the overflow drain voltage, a voltage for turning on the first NMOS transistor is applied to the gate of the first NMOS transistor,
During a shutter operation in which the voltage pulse is superimposed on the overflow drain voltage, the voltage difference between the gate voltage of the first NMOS transistor and the shutter voltage on which the voltage pulse is superimposed on the overflow drain voltage is set to be equal to or lower than a withstand voltage. When the voltage of the source of the first NMOS transistor rises as the voltage pulse is superimposed on the overflow drain voltage, the source is operatively turned to the drain and A solid-state imaging module to which a voltage equal to or lower than a value for turning on the first NMOS transistor is applied.   The input voltage is equal to or higher than a ground potential and equal to or lower than a first power supply voltage, and a voltage higher than the first power supply voltage is applied to a gate of the first NMOS transistor during the normal operation. Solid-state imaging module.   The solid-state imaging module according to claim 6 or 7, wherein a voltage equal to or higher than the first power supply voltage is applied to a gate of the first NMOS transistor during the shutter operation.   9. The shutter operation control circuit according to claim 6, wherein the overflow drain voltage control circuit includes a shutter operation time control circuit that applies the first power supply voltage to a bulk of the first NMOS transistor during the shutter operation. 10. Solid-state imaging module. The operational amplifier includes a differential pair and a current source MOS transistor serving as a current source for supplying current to the differential pair,
10. The current source control device according to claim 6, further comprising a current source control device that turns on the current source MOS transistor during the normal operation and turns off the current source MOS transistor during the shutter operation. Solid-state imaging module.

Images