JP4666907B2 - Method for manufacturing semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing an insulated gate field effect transistor, and more particularly to a method for manufacturing a semiconductor device that can be applied to a thin film transistor (TFT) having a gate overlap structure.

  As a display device using liquid crystal, a product having a large screen exceeding 20 inches has been put into practical use, as represented by a liquid crystal television receiver. In recent years, a drive circuit integrated liquid crystal display device has been realized with TFTs using a polycrystalline silicon film as an active layer.

  However, it has been pointed out that TFTs using a polycrystalline silicon film have a low drain junction breakdown voltage and a large junction leakage current (hereinafter referred to as off-leakage current). As a countermeasure, it is known that it is effective to form a lightly doped drain (LDD) structure.

  Also, a problem has been pointed out that a high electric field is generated in the vicinity of the drain region, and the generated hot carriers are trapped in the gate insulating film on the LDD region, and the device characteristics such as the threshold voltage fluctuate and decrease. Yes. As means for preventing deterioration due to hot carriers, a TFT having a structure in which an LDD region overlaps a gate electrode is disclosed (see Patent Document 1). A gate overlap LDD structure TFT has a higher current driving capability than a normal LDD structure TFT, and effectively relieves a high electric field in the vicinity of the drain region to suppress deterioration due to hot carriers.

JP 2000-294787 A

  However, the gate overlap LDD structure TFT disclosed in the above publication has overlapped with the gate electrode as the design rule is reduced by overlapping the gate electrode after forming the impurity region for forming the LDD in the semiconductor layer. The amount cannot be made accurately.

  As a suitable example of fabricating a gate overlap LDD structure TFT in a self-aligning manner, at least two conductive layers are laminated by one photoexposure treatment and a plurality of etching processes to form upper and lower conductive layers. A technique is disclosed that makes it possible to form an LDD region that overlaps with a gate electrode in a self-aligned manner by making the dimensions different and ion-doping using the dimensional difference and the film thickness difference (for example, (See Patent Document 2).

JP 2002-14337 A

  Of course, in order to maximize the function of the LDD that overlaps the gate electrode as a countermeasure against hot carrier degradation, it is necessary to optimize the length of the LDD (the length with respect to the channel length) according to the driving voltage of the TFT. There is. That is, there is an optimum length for effectively relaxing the high electric field in the vicinity of the drain region.

  The technique disclosed in the above publication includes a first step of etching a two-layered conductive layer into a tapered shape, and a second step of selectively anisotropically etching only the upper layer of the tapered conductive layer. And the length of the LDD can be adjusted by controlling the taper angle.

  In order to drive a TFT having a channel length of about 10 μm at 10 to 20 V, an LDD length of 1 μm or more (preferably 1.5 μm or more) (the length of a portion overlapping with the gate electrode) is required.

  In the conventional technique using a gate electrode having a laminated structure of at least two layers, it is necessary to reduce the taper angle (angle formed with the substrate surface) at the end of the gate electrode processing stage in order to control the length of the LDD. . For this purpose, it is necessary to increase the retraction amount of the mask pattern.

  However, when forming a gate electrode in which the first conductive layer of the two-layer stacked structure is tantalum nitride and the second conductive layer is titanium or a metal containing titanium as a main component, the LDD region is formed by taper etching. It is difficult to obtain a tapered shape necessary for securing a length of 1 μm or more, preferably 1.5 μm, that is, the taper angle at the end of the conductive film is increased. Even if anisotropic etching is performed thereafter, an etching residue (bottoming) occurs at the end portion of the second conductive layer, and the portion acting as the LDD region is shortened. Even in the case of a three-layer laminated structure, the same etching problems as those described above occur and cause similar problems.

  Not only the gate electrode but also the edge or side wall of the film can be etched into a tapered shape based on the mask pattern by etching the workpiece while simultaneously retreating the width of the mask pattern by dry etching. It becomes. For this purpose, the selection of the gas species to be etched, the control of the bias voltage, and the selection ratio between the mask pattern material and the coating film are important.

  In the present invention, after the gate conductive layer having a laminated structure of two to three layers is subjected to taper etching processing, an etching residue is generated at the end of the second conductive film by anisotropic etching processing. Therefore, the length of the LDD region is ensured by reducing or removing the etching residue at the end of the second conductive film.

  Since a sufficient taper cannot be obtained during the taper etching process, it is necessary to remove the etching residue (bottoming) at the end of the second conductive layer in order to lengthen the LDD region as much as possible. In the present invention, an argon plasma treatment is added between a taper etching process and an anisotropic etching process for a conductive layer laminated in two to three layers. It serves to reduce or eliminate the etching residue (bottoming) generated in the film.

  The length of the LDD that overlaps with the gate electrode necessary for suppressing deterioration against hot carriers (hereinafter, this length will be referred to as Lov for convenience) will be considered as follows.

  First, when Lov is a predetermined value with respect to the deterioration of the TFT, the time during which the maximum value of the field effect mobility decreases by 10% is defined as the lifetime, and the reciprocal of the drain voltage is expressed as shown in FIG. From a linear relationship obtained by plotting on a semilogarithmic graph, a voltage with a lifetime of 10 years is derived as a 10-year guaranteed voltage. For example, in FIG. 10, the 10-year guaranteed voltage in a TFT with Lov of 1.0 μm is 16V. Note that the high-voltage power supply voltage in the liquid crystal panel is often 16 V, and it is required that a guaranteed voltage of 19.2 V or more be obtained with a 20% margin. FIG. 9 is a graph in which the estimated guaranteed voltage obtained in this way is plotted with values when Lov is 0.5 μm, 0.78 μm, 1.0 μm, 1.5 μm, and 1.7 μm. In FIG. 9, in the bias stress test, the drain voltage value that takes 20 hours until the on-current value of the TFT fluctuates by 10% is shown as a 20-hour guaranteed voltage.

  Deterioration due to the hot carrier effect is hardly a problem when the driving voltage is low, but cannot be ignored when driving at 10 V or more. As is apparent from FIG. 9, when the drive voltage is 16V, Lov needs to be 1 μm or more, preferably 1.5 μm or more.

  In order to satisfy the above requirements, the present invention provides a method for manufacturing a semiconductor device that forms an LDD that overlaps with a gate electrode in a self-aligning manner, wherein the gate electrode is formed of a stacked body including a plurality of conductive layers, The width of the first conductive layer and the second conductive layer in the channel length direction is longer in the first conductive layer, which is the lower layer, and is used as a mask during ion doping for forming the gate electrode LDD. To do. At this time, in order to make the LDD overlapping with the gate electrode preferably 1.5 μm or more, the mask pattern shape for forming the gate electrode is processed and combined with dry etching to obtain an optimum shape. .

  According to the present invention, a mask pattern is formed on a laminate of metal nitride and titanium or a metal containing titanium as a main component, and a first conductive layer pattern having a tapered sidewall is formed. And a step of performing a first etching process and a second etching process for anisotropically etching the first conductive layer pattern, and an inert gas between the first etching process and the second etching process. The plasma processing is performed.

  According to the present invention, a stacked structure including a first conductive layer on the lower layer side and a second conductive layer on the upper layer side is formed on a semiconductor layer via a gate insulating film, and a mask pattern is formed on the stacked structure. After the second conductive layer and the first conductive layer are taper etched, argon plasma is irradiated to selectively etch the second conductive layer in the first conductive layer pattern based on the mask pattern. By forming two conductive layer patterns, the first conductive layer and the second conductive layer have different widths in the channel direction, and the first conductive layer has a longer second conductive layer pattern. The protruding length of the first conductive layer can be 1 μm or more, and by using this as a shielding mask for ions accelerated by an electric field, a low-concentration drain region overlapping the first conductive layer pattern can be formed. It becomes possible. That is, the low concentration drain region can be formed in a self-aligned manner. Of course, the second conductive layer pattern can be used as a gate electrode.

  In the above invention, a suitable combination of the first conductive layer and the second conductive layer is that the first conductive layer is tantalum nitride and the second conductive layer is titanium or a metal containing titanium as a main component.

  In the present invention, a first conductive layer, a second conductive layer, and a third conductive layer are sequentially stacked on a semiconductor layer via a gate insulating film to form a stacked structure, and a mask pattern is formed thereon. A first conductive layer pattern having a tapered portion at each end is formed, and after the taper etching process, argon plasma is irradiated, and the third conductive layer and the second conductive layer in the first conductive layer pattern are irradiated based on the mask pattern. By selectively etching the conductive layer to form the second conductive layer pattern, the first conductive layer and the second conductive layer have different widths in the channel length direction, and the first conductive layer has a longer second length. A conductive layer pattern is formed. The protruding length of the first conductive layer can be 1 μm or more, and by using this as a shielding mask for ions accelerated by an electric field, a low-concentration drain region overlapping the first conductive layer pattern can be formed. It becomes possible. That is, the low concentration drain region can be formed in a self-aligned manner. Of course, the second conductive layer pattern can be used as a gate electrode.

  In the above invention, a suitable combination of the first conductive layer, the second conductive layer and the third conductive layer is that the first conductive layer is tantalum nitride and the second conductive layer is titanium or an alloy containing titanium as a main component or And the third conductive layer is titanium nitride.

  As described above, according to the present invention, the gate electrode is formed of a laminate composed of a plurality of conductive layers, and the shape of the gate electrode is determined by the width of the first conductive layer and the second conductive layer in the channel direction. In the processing process with a longer shape, after the taper etching process, by providing an argon plasma treatment for the purpose of removing or reducing reaction products, an etching stop occurs during the anisotropic etching process. Thus, an abnormal etching residue (bottoming) at the end of the second conductive layer is avoided. As a result of the absence of etching residue (bottoming) at the end of the second conductive layer, the length of the first conductive layer in the channel length direction can be 1 μm or more. By using this gate electrode as a mask at the time of ion doping, the length of the LDD region overlapping with the gate electrode can be set to 1 μm or more, and the lifetime for hot carrier deterioration can be extended.

  In addition, according to the present invention, a gate electrode is used as a mask during ion doping, an LDD overlapping with the gate electrode is formed in a self-aligned manner, and a TFT having a length (Lov) of 1 μm or more is formed. Can do. The length of the LDD region overlapping with the gate electrode can be set to 1 μm or more, and the lifetime for hot carrier deterioration can be extended.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the embodiments described below, and various modifications are allowed without departing from the scope of the present invention.
(Embodiment 1)

  In the present embodiment, a process for forming an LDD overlapping with the gate electrode in a self-aligned manner using the gate electrode as a mask at the time of ion doping and setting its length (Lov) to 1 μm or more will be described. Specifically, after forming the first conductive layer pattern, argon plasma treatment is performed on the tapered side wall portion conductive layer of the stacked structure having a tapered shape, and the second conductive layer pattern in the first conductive layer pattern is formed based on the mask pattern. An embodiment in which the second conductive layer pattern is formed by selectively etching the conductive layer pattern will be described.

  In FIG. 1A, a first insulating film (underlying film) 101, a semiconductor layer 102, and a second insulating film (gate insulating film) 103 are formed over a glass substrate 100, and a first conductive layer 104 and a second insulating film are formed thereover. A conductive layer 105 and a third conductive layer 106 are formed. The mask pattern 107 is formed using a photoresist by a light exposure process.

  The first conductive layer is formed of a refractory metal such as tantalum nitride (TaN) with a thickness of 30 to 50 nm, and the second conductive layer is titanium or an alloy or compound containing titanium as a main component with a thickness of 300 to 600 nm. To form.

  The third conductive layer uses a refractory metal such as titanium nitride (TiN). However, the third conductive layer is provided in order to lower the contact resistance, and is not an essential constituent element in the configuration of the present invention. Since titanium nitride can be processed with the same etching gas as titanium, processing is facilitated by combining the second conductive layer with titanium or an alloy or compound containing titanium as a main component.

Next, as shown in FIG. 1B, the second conductive layer 105 and the third conductive layer 106 are etched by dry etching. As the etching gas, CF ₄ , Cl ₂ , and O ₂ are used. In order to improve the etching rate, a dry etching apparatus using a high-density plasma source such as ECR (Electron Cyclotron Resonance) or ICP (Inductively Coupled Plasma) is used.

  The mask pattern 107 formed of resist is sputtered by ions accelerated by an electric field, and reaction by-products adhere to the side wall of the workpiece. This is also called a side wall protective film, but the reason why the second conductive layer mainly composed of titanium is tapered in the processing at this stage is to eliminate the side wall protective film. That is, as shown in FIG. 3A, reaction by-products are unlikely to be deposited on the sidewall even if anisotropic etching is performed on the second conductive layer 105 having a tapered portion as shown in FIG. As shown, the second conductive layer 105 ′ and the third conductive layer 106 ′ can be patterned by etching without leaving a residue. On the other hand, when the sidewall of the second conductive layer 105 is almost vertical as shown in FIG. 4A, reaction by-products are deposited during the etching process, and thereafter anisotropic etching is performed as shown in FIG. 4B. However, the reaction by-product remains, resulting in a defective shape. That is, if at least the second conductive layer is processed into a tapered shape at this stage, the sidewall protective film can be eliminated.

Next, the etching gas is switched to CF ₄ and Cl ₂ to etch the tantalum nitride as the first conductive layer. Of course, all the conductive layers may be etched at the same time, but when etching the thick second conductive layer 105, it is necessary to set a longer etching time in consideration of variations in the etching rate. In that case, if the underlayer is silicon oxide, it is etched and becomes extremely thin. In order to prevent this, two-stage etching is performed in this way.

  Thus, as shown in FIG. 1C, the first conductive layer pattern 108 including the first conductive layer 104 ′, the second conductive layer 105 ′, and the third conductive layer 106 ′ is formed on the second insulating film 103. Is done. The angle formed with the surface of the tapered substrate 100 at the end is 10 to 20 degrees. This angle is mainly determined by the relationship with the film thickness of the second conductive layer, but the length occupied by the tapered portion is set to 0.5 to 1.5 μm.

  After each conductive film is tapered, the reaction product adhering to the tapered side wall is removed by argon plasma treatment. If this argon plasma treatment is not performed, the reaction product becomes a stopper even if processing is performed under the anisotropic etching conditions later, and etching residue (bottoming) occurs at the end of the second conductive layer, which is the target as much as possible. Argon plasma treatment after taper processing is necessary to prevent etching residue at the end of the second conductive layer from being formed easily near the vertical. (FIG. 1 (D)).

Then, the second conductive layer 105 ′ and the third conductive layer 106 ′ are selectively etched based on the mask pattern 107 ′ using BCl ₃ , Cl ₂ , and O ₂ as an etching gas. In this case, the bias voltage applied to the substrate side is lowered so that the first conductive layer 104 ′ remains. The end portion of the second conductive layer 105 ′ recedes inward from the end portion of the first conductive layer 104 ′, and the length of Lov is determined by the receding width as will be described later. Thus, a second conductive layer pattern 109 composed of the first conductive layer 104 ′, the second conductive layer 105 ″, and the third conductive layer 106 ″ is formed, and becomes a gate electrode at a portion that intersects the semiconductor layer 102. . (FIG. 1 (E)).

The addition of one conductivity type impurity to the semiconductor layer 103, that is, the formation of LDD and source / drain regions, can be formed in a self-aligned manner using the second conductive layer pattern 109. FIG. 2A shows a doping process for forming an LDD that overlaps with the gate electrode, and ions of one conductivity type impurity are allowed to pass through the first conductive layer 104 ′ and the semiconductor layer 102 located in the lower layer portion thereof. Is added to form a one-conductivity type impurity region 110 having a first concentration. Although depending on the film thickness of the second insulating layer or the first conductive layer, an acceleration voltage of 50 kV or more is required in this case. The impurity concentration of the first concentration one-conductivity type impurity region 110 is 1 × 10 ^{16 to} 5 × 10 ¹⁸ atoms / cm ³ (peak value) assuming LDD.

In the doping process for forming the source / drain regions, the second conductive layer pattern 109 is used as an ion shielding mask, and the first conductive region 111 of the second concentration is formed outside the single conductive impurity region 110 of the first concentration. To do. In this case, the acceleration voltage is set to 30 kV or less. The impurity concentration of the one-conductivity type impurity region 111 of the second concentration is 1 × 10 ^{19 to} 5 × 10 ²¹ atoms / cm ³ (peak value). (Fig. 2 (B))

  Thereafter, a third insulating layer 112 using silicon nitride, a fourth insulating film 113 using a low dielectric constant organic compound material, and a wiring 114 are formed. (Fig. 2 (C))

  As described above, in the present embodiment, a TFT having a gate electrode as a mask at the time of ion doping, forming an LDD overlapping with the gate electrode in a self-aligned manner, and having a length (Lov) of 1 μm or more is provided. Can be formed. The length of the LDD region overlapping with the gate electrode can be set to 1 μm or more so that hot carrier deterioration is less likely to occur.

(Example 1)
In this example, an example of processing a gate electrode in accordance with the process based on Embodiment Mode 1 will be described. This embodiment will be described with reference to FIG.

First, the first insulating layer 101 is formed on the aluminosilicate glass substrate 100 with a 150 nm silicon oxynitride film by plasma CVD. The semiconductor layer 102 is formed of a crystalline silicon film obtained by crystallizing an amorphous silicon film with a thickness of 50 nm by laser annealing so as to be isolated and isolated in an island shape. As the second insulating film 103, a 115 nm-thick silicon oxynitride film is formed by a plasma CVD method using SiH ₄ and N ₂ O as source gases. The first conductive layer 104 formed of tantalum nitride has a thickness of 30 nm, the second conductive layer 105 formed of titanium has a thickness of 320 nm, and the third conductive layer 106 formed of titanium nitride is formed with a thickness of 50 nm. The mask pattern 107 is made of a positive photoresist and has a thickness of 1.5 μm. The width of the mask pattern may be set appropriately, but in this embodiment, light exposure is formed with mask patterns of 4.5 μm and 10 μm. (Fig. 1 (A))

  Next, the second conductive layer (titanium) 105 and the third conductive layer (titanium nitride) 106 are etched by dry etching. An ICP etching apparatus is used for etching. FIG. 5 shows the configuration of the ICP etching apparatus. The reaction chamber 801 is connected to a gas supply means 803 for etching and an exhaust means 804 for maintaining the reaction chamber in a reduced pressure state. The plasma generating means includes a spiral coil 802 inductively coupled to the reaction chamber 801 via a quartz plate and a high frequency (13.56 MHz) power supply means 805. Bias application to the substrate side is performed by a high frequency (13.56 MHz) power supply means 806 so that a self-bias is generated on a stage describing the substrate. For the etching process, the main parameters are the etching gas type to be supplied, the high-frequency power supplied by the high-frequency (13.56 MHz) power supply means 806 and 807, and the etching pressure.

In the etching process of FIG. 1B, CF ₄ , Cl ₂ , and O ₂ are used as etching gases. The etching pressure is 1.3 Pa, and 500 W of plasma generation power and 300 W of substrate bias power are supplied. Subsequently, as shown in FIG. 1C, the etching gas is switched to CF ₄ and Cl ₂ to etch tantalum nitride as the first conductive layer. As etching conditions at this time, an etching pressure of 1.5 Pa, a power of generating plasma of 500 W, and a power of 10 W of substrate bias are supplied. As described above, the first conductive layer pattern 108 can be formed.

  Thereafter, an argon plasma process is performed to remove or reduce the reaction product (TiOx), which is a stopper film attached to the tapered side wall portion of the first conductive layer pattern 108. Similarly, in this argon plasma process, an ICP etching apparatus is used, argon is supplied at 150 sccm, a plasma generation power of 450 W and a power of 100 W of substrate bias are supplied at a processing pressure of 2.0 Pa, and a process of 30 sec is performed.

Next, anisotropic etching is performed using BCl ₃ , Cl ₂ , and O ₂ as an etching gas to mainly process the second conductive layer 105 ′. The etching pressure is 1.9 Pa, and 500 W of plasma generation power and 10 W of substrate bias power are supplied. The end portion of the second conductive layer 105 ′ recedes inward from the end portion of the first conductive layer 104 ′. In this way, the second conductive layer pattern 109 is formed, which becomes a gate electrode at a portion intersecting with the semiconductor layer 102. The receding width from the end of the first conductive layer 104 ′ can be 1 μm or more. As shown in FIG. 6, the receding width d is a length that determines the Lov length.

  FIG. 7 and FIG. 8 are scanning electron microscope (SEM) images showing typical processed shapes when taper processing, argon plasma processing, and anisotropic etching processing are performed. A state is shown in which a tantalum nitride layer, a titanium layer, a titanium nitride layer, and a resist as a mask material are stacked from the lower layer. This figure is an SEM image observed obliquely and from a cross section, and the receding width of the titanium layer or the protruding width of the tantalum nitride layer is expected to be about 1.0 μm.

Thereafter, phosphorus or boron at a concentration of 1 × 10 ^{16 to} 5 × 10 ¹⁸ atoms / cm ³ (peak value) is ion-doped at an accelerating voltage of 50 kV in the first concentration one-conductivity type impurity region 110 forming the LDD. Added. (Fig. 2 (A))

Further, the doping process for forming the source / drain regions uses the second conductive layer pattern 109 as an ion shielding mask, and the second concentration one-conductivity type impurity region outside the first concentration one-conductivity type impurity region 110. 111 is formed. In this case, the acceleration voltage is set to 10 kV and the phosphorus or boron concentration is set to 1 × 10 ^{19 to} 5 × 10 ²¹ atoms / cm ³ (peak value). (Fig. 2 (B))

  Thereafter, silicon oxynitride containing hydrogen is formed to a thickness of 100 nm by plasma CVD, and photosensitive or non-photosensitive acrylic or polyimide resin is formed to a thickness of 1 μm to form the fourth insulating layer 113. . Further, the wiring 114 is formed as necessary.

As described above, an LDD overlapping with the gate electrode can be formed in a self-aligning manner, and a TFT having a length (Lov) of 1 μm or more can be formed.
(Example 2)

 The present invention can be applied to a semiconductor device provided with various display screens. This is particularly effective for a large-screen semiconductor device in which the diagonal of the display screen exceeds 20 inches.

  FIG. 12 illustrates an example of a structure of a semiconductor device in which a display panel 901 is incorporated in a housing 900, which can be applied as a television receiver or a computer monitor system. The housing 900 is equipped with an amplifier formed of a semiconductor integrated circuit, a high-frequency circuit, an electronic circuit board 902 that incorporates a semiconductor memory or a magnetic memory such as a hard disk as a memory function, and a speaker 903 that reproduces sound. Has been.

  The display panel 901 includes a driver-integrated type in which an active matrix pixel circuit 904, a scanning line driving circuit 905, and a data line driving circuit 906 formed by arranging TFTs in a matrix form are integrally formed using the gate overlap TFT according to the present invention. can do.

  FIG. 11 is a diagram showing a main configuration of the active matrix pixel circuit 904. A gate electrode 302 and a data signal line 303 intersecting with the semiconductor layer 301 are formed in the same layer. That is, the etching process for forming a pattern of the gate electrode or the wiring formed by a laminated body including at least one conductive layer mainly composed of titanium is performed according to the first embodiment. As a result, it is possible to form a gate overlap TFT having a Lov length of 1 μm or more, and the data signal line can also be reduced in resistance. The gate signal line 304 is formed in an upper layer through an interlayer insulating film, and is connected to the gate electrode 302 through a contact hole. Of course, this wiring can also be formed of titanium and aluminum, and the resistance of the wiring can be reduced. A wiring 305 that connects the data signal line 303 and the semiconductor layer 301 can also be formed in the same layer as the gate signal line 304. The pixel electrode 306 is formed using ITO (Indium Tin Oxide) which is a compound of indium oxide and tin oxide. Details of such pixels are disclosed in Japanese Patent Application Laid-Open No. 2001-313397.

  In this embodiment, an example of a semiconductor device is shown, but the present invention is not limited to this embodiment and can be applied to various semiconductor devices. For example, in addition to navigation systems, sound playback devices (car audio, audio components, etc.), notebook personal computers, game machines, portable information terminals (mobile computers, mobile phones, portable game machines, electronic books, etc.), refrigerator devices, Applicable to various fields from home appliances such as washing machines, rice cookers, landline telephones, vacuum cleaners, thermometers, large-scale information play such as hanging advertisements in trains, and information on arrivals and departures at railway stations and airports. Can do.

  The embodiments of the present invention have been described as above. However, it will be understood by those skilled in the art that the modes and details can be variously changed without departing from the spirit and scope of the present invention. It is easy to understand.

FIG. 11 is a cross-sectional view illustrating a manufacturing process of a semiconductor device of the present invention. FIG. 11 is a cross-sectional view illustrating a manufacturing process of a semiconductor device of the present invention. It is a figure explaining the removal effect of the reaction by-product by taper etching. It is a figure explaining the influence of the reaction by-product in case taper etching is not performed. It is a figure explaining the structure of an ICP etching apparatus. It is a figure explaining the relationship between receding width d of the 2nd conductive layer, and Lov length of gate overlap TFT. 2 is an SEM image of the shape of a conductive layer pattern etched according to Example 1 viewed from an oblique direction. 2 is a SEM image showing a cross-sectional shape of a conductive layer pattern etched according to Example 1. FIG. It is a graph which shows the Lov length dependence of an estimated guarantee voltage (on-current 10% degradation). It is a characteristic figure which estimates the lifetime of TFT based on a bias stress test, and is a graph which shows about Lov length dependence. 1 is a top view illustrating a configuration of an active matrix pixel of a semiconductor device according to the present invention. It is a figure which shows an example of a semiconductor device.

Claims (8)

On a semiconductor layer via a gate insulating film, the first conductive layer, and sequentially laminated to form a laminated body and the second conductive layer having an alloy or a compound mainly comprising titanium or titanium,
Forming a mask pattern on the laminate,
Using an ICP etching apparatus, based on the mask pattern, by etching process on the first conductive layer and the second conductive layer, the side wall portion of the first conductive layer and the second conductive layer into a tapered shape forming a first conductive layer pattern,
Using the ICP etching apparatus, by performing an etching process with argon plasma on the first conductive layer pattern, reaction products attached to the side wall portion of the first conductive layer pattern are removed or reduced ,
By performing selective anisotropic etching on the second conductive layer in the first conductive layer pattern to form a second conductive layer pattern,
Wherein the second conductive layer masking the second conductive layer in the pattern, the added one conductivity type impurity into the semiconductor layer, the low concentration in a region overlapping with the first conductive layer in the second conductive layer pattern Forming a drain region ,
A method for manufacturing a semiconductor device, comprising forming a transistor having the semiconductor layer, the gate insulating film, and the second conductive layer pattern . According to claim 1, wherein the first conductive layer, a method for manufacturing a semiconductor device, wherein the Ru tantalum nitride der. A stacked body is formed by sequentially stacking a first conductive layer, titanium, a second conductive layer containing titanium or an alloy or a compound containing titanium , and a third conductive layer on the semiconductor layer with a gate insulating film interposed therebetween. ,
Forming a mask pattern on the laminate,
Using the ICP etching apparatus, the first conductive layer, the second conductive layer, and the third conductive layer are etched based on the mask pattern, whereby the first conductive layer and the second conductive layer are etched. and forming a first conductive layer pattern side wall portions of the third conductive layer in a tapered shape,
Using the ICP etching apparatus, by performing an etching process with argon plasma on the first conductive layer pattern, a reaction product adhering to the side wall portion of the first conductive layer pattern is removed or reduced ,
By performing selective anisotropic etching on the first conductive layer and the second conductive layer in the pattern and the third conductive layer, forming a second conductive layer pattern,
Using the second conductive layer and the third conductive layer in the second conductive layer pattern as a mask, an impurity of one conductivity type is added to the semiconductor layer, and the first conductive layer in the second conductive layer pattern A low-concentration drain region is formed in a region overlapping with
A method for manufacturing a semiconductor device, comprising forming a transistor having the semiconductor layer, the gate insulating film, and the second conductive layer pattern . According to claim 3, wherein the first conductive layer is tantalum nitride, a method for manufacturing a semiconductor device, characterized in that before the third conductive layer SL is titanium nitride. The method for manufacturing a semiconductor device according to claim 1 , wherein the reaction product is TiOx . In any one of claims 1 to 5, a method for manufacturing a semiconductor device, wherein the length of the lightly doped drain region overlapping with the second conductive layer pattern is 1μm or more. In any one of claims 1 to 6, the method for manufacturing a semiconductor device, characterized in that the angle between the tapered first conductive layer pattern side wall and the substrate surface is 20 degrees or less than 10 degrees . In any one of claims 1 to 7, for manufacturing a semiconductor device according to the to the first conductive layer pattern etching process for forming the, characterized by using an etching gas containing CF _4, Cl ₂ and O ₂ Method.