JP4702001B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device including an insulated gate transistor capable of independently controlling a substrate potential.

Conventionally, a substrate potential control circuit for controlling a substrate potential is connected to a substrate potential dedicated electrode extending from a body contact region provided outside a source or emitter cell of a power MOS (Metal Oxide Semiconductor) transistor. A technique is disclosed in which a voltage is applied to make the potential difference between the gate electrode and the substrate constant when the transistor is turned on and off, and a reverse bias is applied to the substrate when the transistor is turned off (see Patent Document 1).
Japanese Patent No. 362293 (pages 1 to 10 and FIGS. 9 and 10)

  In the technique of Patent Document 1, the substrate potential and the source potential are controlled independently, the potential difference between the gate and the substrate is made constant by turning the transistor on and off, and a reverse bias is applied to the substrate when the transistor is turned off. The switching characteristics are improved by eliminating the charge and discharge in the parasitic capacitance formed between the two and the turn-off time and the turn-off time, thereby reducing the switching delay.

  However, even in the technique of Patent Document 1, since it takes time to extract the charge accumulated in the parasitic capacitance formed between the gate and the drain when the transistor is turned off, the turn-off time cannot be sufficiently shortened. There was a problem.

Note that Patent Document 1 describes that switching characteristics can be improved by applying a voltage that makes the potential difference between the gate and the substrate constant by turning on and off the transistor.
Patent Document 1 describes that the threshold voltage can be optimized by applying a reverse bias to the substrate when the transistor is turned off.

That is, the description in Patent Document 1 misunderstands that the technique of making the potential difference between the gate electrode and the substrate constant by turning the transistor on and off and the technique of applying a reverse bias to the substrate when the transistor is turned off are completely different techniques. It invites.
However, if the potential difference between the gate electrode and the substrate is constant when the transistor is turned on and off, a reverse bias is applied to the substrate when the transistor is turned off.
However, when a reverse bias is applied to the substrate when the transistor is turned off, the potential difference between the gate electrode and the substrate does not need to be constant depending on whether the transistor is turned on or off.

  The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device including an insulated gate transistor capable of shortening the turn-off time and suppressing heat generation due to switching. is there.

The invention described in claim 1
An insulated gate transistor (Tp, Tn) having an insulated gate;
A semiconductor device (10, 30) comprising a substrate potential control circuit (14, 32) for controlling the substrate potential (VB) of the transistor,
The substrate potential control circuit includes:
When the transistor is turned off, the substrate potential is increased so that the absolute value (| Vt−Vin |) of the potential difference between the threshold voltage (Vt) of the transistor and the voltage (Vin) input to the gate of the transistor increases. By applying a reverse bias to the transistor substrate ,
The timing (t4) at which the reverse bias is applied is after the time point (t3) when the turn-on of the transistor is completed, and when the voltage (Vin) input to the gate of the transistor is switched to a level at which the transistor is turned off ( t5) previously set to be the technical features of the Rukoto.

The invention described in claim 2
The semiconductor device (10, 30) according to claim 1 ,
The substrate potential control circuit (14, 32) has a timing (t8) for releasing the reverse bias applied to the substrate of the transistor (Tp, Tn) after the time (t7) when the transistor is turned off, and A technical feature is that the voltage (Vin) input to the gate of the transistor is set before the time (t9) when the voltage is switched to a level at which the transistor is turned on again.

The invention according to claim 3
The semiconductor device according to claim 1 or 2 ,
The substrate potential control circuit (14, 32)
Voltage generating means (16, 34) for generating voltages (Vp, Vq) for applying a reverse bias to the substrate of the transistors (Tp, Tn);
Delay means (19) for delaying and outputting a signal (Vin) input to the gate of the transistor by a predetermined delay time (tc);
The present invention is characterized by comprising voltage application means (Tc, Te) for applying the voltage generated by the voltage generation means to the substrate of the transistor in accordance with the signal output from the delay means.

<Claim 1>
In an insulated gate transistor, the absolute value of the threshold voltage viewed from the source potential (emitter potential) is increased by applying a reverse bias to the substrate to generate the substrate effect.

For example, in a P-channel MOS transistor (Tp), by raising the substrate potential (VB) to apply a reverse bias to the substrate to generate the substrate effect, the threshold voltage (Vt) viewed from the source potential (Vs) is obtained. ) Can be increased and the actual value of the threshold voltage can be decreased.
In the N-channel MOS transistor (Tn), the substrate potential (VB) is lowered to apply a reverse bias to the substrate to generate a substrate effect, thereby causing a threshold voltage (Vt) viewed from the source potential (Vs). ) Can be increased and the actual value of the threshold voltage can be increased.

Here, the transistor turn-off time is the time when the gate potential (Vg) reaches the threshold voltage (Vt) from the time (t5) when the voltage (Vin) input to the gate of the transistor is switched to a level for turning off the transistor ( The gate potential is constant only during the first period (t5 to t6) until t6) and during the period when charges are extracted from the parasitic capacitance formed between the gate and drain (collector) of the transistor and discharged. This is a time (t5 to t7) obtained by adding the second period (tb: t6 to t7).
At this time, heat generation due to switching of the transistor occurs in the second period.

  In the second period (tb), the amount of charge (Qgd) required to charge the parasitic capacitance formed between the gate and drain of the transistor is input to the threshold voltage (Vt) and the gate. It is proportional to the value divided by the absolute value (| Vt−Vin |) of the potential difference from the voltage (Vin) (Formula 1: tb = Qgd × Rg / | Vt−Vin |).

In the first aspect of the present invention, when the transistor is turned off, the substrate potential (Vt−Vin |) is increased so that the absolute value (| Vt−Vin |) of the potential difference between the threshold voltage (Vt) and the voltage (Vin) input to the gate increases. By controlling VB), a reverse bias is applied to the substrate of the transistor.
Therefore, the second period (tb) that affects the heat generation of the transistor can be shortened, and the turn-off time of the transistor can be shortened.

By the way, in the technique of Patent Document 1, the potential difference between the gate potential (Vg) and the substrate potential (VB) is made constant by turning on and off the transistor, and a reverse bias is applied to the substrate when the transistors (Tp, Tn) are turned off. .
That is, in the technique of Patent Document 1, a reverse bias is applied to the substrate at a timing (t5) when the voltage (Vin) input to the gate of the transistor switches to a level at which the transistor is turned off.

On the other hand, in the first aspect of the invention, the timing (t4) for applying the reverse bias to the transistor substrate is the time (t3) after the transistor turn-on is completed and the voltage (Vin) input to the gate is It is set before the time point (t5) when the level is switched to turn off the transistor.

Therefore, when the transistor is turned off (t5 to t7), the absolute value (| Vt−Vin |) of the potential difference between the voltage (Vin) input to the gate and the threshold voltage (Vt) is defined in the invention of claim 1 . Compared with the technique of patent document 1, it becomes smaller.
As a result, the second period (tb) is shorter in the invention of claim 1 than in the technique of Patent Document 1.
At this time, in the first period (t5 to t6), the technique of Patent Document 1 is slightly shorter than the invention of claim 1 . However, since the first period is shorter than the second period (tb), the turn-off time (t5 to t7), which is the combined time of the first period and the second period, is claimed as compared to the technique of Patent Document 1. The invention of Item 1 is shorter.
Then, since the heat generation due to the switching of the transistor occurs in the second period (tb), the heat generation due to the switching of the transistor is caused according to the invention of claim 1 in which the second period is shorter than the technique of Patent Document 1. Can be suppressed.
As described above, according to the first aspect of the present invention, the turn-off time that affects the heat generation of the transistor can be further shortened compared to the technique of Patent Document 1.

< Claim 2 >
In the invention of claim 2 , the timing (t8) for releasing the reverse bias applied to the substrate of the transistor (Tp, Tn) is input to the gate of the transistor after the time when the transistor turn-off is completed (t7). It is set before the time point (t9) when the voltage (Vin) switches to a level at which the transistor is turned on again.
Therefore, according to the invention of claim 2 , the operation and effect of the invention of claim 1 can be obtained more reliably.

<Claim 3>
According to a third aspect of the present invention, the substrate potential control circuit (14, 32) comprises a voltage generating means (16, 34), a delay means (19), and a voltage applying means (Tc, Te).
Therefore, according to the invention of claim 3, the substrate potential control circuit capable of obtaining the operation and effect of the invention of claim 1 or claim 2 can be easily realized with a simple configuration.

(Explanation of terms)
The reference numerals in parentheses described in [Means for Solving the Problems] and [Effects of the Invention] are the components and structures described in [Best Mode for Carrying Out the Invention] to be described later. This corresponds to the element code.
The correspondence between the constituent members and constituent elements described in [Means for Solving the Problems] and [Effects of the Invention] and the constituent members and constituent elements described in [Best Mode for Carrying Out the Invention] is as follows: It is as follows.

The “insulated gate type transistor” corresponds to the transistors Tp and Tn.
The “voltage input to the gate of the transistor” corresponds to the signal voltage Vin generated by the oscillation circuit 12.
The “voltage generation means” corresponds to the booster circuit 16 or the step-down circuit 34.
The “delay unit” corresponds to the delay circuit 19.
“Voltage applying means” corresponds to the transistors Tc and Te.

  Hereinafter, embodiments embodying the present invention will be described with reference to the drawings. In each embodiment, the same constituent members and constituent elements are denoted by the same reference numerals, and redundant description of the same content is omitted.

<First Embodiment>
FIG. 1 is a circuit diagram showing a circuit configuration of a semiconductor device 10 according to the first embodiment.
The semiconductor device 10 constituting the oscillation device includes a monolithic IC (Integrated Circuit) in which a P-channel power MOS transistor Tp, a gate resistor Rg, an oscillation circuit 12, and a substrate potential control circuit 14 are integrated on one chip.

The oscillation circuit 12 includes a known ring oscillator in which a plurality of inverter gates INV are connected in a ring shape, and generates and outputs a transistor drive command signal Vin that is a rectangular wave. The oscillation circuit 12 is supplied with power from a DC power supply Vr.
The signal Vin is input to the gate of the transistor Tp via the gate resistor Rg and also input to the substrate potential control circuit 14.
The gate resistance Rg (1) prevents parasitic oscillation of the transistor Tp, (2) prevents a surge voltage from being applied to the gate of the transistor Tp, and (3) current drive capability of the oscillation circuit 12 and the transistor It is provided for the purpose of matching with Tp.

In the transistor Tp, the source is connected to the DC power source Vs, the load Z is connected between the drain and the ground outside the chip of the semiconductor device 10, and the substrate is connected to the substrate potential control circuit 14.
The transistor Tp has a structure capable of independently controlling the substrate potential (substrate potential VB) and the source potential (source potential Vs). The specific structure of the transistor Tp is not limited to the structure disclosed in Patent Document 1 (FIGS. 1 to 8, FIGS. 11 to 16, 19, and 22), and the substrate potential and the source potential can be set independently. Any structure may be used as long as it can be controlled.

  Note that the substrate of the transistor Tp is element-isolated from the substrate on which the oscillation circuit 12 and the substrate potential control circuit 14 are formed using an appropriate element isolation method (for example, trench isolation, LOCOS isolation, etc.). Therefore, the change in the substrate potential VB of the transistor Tp does not affect other elements constituting the circuits 12 and 14, and the transistor Tp and the circuits 12 and 14 can be integrated into one chip to form a composite IC. .

The substrate potential control circuit 14 includes a booster circuit 16 and a substrate bias circuit 18.
The step-up circuit 16 includes a known step-up charge including a ring oscillator OC as an oscillator, transistors Ta and Tb as switching elements, collector resistors Ra and Rb, pumping capacitors Ca and Cb, and diodes Da and Db constituting a rectifier circuit. It consists of a pump circuit, and generates and outputs a positive voltage Vp obtained by boosting the DC power supply Vc.

The substrate bias circuit 18 includes a delay circuit 19 in which a plurality of inverter gates INV are connected in series, a resistor Rs, and a P-channel MOS transistor Tc.
The signal Vin generated by the oscillation circuit 12 is input to the gate of the transistor Tc via the delay circuit 19.
In the transistor Tc, the drain is connected to the substrate of the transistor Tp and is connected to the DC power source Vs through the resistor Rs, and the source is connected to the booster circuit 16 to which the boosted voltage Vp is applied.

  FIG. 2 is a timing chart for explaining the operation of the semiconductor device 10. The gate potential Vg, the substrate potential VB, the threshold voltage Vt, the drain potential Vd of the transistor Tp, and the signal voltage Vin generated by the oscillation circuit 12 are illustrated. It is a graph which shows a time displacement.

In the transistor Tp, a parasitic capacitance is formed between the gate and each part (substrate, source, drain). These parasitic capacitances are determined by the structure of the transistor Tp and the dimensions of each part.
Further, since the source of the transistor Tp is connected to the DC power source Vs, the source potential Vs is a constant voltage equal to the potential of the DC power source Vs.
For ease of explanation, the source potential Vs and the DC power source Vs are denoted by the same reference numerals. Further, the signal Vin that is a rectangular wave generated by the oscillation circuit 12 and the signal voltage Vin are indicated by the same reference numerals.

[When transistor Tp is turned on]
When the signal voltage Vin is switched from the high level (source potential Vs) to the low level (ground potential GND), the transistor Tp starts to turn on (time t1), and charges are injected into the parasitic capacitance of the gate of the transistor Tp and charged. Is started.
Then, when the gate potential Vg reaches the threshold voltage Vt (time t2), the transistor Tp is turned on, and the potential difference between the source and drain of the transistor Tp is reduced, so that the drain potential Vd starts to rise.

At this time, the gate potential Vg is constant while the charge is accumulated in the parasitic capacitance formed between the gate and drain of the transistor Tp and charged (time t2 to t3).
Thereafter, when the potential difference between the source and the drain of the transistor Tp is reduced, the turn-on is completed (time t3), and the gate potential Vg starts to decrease toward the low level of the signal voltage Vin.

Here, the period (time interval) ta from time t2 to t3 is a resistance to the charge amount Qgd required to charge the parasitic capacitance formed between the gate and drain of the transistor Tp, as shown in Equation 1. A value obtained by multiplying the resistance value Rg of Rg is divided by the absolute value (| Vt−Vin |) of the potential difference between the signal voltage Vin and the threshold voltage Vt.
That is, the period ta is proportional to the value obtained by dividing the charge amount Qg by the absolute value (| Vt−Vin |) of the potential difference between the signal voltage Vin and the threshold voltage Vt.
ta = Qgd × Rg / | Vt−Vin | (Equation 1)

[When transistor Tp is turned off]
When the signal voltage Vin is switched from the low level to the high level, the transistor Tp starts to be turned off (time t5), and electric charges are extracted from the parasitic capacitance of the gate of the transistor Tp to start discharging.
Then, when the gate potential Vg reaches the threshold voltage Vt (time t6), the transistor Tp is turned off, and the potential difference between the source and drain of the transistor Tp increases, so the drain potential Vd starts to decrease.

At this time, the gate potential Vg is constant while the charge is extracted from the parasitic capacitance formed between the gate and drain of the transistor Tp and discharged (time t6 to t7).
Thereafter, when the potential difference between the source and the drain of the transistor Tp is increased, the turn-off is completed (time t7), and the gate potential Vg starts to rise toward the high level of the signal voltage Vin.
Here, the period tb from the time t6 to the time t7 is also expressed by the formula 1 (tb = Qgd × Rg / | Vt−Vin |), similarly to the period ta from the time t2 to the time t3.

[Operations and effects of the first embodiment]
According to the first embodiment, the following actions and effects can be obtained.

[1-1] In the MOS transistor, the absolute value of the threshold voltage as viewed from the source potential is increased by applying a reverse bias to the substrate to generate the substrate effect.
In other words, in the P-channel power MOS transistor Tp, the absolute value of the threshold voltage Vt viewed from the source potential Vs is increased by generating a substrate effect by applying a reverse bias to the substrate by increasing the substrate potential VB. And the actual value of the threshold voltage Vt can be lowered.

Thus, in the first embodiment, when the transistor Tp is turned off, the substrate potential VB is controlled so that the absolute value (| Vt−Vin |) of the potential difference between the threshold voltage Vt and the signal voltage Vin becomes large. A reverse bias is applied to the substrate of the transistor Tp.
Therefore, the period tb can be shortened, and the turn-off time of the transistor Tp can be shortened.

That is, in the first embodiment, the substrate effect is generated by applying a reverse bias to the substrate by increasing the substrate potential VB before the time point (time t5) when the signal voltage Vin switches from the low level to the high level. As a result, the absolute value of the threshold voltage Vt viewed from the source potential Vs is increased, and the actual value of the threshold voltage Vt is decreased (time t4).
Further, at a time after the time when the transistor Tp is turned off (time t7), the substrate potential VB is made equal to the source potential Vs, thereby releasing the reverse bias applied to the substrate and stopping the generation of the substrate effect. The absolute value of the threshold voltage Vt viewed from the potential Vs is lowered, and the actual value of the threshold voltage Vt is increased (time t8).
Then, during the period before and after the transistor Tp is turned off, the substrate potential VB is held at a high constant value, and the actual value of the threshold voltage Vt is held at a low constant value (time t4 to t8).

FIG. 3 is a timing chart for explaining the operation when the technique of Patent Document 1 is applied to the P-channel power MOS transistor Tp.
In FIG. 3, the same reference numerals are assigned to the times (timing) at which operations similar to those in FIG. 2 are performed.
In the technique of Patent Document 1, the potential difference between the gate potential Vg and the substrate potential VB is constant when the transistor Tp is turned on and off, and a reverse bias is applied to the substrate when the transistor Tp is turned off.

That is, according to the technique of Patent Document 1, when the signal voltage Vin is switched from the low level to the high level, the substrate potential is reversed by applying a reverse bias to the substrate by generating the substrate potential VB. The observed absolute value of the threshold voltage Vt is increased, and the actual value of the threshold voltage Vt is decreased (time t5).
After the transistor Tp is turned off, the substrate potential VB is changed at a high value and the actual value of the threshold voltage Vt is changed at a low value in order to make the potential difference between the gate potential Vg and the substrate potential VB constant. (Time t5 to t9).

As described above, the timing of applying the reverse bias to the substrate by increasing the substrate potential VB is the time (time t4) before the signal voltage Vin is switched from the low level to the high level in the first embodiment. In the technique of Patent Document 1, it is a time (time t5) when the signal voltage Vin switches from the low level to the high level.
Therefore, when the transistor Tp is turned off (time t5 to t7), the actual value of the threshold voltage Vt of the technique of Patent Document 1 is compared with the actual value Vm of the threshold voltage Vt of the first embodiment. Vn becomes larger.

That is, at the time of turning off the transistor Tp, the absolute value (| Vt−Vin |) of the potential difference between the signal voltage Vin and the threshold voltage Vt is smaller in the technique of Patent Document 1 than in the first embodiment.
Therefore, according to Equation 1, the period tb is shorter in the first embodiment than in the technique of Patent Document 1.

Here, the turn-off time of the transistor Tp is a period from time t5 to t7, and is a time obtained by adding the period tb to the period from time t5 to t6. Then, heat generation due to switching of the transistor Tp occurs in the period tb.
At this time, the period of time t5 to t6 is slightly shorter in the technique of Patent Document 1 than in the first embodiment. However, since the period from time t5 to t6 is shorter than the period tb, the turn-off time of the transistor Tp (time t5 to t7) is shorter in the first embodiment than in the technique of Patent Document 1.
Since the heat generation due to the switching of the transistor Tp occurs in the period tb, the heat generation due to the switching of the transistor Tp can be suppressed according to the first embodiment in which the period tb is shorter compared to the technique of Patent Document 1. .
Thus, according to the first embodiment, the turn-off time that affects the heat generation of the transistor Tp can be further shortened as compared with the technique of Patent Document 1.

  Incidentally, the absolute value (| Vt−Vin |) of the potential difference between the signal voltage Vin and the threshold voltage Vt is greater when the transistor Tp is turned on (time t1 to t3) than when the transistor Tp is turned on (time t1 to t3). Therefore, the period tb is longer than the period ta.

[1-2] In the first embodiment, the timing of applying a reverse bias to the substrate by increasing the substrate potential VB (time t4) is after the time point when the turn-on of the transistor Tp is completed (time t3) and the signal It is necessary to set the voltage Vin before the time (time t5) when the voltage Vin switches from the low level to the high level.
Here, the time point at which the signal voltage Vin switches from the low level to the high level is the time point at which the signal voltage Vin switches to a level at which the transistor Tp is turned off.
The timing for applying the reverse bias to the substrate should desirably be set to a point in time after the gate potential Vg sufficiently drops toward the low level of the signal voltage Vin.

The specific value of the timing for applying the reverse bias to the substrate is an experimentally optimum value by cutting and trying, taking into account a sufficient margin for reliably obtaining the operation and effect of [1-1]. Find and set.
For example, it may be set to be 30% or more and 90% or less in the period from the time when the signal voltage Vin switches from the high level to the low level (time t1) to the time when the signal voltage Vin switches again to the high level (time t5).

[1-3] In the first embodiment, the timing for releasing the reverse bias applied to the substrate by making the substrate potential VB equal to the source potential Vs (time t8) is the time when the turn-off of the transistor Tp is completed (time t7). Thereafter, it is necessary to set the signal voltage Vin before the time point (time t9) when the signal voltage Vin switches from the high level to the low level again.
Here, the time point at which the signal voltage Vin switches from the high level to the low level again is the time point at which the signal voltage Vin switches to a level at which the transistor Tp is turned on again.
The timing for releasing the reverse bias applied to the substrate should desirably be set to a point after the gate potential Vg has sufficiently increased toward the high level of the signal voltage Vin.

The specific value of the timing for releasing the reverse bias applied to the substrate is experimentally determined by cut-and-try after allowing for a sufficient margin for reliably obtaining the operation and effect of [1-1]. Find and set the optimal value.
For example, it may be set to be 50% or more and 90% or less in the period from the time when the signal voltage Vin switches from the low level to the high level (time t5) to the time when the signal voltage Vin switches to the low level again (time t9).

[1-4] The signal voltage Vin is input to the gate of the P-channel MOS transistor Tc via the delay circuit 19.
In the transistor Tc, the drain is connected to the substrate of the transistor Tp and is connected to the DC power source Vs via the resistor Rs, and the source is connected to the booster circuit 16 to which the boosted voltage Vp is applied.

Therefore, the transistor Tc is turned on after the delay time tc by the delay circuit 19 has elapsed from the time (time t1) when the signal voltage Vin switches from the high level to the low level. Then, the boosted voltage Vp is applied to the substrate of the transistor Tp via the turned-on transistor Tc, and the substrate potential VB becomes equal to the boosted voltage Vp.
Further, the transistor Tc is turned off after the delay time tc by the delay circuit 19 has elapsed from the time (time t5) when the signal voltage Vin switches from the low level to the high level. Then, the source potential Vs is applied to the substrate of the transistor Tp via the resistor Rs, and the substrate potential VB becomes equal to the source potential Vs.
As a result, the substrate potential VB changes as in [1-1].

Here, since the delay time tc of the delay circuit 19 is a period from time t1 to t4 and a period from time t5 to t8, it may be set as [1-2] [1-3].
The resistor Rs is provided in order to prevent the substrate potential VB from being equal to the source potential Vs when the transistor Tc is turned on. The resistance value is experimentally found by cutting and trying. What is necessary is just to set, for example, to several hundred-several thousand ohms.
Thus, the substrate potential control circuit 14 can be easily realized with a simple configuration.

Second Embodiment
FIG. 4 is a circuit diagram illustrating a circuit configuration of the semiconductor device 30 according to the second embodiment.
The semiconductor device 30 constituting the oscillation device is composed of a monolithic IC in which an N-channel power MOS transistor Tn, a gate resistor Rg, an oscillation circuit 12, and a substrate potential control circuit 32 are integrated on one chip.

  The signal Vin generated by the oscillation circuit 12 is input to the gate of the transistor Tn via the gate resistor Rg and also input to the substrate potential control circuit 32.

In the transistor Tn, the source is connected to the ground, the load Z is connected between the drain and the DC power supply Va outside the chip of the semiconductor device 30, and the substrate is connected to the substrate potential control circuit 32.
The transistor Tn has a structure in which the substrate potential and the source potential can be controlled independently. Note that the specific structure of the transistor Tn is not limited to the structure disclosed in Patent Document 1, and may be any structure as long as the substrate potential and the source potential can be controlled independently.

  Note that the substrate of the transistor Tn is element-isolated from the substrate on which the oscillation circuit 12 and the substrate potential control circuit 32 are formed using an appropriate element isolation method (for example, trench isolation, LOCOS isolation, etc.). Therefore, the change in the substrate potential VB of the transistor Tn does not affect other elements constituting the circuits 12 and 32, and the transistor Tn and the circuits 12 and 34 can be integrated into one chip to form a composite IC. .

The substrate potential control circuit 32 includes a step-down circuit 34 and a substrate bias circuit 36.
The step-down circuit 34 is composed of a known step-down circuit including a ring oscillator OC as an oscillator, a transistor Td as a switching element, an inductor L, a pumping capacitor Cc, and a diode Dc constituting a rectifier circuit. A voltage Vq is generated and output.

The substrate bias circuit 36 includes a delay circuit 19 in which a plurality of inverter gates INV are connected in series, a resistor Rs, and an N-channel MOS transistor Te.
The signal Vin generated by the oscillation circuit 12 is input to the gate of the transistor Te through the delay circuit 19.
In the transistor Te, the drain is connected to the substrate of the transistor Tn and is connected to the ground via the resistor Rs, and the source is connected to the step-down circuit 34 to which the step-down voltage Vq is applied.

  FIG. 5 is a timing chart for explaining the operation of the semiconductor device 30. The gate potential Vg of the transistor Tn, the substrate potential VB, the threshold voltage Vt, the drain potential Vd, and the signal voltage Vin generated by the oscillation circuit 12 are shown. It is a graph which shows a time displacement.

In the transistor Tn, a parasitic capacitance is formed between the gate and each part (substrate, source, drain). These parasitic capacitances are determined by the structure of the transistor Tn and the dimensions of each part.
Further, since the source of the transistor Tn is connected to the ground, the source potential Vs is the ground potential GND.
Note that the potential Va of the DC power supply Va is equal to the potential Vs of the DC power supply Vs of the first embodiment.

[When transistor Tn is turned on]
When the signal voltage Vin is switched from the low level (ground potential GND) to the high level (potential Va), the transistor Tn is turned on (time t1), and charge is injected into the parasitic capacitance of the gate of the transistor Tn to charge the transistor Tn. Be started.
When the gate potential Vg reaches the threshold voltage Vt (time t2), the transistor Tn is turned on, and the potential difference between the source and the drain of the transistor Tn is decreased, so that the drain potential Vd starts to decrease.

At this time, the gate potential Vg is constant while charge is accumulated in the parasitic capacitance formed between the gate and drain of the transistor Tn (time t2 to t3).
After that, when the potential difference between the source and drain of the transistor Tn is reduced, the turn-on is completed (time t3), and the gate potential Vg starts to rise toward the high level of the signal voltage Vin.

  Here, during the period ta from time t2 to t3, as shown in the equation 1, the resistance Rg is added to the charge amount Qgd necessary for charging the parasitic capacitance formed between the gate and drain of the transistor Tn. The value obtained by multiplying the value Rg is divided by the absolute value (| Vt−Vin |) of the potential difference between the signal voltage Vin and the threshold voltage Vt.

[When transistor Tn is turned off]
When the signal voltage Vin is switched from the high level to the low level, the transistor Tn starts to be turned off (time t5), and electric charges are extracted from the parasitic capacitance of the gate of the transistor Tn to start discharging.
Then, when the gate potential Vg reaches the threshold voltage Vt (time t6), the transistor Tn is turned off, and the potential difference between the source and drain of the transistor Tn increases, so that the drain potential Vd starts to rise.

At this time, the gate potential Vg is constant while the charge is extracted from the parasitic capacitance formed between the gate and drain of the transistor Tn and discharged (time t6 to t7).
Thereafter, when the potential difference between the source and the drain of the transistor Tn is increased, the turn-off is completed (time t7), and the gate potential Vg starts to decrease toward the low level of the signal voltage Vin.
Here, the period tb from the time t6 to the time t7 is also expressed by the formula 1 (tb = Qgd × Rg / | Vt−Vin |), similarly to the period ta from the time t2 to the time t3.

[Operation and Effect of Second Embodiment]
According to the second embodiment, the following actions and effects can be obtained.

  [2-1] In the N-channel power MOS transistor Tn, the substrate potential VB is lowered to apply a reverse bias to the substrate to generate a substrate effect, whereby the absolute value of the threshold voltage Vt viewed from the source potential Vs is obtained. The value can be increased and the actual value of the threshold voltage Vt can be increased.

Therefore, in the second embodiment, when the transistor Tn is turned off, the substrate potential VB is controlled so that the absolute value (| Vt−Vin |) of the potential difference between the threshold voltage Vt and the signal voltage Vin becomes large. A reverse bias is applied to the substrate of the transistor Tn.
Therefore, the period tb can be shortened, and the turn-off time of the transistor Tn can be shortened.

That is, in the second embodiment, the substrate effect is generated by applying a reverse bias to the substrate by lowering the substrate potential VB before the time (time t5) when the signal voltage Vin switches from the high level to the low level. Thus, the absolute value of the threshold voltage Vt viewed from the source potential Vs (= ground potential GND) is increased, and the actual value of the threshold voltage Vt is increased (time t4).
Further, at the time after the time when the transistor Tn is turned off (time t7), the substrate potential VB is made equal to the source potential Vs (= ground potential GND), thereby releasing the reverse bias applied to the substrate and generating the substrate effect. By stopping, the absolute value of the threshold voltage Vt viewed from the source potential Vs is lowered, and the actual value of the threshold voltage Vt is lowered (time t8).
Then, during the period before and after the transistor Tn is turned off, the substrate potential VB is held at a low constant value, and the actual value of the threshold voltage Vt is held at a high constant value (time t4 to t8).

FIG. 6 is a timing chart for explaining the operation when the technique of Patent Document 1 is applied to an N-channel power MOS transistor Tn.
In FIG. 6, the same reference numerals are given to the times (timing) at which the same operations as in FIG. 5 are performed.
In the technique of Patent Document 1, the potential difference between the gate potential Vg and the substrate potential VB is constant when the transistor Tn is turned on and off, and a reverse bias is applied to the substrate when the transistor Tn is turned off.

That is, in the technique of Patent Document 1, when the signal voltage Vin is switched from the high level to the low level, the substrate potential VB is lowered to reverse bias the substrate to generate the substrate effect, thereby generating the source potential Vs ( = The absolute value of the threshold voltage Vt viewed from the ground potential GND) is increased, and the actual value of the threshold voltage Vt is increased (time t5).
After the transistor Tn is turned off, the substrate potential VB is changed at a low value and the actual value of the threshold voltage Vt is changed at a high value in order to make the potential difference between the gate potential Vg and the substrate potential VB constant. (Time t5 to t9).

As described above, the timing of applying the reverse bias to the substrate by lowering the substrate potential VB is the time (time t4) before the signal voltage Vin is switched from the high level to the low level in the second embodiment. In the technique of Patent Document 1, it is a time point (time t5) when the signal voltage Vin is switched from the high level to the low level.
Therefore, when the transistor Tn is turned off (time t5 to t7), compared to the actual value Vx of the threshold voltage Vt of the second embodiment, the actual value of the threshold voltage Vt of the technique of Patent Document 1 is described. Vy becomes smaller.

That is, when the transistor Tn is turned off, the absolute value (| Vt−Vin |) of the potential difference between the signal voltage Vin and the threshold voltage Vt is smaller in the technique of Patent Document 1 than in the second embodiment.
Therefore, according to Equation 1, the period tb is shorter in the first embodiment than in the technique of Patent Document 1.

Here, the turn-off time of the transistor Tn is a period from time t5 to t7, and is a time obtained by adding the period tb to the period from time t5 to t6. Then, heat generation due to switching of the transistor Tn occurs in the period tb.
At this time, the period of time t5 to t6 is slightly shorter in the technique of Patent Document 1 than in the second embodiment. However, since the period from time t5 to t6 is shorter than the period tb, the turn-off time of the transistor Tn (time t5 to t7) is shorter in the second embodiment than in the technique of Patent Document 1.
Since the heat generation due to the switching of the transistor Tn occurs in the period tb, the heat generation due to the switching of the transistor Tn can be suppressed according to the second embodiment in which the period tb is shorter compared to the technique of Patent Document 1. .
Thus, according to the second embodiment, the turn-off time that affects the heat generation of the transistor Tn can be further shortened as compared with the technique of Patent Document 1.

  Incidentally, the absolute value (| Vt−Vin |) of the potential difference between the signal voltage Vin and the threshold voltage Vt is greater when the transistor Tn is turned on (time t1 to t3) than when the transistor Tn is turned on (time t1 to t3). Therefore, the period tb is longer than the period ta.

[2-2] In the second embodiment, the timing of applying a reverse bias to the substrate by lowering the substrate potential VB (time t4) is after the time point when the turn-on of the transistor Tn is completed (time t3) and the signal It is necessary to set the voltage Vin before the time (time t5) when the voltage Vin switches from the high level to the low level.
Here, the time when the signal voltage Vin is switched from the high level to the low level is the time when the signal voltage Vin is switched to a level at which the transistor Tn is turned off.
The timing for applying the reverse bias to the substrate should desirably be set to a point after the gate potential Vg has sufficiently increased toward the high level of the signal voltage Vin.

The specific value of the timing for applying the reverse bias to the substrate is an experimentally optimum value by cutting and trying, with a sufficient margin for reliably obtaining the operation and effect of [2-1]. Find and set.
For example, it may be set to be 30% or more and 90% or less in the period from the time when the signal voltage Vin switches from the low level to the high level (time t1) to the time when the signal voltage Vin switches again to the low level (time t5).

[2-3] In the second embodiment, the turn-off of the transistor Tn is completed at the timing (time t8) of releasing the reverse bias applied to the substrate by making the substrate potential VB equal to the source potential Vs (= ground potential GND). It is necessary to set after the time (time t7) and before the time (time t9) when the signal voltage Vin switches from the low level to the high level again.
Here, the time point at which the signal voltage Vin switches from the low level to the high level again is the time point at which the signal voltage Vin switches to a level at which the transistor Tn is turned on again.
The timing for releasing the reverse bias applied to the substrate should desirably be set to a point after the gate potential Vg has sufficiently dropped toward the low level of the signal voltage Vin.

Note that the specific value of the timing for releasing the reverse bias applied to the substrate is experimentally determined by cutting and trying after a sufficient margin for reliably obtaining the operation and effect of [2-1]. Find and set the optimal value.
For example, it may be set to be 50% or more and 90% or less in the period from the time when the signal voltage Vin switches from the high level to the low level (time t5) to the time when the signal voltage Vin switches again to the high level (time t9).

[2-4] The signal voltage Vin is input to the gate of the N-channel MOS transistor Te via the delay circuit 19.
In the transistor Te, the drain is connected to the substrate of the transistor Tn and is connected to the ground via the resistor Rs to be the ground potential GND, and the source is connected to the step-down circuit 34 to which the step-down voltage Vq is applied. ing.

Therefore, the transistor Te is turned on after the delay time tc by the delay circuit 19 has elapsed from the time (time t1) when the signal voltage Vin switches from the low level to the high level. Then, the step-down voltage Vq is applied to the substrate of the transistor Tn through the turned-on transistor Te, and the substrate potential VB becomes equal to the step-down voltage Vq.
Further, the transistor Te is turned off after the delay time tc by the delay circuit 19 has elapsed from the time (time t5) when the signal voltage Vin switches from the high level to the low level. Then, the ground potential GND is applied to the substrate of the transistor Tn via the resistor Rs, and the substrate potential VB becomes equal to the ground potential GND.
As a result, the substrate potential VB changes as in [2-1].

Here, since the delay time tc of the delay circuit 19 is a period from time t1 to t4 and a period from time t5 to t8, it may be set as [2-2] [2-3].
The resistor Rs is provided to prevent the substrate potential VB from becoming equal to the ground potential GND when the transistor Te is turned on. The resistance value is experimentally found by cutting and trying. What is necessary is just to set, for example, to several hundred-several thousand ohms.
Thus, the substrate potential control circuit 32 can be easily realized with a simple configuration.

<Another embodiment>
The present invention is not limited to the above-described embodiments, and may be embodied as follows. Even in this case, operations and effects equivalent to or higher than those of the above-described embodiments can be obtained.

[1] The booster circuit 16 of the first embodiment is formed of a charge pump circuit, but any circuit may be used as long as it can generate the boosted voltage Vp. Further, the booster circuit 16 may be replaced with a positive high voltage power source that generates the voltage Vp.
Also, any circuit may be used for the step-down circuit 34 of the second embodiment as long as the step-down voltage Vq can be generated. Further, the step-down circuit 34 may be replaced with a negative high voltage power source that generates the voltage Vq.

  [2] In the above embodiments, the DC power sources Vr, Vs, and Vc are provided separately. However, the DC power sources Vr, Vs, and Vc may be shared.

  [3] Each of the above embodiments is applied to a semiconductor device that constitutes an oscillation device. However, the present invention may be applied to any device as long as the power MOS transistor is turned on / off.

  [4] Each of the above embodiments includes a monolithic IC in which semiconductor devices are integrated on a single chip, but a power MOS transistor may be configured as a single device.

[5] Although each of the above embodiments is applied to a MOS transistor, the present invention can be applied to any type of transistor as long as it is an insulated gate transistor driven by forming a channel with an insulated gate. Good.
The present invention may be applied not only to an insulated gate transistor having one channel but also to an insulated gate transistor having a plurality of channels.

  Insulated gate transistors include IGBTs (Insulated Gate Bipolar Transistors) and IGFETs (Insulated Gate Field Effect Transistors). When the present invention is applied to an IGBT, the source of the MOS transistor in each of the above embodiments corresponds to the emitter of the IGBT, and the drain of the MOS transistor corresponds to the collector of the IGBT.

The gate structure of the IGFET may be any structure as long as it has a broad MIS (Metal Insulated Semiconductor) structure including a MOS (Metal Oxide Semiconductor) structure.
The structure of the source / drain region of the IGFET may be any structure such as LDMOS (Laterally Diffused MOS) or VDMOS (Vertical Diffused MOS).

1 is a circuit diagram showing a circuit configuration of a semiconductor device 10 according to a first embodiment embodying the present invention; 4 is a timing chart for explaining the operation of the semiconductor device 10 and shows the time displacement of the gate potential Vg, substrate potential VB, threshold voltage Vt, drain potential Vd of the transistor Tp and the signal voltage Vin generated by the oscillation circuit 12; It is a graph. 10 is a timing chart for explaining an operation when the technique of Patent Document 1 is applied to a P-channel power MOS transistor Tp. It is a circuit diagram which shows the circuit structure of the semiconductor device 30 of 2nd Embodiment which actualized this invention. 4 is a timing chart for explaining the operation of the semiconductor device 30 and shows the time displacement of the gate potential Vg, the substrate potential VB, the threshold voltage Vt, the drain potential Vd of the transistor Tn, and the signal voltage Vin generated by the oscillation circuit 12; It is a graph. 12 is a timing chart for explaining an operation when the technique of Patent Document 1 is applied to an N-channel power MOS transistor Tn.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Semiconductor device of 1st Embodiment 12 ... Oscillator circuit 14 ... Substrate potential control circuit 16 ... Booster circuit (voltage generation means)
18 ... Substrate bias circuit 19 ... Delay circuit (delay means)
DESCRIPTION OF SYMBOLS 30 ... Semiconductor device of 2nd Embodiment 32 ... Substrate potential control circuit 34 ... Step-down circuit (voltage generation means)
36 ... Substrate bias circuit Tp ... P-channel power MOS transistor Tc ... P-channel MOS transistor (voltage applying means)
Tn: N channel power MOS transistor Te: N channel MOS transistor (voltage applying means)
Rg: Gate resistance Rs: Resistance Vin: Transistor drive command signal (signal voltage)
Vg ... gate potential Vd ... drain potential Vs ... source potential Vt ... threshold voltage VB ... substrate potential Vp ... boost voltage Vq ... step-down voltage GND ... ground potential Va ... potential of DC power supply Va

Claims (3)

An insulated gate transistor with an insulated gate; and
A semiconductor device comprising a substrate potential control circuit for controlling the substrate potential of the transistor,
The substrate potential control circuit includes:
When the transistor is turned off, the substrate potential is controlled so that the absolute value of the potential difference between the threshold voltage of the transistor and the voltage input to the gate of the transistor is increased, thereby reverse biasing the substrate of the transistor. the over,
The timing for applying the reverse bias, and later when the turn-on of the transistor is completed, and the voltage input to the gate of the transistor is characterized that you set before the time of switching to the level for turning off the transistor Semiconductor device. The semiconductor device according to claim 1 ,
The substrate potential control circuit releases the reverse bias applied to the substrate of the transistor after the completion of turn-off of the transistor, and the voltage input to the gate of the transistor turns on the transistor again. A semiconductor device that is set before the time of switching to a level. The semiconductor device according to claim 1 or 2 ,
The substrate potential control circuit includes:
Voltage generating means for generating a voltage for applying a reverse bias to the substrate of the transistor;
Delay means for delaying and outputting a signal input to the gate of the transistor by a predetermined delay time;
A semiconductor device comprising: a voltage applying unit that applies a voltage generated by the voltage generating unit to a substrate of the transistor in accordance with a signal output from the delay unit.

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