JP4728779B2 - Detection circuit - Google Patents

Description

  The present invention relates to a method for confirming a connection state after mounting a semiconductor integrated circuit chip (LSI chip) on a substrate such as a package.

  Conventionally, detection of whether or not an electrode pad on an LSI chip (hereinafter also referred to simply as “chip”) and a lead terminal on a package are electrically connected is performed by using a dummy pad at the corner of the LSI chip. In this case, the connection state between the electrode pad and the lead terminal is determined at the package stage by electrically connecting them, sealing the package, and performing an open / short test on the terminals to which the pads are connected. However, it was determined whether or not a problem occurred. Also, a JTAG test circuit is inserted at the chip design stage, and after mounting the product, the connection state between the electrode pad and the lead terminal is detected by open / short of a DC test using the JTAG circuit.

  Further, on the input side, a pad that outputs “H” (power supply voltage level) as a detection signal if it is short-circuited with GND (ground voltage level) is provided, and a detection signal from the pad and a control signal input from outside are provided. Is input to an OR (logical sum) gate, and the output of the OR gate is output to the outside (for example, see Patent Document 1). In this semiconductor integrated circuit, a plurality of chips incorporating these mechanisms are mounted on a substrate, and respective inputs and outputs are sequentially connected to confirm a short circuit with GND or a connection state between the substrate and the chip. is there.

JP-A-8-285924

  All of the above-described conventional techniques are for confirming the connection state between the chip immediately after mounting the LSI chip and the substrate (lead terminal), and cannot be confirmed after assembly as a product such as an electronic device is completed. There was a problem.

  In recent years, as portable devices and the like have become thinner, for high-density mounting, for example, in a semiconductor device in which a chip is supported by electrically connecting electrode pads on the chip and lead terminals of the package, Films (TCP, COP, etc.) that are substrates on which LSI chips are mounted are also becoming thinner. Since the film is easily bent due to the reduction in thickness, there is an increased risk that the electrode pad of the LSI chip is peeled off from the lead terminal on the film. In addition, for example, when a plurality of LSIs such as a liquid crystal driver LSI and a liquid crystal controller LSI are mounted on a film and mounted in plural, the mounting method may be different. For this reason, when a plurality of LSIs are mounted, it is difficult to perform a check after mounting the LSI and identify a defective LSI, as compared with a case where a mounting state (connection state) of one LSI is confirmed by a tester or the like.

  The present invention has been made in view of the above problems, and an object of the present invention is to detect a connection state between a semiconductor integrated circuit chip and a substrate side in contact with the same in a state where the chip is mounted on a substrate. A semiconductor device is provided.

In order to achieve the above object, a detection circuit according to the present invention is a semiconductor device in which the chip is supported by electrically connecting an electrode pad on a semiconductor integrated circuit chip and a lead terminal of the package. Is a detection circuit for detecting separation from the package, wherein the input level is a first buffer having at least an input buffer capable of fixing the input level to a predetermined first level, and the output level is a second level different from the first level A second buffer having at least an output buffer capable of being output, a first electrode pad connected to an input terminal of the first buffer, and a second electrode pad connected to an output terminal of the second buffer, In a state where the first electrode pad and the second electrode pad are connected outside the chip via the lead terminal, the inspection trigger signal When the second buffer outputs the second level, the first buffer determines that it is normal when it detects the second level input, and the first buffer receives the first level input. The first feature is that a pair of the first electrode pad and the second electrode pad is arranged at each of the four corners of the chip. .

The detection circuit having the above characteristics is characterized in that the first electrode pad and the second electrode pad are provided in a peripheral portion of the chip.

Detection circuit of any of the above features, the first buffer is a third feature in that the input terminal is a bidirectional buffer with a pull-up or pull-down mechanism.

Detection circuit of any of the above features, the second buffer, and the fourth being a bidirectional buffer with the input control function.

Any of the above detection circuit feature comprises a possible status register stores the verification result data inside the chip, and the fifth, characterized in that the verification result data of the status register is configured externally readably .

In order to achieve the above object, a semiconductor device according to the present invention includes a detection circuit having any one of the above characteristics, and the first electrode pad and the second electrode pad are disposed outside the chip via the lead terminal of the package. And are connected.

  In the present invention, the package refers to a package that supports at least one LSI chip and exchanges electrical signals with the chip, and includes a printed circuit board and the like.

  According to the present invention, at least a first buffer having an input buffer capable of fixing an input level to a predetermined first level, and at least an output buffer capable of outputting with a second level different from the first level. Since the configuration includes the second buffer, the conductive state between the electrode pad and the lead terminal can be detected using a standard buffer without using a special circuit such as a JTAG circuit, and the connection state between the chip and the package can be determined. It can be detected and does not require extra cost. Furthermore, if the configuration is such that no operation is performed at all in the normal state, only one clock cycle is operated at the time of test execution, so that power consumption is not affected. In addition, since a normal input buffer, output buffer, or I / O buffer registered in the library can be used as it is, there is no need to newly create a special test buffer, and the detection circuit can be configured with a simple configuration. Can be realized.

  Furthermore, for detecting the connection state between the chip and the package, a detection circuit for the first electrode pad or the second electrode pad is realized at one location on the chip by two buffers, the first buffer and the second buffer. If four are used and installed at four corners of the chip, the connection state between the chip and the package at the four corners of the chip can be detected. Usually, when bonding chips, there are many situations in which the vicinity of the center is bent and the four corners of the chip are open. By detecting the conduction state between the electrode pad and the lead terminal at the four corners of the chip, It becomes possible to detect a connection failure between the chip and the package with a limited circuit configuration.

  Further, in the case of a configuration in which the detection circuit is realized by a logic circuit and includes a status register for holding the result, the presence or absence of the problem can be detected from the host side by software after the product is completed. Thereby, it is possible to easily check the mounting state even after the assembly of the electronic device is completed. In addition, by periodically checking the software, the connection status of the chip is checked during normal operation. If a problem occurs, the system is shut down, etc. Measures for avoiding the influence on other circuits can be taken, and the product can be prevented from being destroyed.

  Hereinafter, embodiments of a detection circuit according to the present invention (hereinafter abbreviated as “the circuit of the present invention” as appropriate) will be described with reference to the drawings.

  First, the configuration of the circuit of the present invention and the semiconductor device mounting the circuit of the present invention will be described with reference to FIGS. The semiconductor device on which the circuit 1 of the present invention is mounted is obtained by thermocompression bonding of bumps formed on electrode pads on a chip and inner leads (lead terminals) formed on a film (corresponding to a substrate on the package side), The chip and the film are connected. Here, FIG. 1 shows a semiconductor device including the circuit 1 of the present invention. In the present embodiment, as shown in FIG. 1, four pairs of bidirectional buffers of a first buffer 2 and a second buffer 3 composed of bidirectional I / O buffers are used, and the first buffer 2 connected to the first buffer 2 is used. Description will be made assuming that a pair of the first electrode pad 4 and the second electrode pad 5 connected to the second buffer 3 is disposed at each of the four corners of the chip. On the substrate on which the chip is mounted, there is a lead terminal 6 for connecting the first electrode pad 4 connected to the first buffer 2 and the second electrode pad 5 connected to the second buffer 3 outside the chip. , Arranged at the four corners of the chip, respectively.

  FIG. 2 shows the configuration of the circuit 1 of the present invention. The first buffer 2 can fix the input level to a predetermined first level, here “L” (low voltage level, eg, ground voltage level). An input buffer with a pull-down function is provided. The second buffer 3 is configured to be capable of outputting at a second level different from the first level, here “H” (high voltage level, for example, power supply voltage level). The first level and the second level are not limited to the power supply voltage level and the ground voltage level, but can be any voltage level that can be determined as “H” or “L” of the input voltage and output voltage of each buffer. good.

  Next, the operation of the circuit 1 of the present invention will be described with reference to FIG. The circuit 1 of the present embodiment of the present embodiment is not a connection check by a tester but a confirmation at the software level.

  First, the operation of the circuit 1 of the present invention in the normal state will be described. In the normal state, the first buffer 2 with the pull-down function is set to the output mode, and the second buffer 3 with the input restriction function is set to the input mode.

  More specifically, in the normal state, the output control signal OEN2 of the first buffer 2 is set to “L” (ground voltage level), and the output buffer of the first buffer 2 is active. At this time, in this embodiment, “L” is set to the output signal O_Data2 output from the chip to the first electrode pad 4 via the output buffer. Further, the input signal I_Data2 becomes “L” because the output of the output signal O_Data2 is input via the input buffer. The pull-down control signal PDEN2 is “H” (power supply voltage level). Accordingly, in the normal state, the first buffer 2 outputs the output signal “L” from the first electrode pad 4, and the output signal “L” is input to the second buffer 3.

  In the normal state, the output control signal OEN1 is set to “H” and the output signal O_Data1 is set to “H”, but the second buffer 3 is not output from the output buffer of the second buffer 3. The input control signal PCTLA1 is set to “H”, and the input buffer is active. As described above, since the output signal “L” from the first buffer 2 is input to the second electrode pad 5, the input signal I_Data1 input from the second electrode pad 5 into the chip through the input buffer. Becomes “L” in response to the fact that PCTLA1 is active.

  In the present embodiment, since the first buffer 2 and the second buffer 3 are not used in the normal state, the output of the first buffer 2 is set in a floating state and the input of the second buffer 3 is fixed. It doesn't matter.

  Next, an operation when the inspection trigger signal is input will be described. When the inspection trigger signal is input, the first buffer 2 with the pull-down function is set to the input mode, and the second buffer 3 with the input restriction function is set to the output mode. The circuit 1 of the present invention receives the trigger signal for confirming the connection state of the chip, and then shifts to the test mode to detect the connection state of the chip. When the trigger signal is input, the second buffer 3 is switched to the output mode, and the first buffer 2 is switched to the input mode.

  Specifically, when the trigger signal is input, the second buffer 3 sets the output control signal OEN1 to “L”, activates the output buffer, and sets the output signal O_Data1 to “H”. As a result, “H” is output from the second electrode pad 5 of the second buffer 3 to the first buffer 2. In this embodiment, at this time, the input control signal PCTLA1 is set to “H”, and “H” is input to the input signal I_Data1.

  When the trigger signal is input, the first buffer 2 sets the output control signal OEN2 to “H” and shuts off the output of the output buffer. At this time, in this embodiment, the output signal O_Data2 is set to “L”. Further, the pull-down function control signal PDEN2 is set to “L” to enable the pull-down function.

  At this time, as described above, the output signal “H” is output from the second buffer 3, and if the second electrode pad 5 and the first electrode pad 4 are not peeled off, the second buffer 3 includes the second buffer 3. 3 is input, and the input signal I_Data of the first buffer 2 becomes “H”, which can be detected internally. On the other hand, if the second electrode pad 5 and the first electrode pad 4 are separated, the output signal from the second buffer 3 is not input to the first electrode pad 4, and the input of the first buffer 2 is Since it becomes Hi-Z (open), the pull-down function works and the input signal I_Data2 becomes “L”. That is, when the input signal I_Data2 of the first buffer 2 is “H”, it is determined that the chip and the film are not separated. When the input signal I_Data2 is “L”, the chip and the film are separated. Can be determined.

  In the present embodiment, the input signal I_Data2 of the first buffer 2 is further input to the status register 7, respectively. In the test mode, the input signal I_Data2 of the first buffer 2 is observed inside the chip, and the result is reflected in the status register 7. By referring to the status register 7 via the I / O pad 8, it can be determined whether or not the chip and the film are peeled off. As a result, when the result that the chip and the film are separated is stored in the status register 7, the operation of the LSI in which the chip and the film are separated is stopped. It becomes possible not to affect the circuit.

<Another embodiment>
Another embodiment of the circuit 1 of the present invention will be described.

  <1> In the above embodiment, the case where the first buffer 2 is a bidirectional buffer with a pull-down function has been described. However, the first buffer 2 may be a bidirectional buffer with a pull-up function. In this case, in the test mode, the output signal O_Data 1 of the second buffer 3 is set to “L”, and “L” is output from the second buffer 3 to the first buffer 2. Further, the pull-up control signal PDEN2 is set to “L” to enable the pull-up function. With this configuration, when the input signal I_Data2 of the first buffer 2 is “L”, it is determined that the chip and the film are not separated, and when the input signal I_Data2 is “H”, the chip and the film Can be determined to be peeled off.

  <2> In each of the above embodiments, the case where the circuit of the present invention is installed at the four corners of the chip has been described. However, it is also a preferred embodiment that the circuit is installed at the periphery of the chip.

  <3> In each of the above embodiments, the case where the circuit of the present invention is configured by two bidirectional buffers has been described. However, the present invention is not limited to this. The first buffer 2 may be a buffer including at least an input buffer that can fix the input level to a predetermined first level. Further, the second buffer 3 may be a buffer having at least an output buffer that can output with a second level different from the first level.

1 is a schematic configuration diagram showing a schematic configuration of a semiconductor memory device equipped with a detection circuit according to the present invention. The circuit diagram which shows the example of 1 structure of the detection circuit based on this invention Timing chart showing operation of detection circuit according to the present invention

Explanation of symbols

1: circuit of the present invention 2: first buffer 3: second buffer 4: first electrode pad 5: second electrode pad 6: lead terminal 7: status register 8: I / O buffer

Claims (6)

In a semiconductor device in which the chip is supported by electrically connecting an electrode pad on a semiconductor integrated circuit chip and a lead terminal of the package, the detection circuit detects that the chip peels from the package,
A first buffer having at least an input buffer capable of fixing an input level to a predetermined first level; a second buffer having at least an output buffer capable of outputting an output level at a second level different from the first level; A first electrode pad connected to the input terminal of the first buffer; and a second electrode pad connected to the output terminal of the second buffer;
In a state where the first electrode pad and the second electrode pad are connected outside the chip via the lead terminal, the second buffer outputs the second level when an inspection trigger signal is input, and the first buffer Configured to determine that the buffer is normal when detecting the second level input, and to determine that the buffer is abnormal when the first buffer detects the first level input ;
2. A detection circuit according to claim 1, wherein a pair of the first electrode pad and the second electrode pad is disposed at each of four corners of the chip . 2. The detection circuit according to claim 1, wherein the first electrode pad and the second electrode pad are disposed in a peripheral portion of the chip. The first buffer, the detection circuit according to claim 1 or 2, characterized in that the input terminal is a bidirectional buffer with a pull-up or pull-down mechanism. The second buffer, the detection circuit according to any one of claim 1 to 3, characterized in that a bidirectional buffer with the input control function. The status register capable of storing verification result data inside the chip is provided, and the verification result data of the status register is configured to be readable from the outside. 5 . Detection circuit. Characterized by claim comprising a detecting circuit according to any one of claim 1 to 5, and the first electrode pad and the second electrode pads are connected through the lead terminals of the package by the off-chip A semiconductor device.