JP4729348B2 - Manufacturing method of semiconductor integrated circuit device - Google Patents

Description

  The present invention relates to a technology for manufacturing a semiconductor integrated circuit device, and more particularly to a technology effective when applied to an electrical inspection of a semiconductor integrated circuit performed by pressing a probe of a probe card against an electrode pad of the semiconductor integrated circuit device. is there.

Japanese Unexamined Patent Publication No. 7-283280 (Patent Document 1), Japanese Unexamined Patent Publication No. 8-50146 (Patent Document 2 (corresponding PCT International Publication WO95-34000)), Japanese Unexamined Patent Publication No. 8-2014427 (Patent Document 3). JP-A-10-308423 (Patent Document 4), JP-A-11-23615 (Patent Document 5 (corresponding US Patent Publication USP 6,305,230)), JP-A-11-97471 (Patent) Document 6 (Corresponding European Patent Publication EP1022775)), Japanese Unexamined Patent Publication No. 2000-150594 (Patent Document 7 (Corresponding European Patent Publication EP099451)), and Japanese Unexamined Patent Publication No. 2001-159543 (Patent Document 8) include semiconductors It has a probe (contact terminal), insulating film, and lead-out wiring formed using integrated circuit device manufacturing technology Prober structure, its manufacturing method, the test pad and technology that enables the implementation of probe testing is disclosed by using the prober against narrow pitch chips.
JP-A-7-283280 JP-A-8-50146 JP-A-8-201427 JP-A-10-308423 Japanese Patent Laid-Open No. 11-23615 Japanese Patent Laid-Open No. 11-97471 JP 2000-150594 A JP 2001-159634 A

  There is a probe inspection as an inspection technique for a semiconductor integrated circuit device. This probe inspection includes a function test for confirming whether or not the device operates according to a predetermined function, a test for determining a non-defective product / defective product by performing a DC operation characteristic and an AC operation characteristic test, and the like. In probe inspection, probe inspection is performed in the wafer state in response to demands for wafer shipment (quality differentiation), KGD (Known Good Die) support (MCP (Multi-Chip Package) yield improvement), and total cost reduction. Technology to do is used.

  In recent years, semiconductor integrated circuit devices have become more multifunctional, and it has been promoted to create a plurality of circuits on one semiconductor chip (hereinafter simply referred to as a chip). Further, in order to reduce the manufacturing cost of the semiconductor integrated circuit device, the semiconductor element and the wiring are miniaturized to reduce the area of the semiconductor chip (hereinafter simply referred to as a chip), and the semiconductor wafer (hereinafter simply referred to as the wafer). Increasing the number of chips acquired per sheet is underway. Therefore, not only the number of test pads (bonding pads) is increased, but also the arrangement of test pads is narrowed and the area of the test pads is also reduced. When a prober having a cantilever-like probe is used for the probe inspection as the pitch of the test pad is reduced, it is difficult to install the probe in accordance with the position of the test pad. There is a problem that becomes.

  The present inventors have studied a technique that can realize a probe inspection even for a chip having a narrow test pad pitch by using a prober having a probe formed by using a manufacturing technique of a semiconductor integrated circuit device. ing. Among them, the present inventors have found the following problems.

  That is, the probe is a part of a thin film probe formed by depositing a metal film and a polyimide film using a manufacturing technique of a semiconductor integrated circuit device, patterning them, and the like, and is an inspection object. It is provided on the main surface side of the thin film probe facing the chip. In probe inspection using such a thin film probe, since high-speed processing of the probe inspection is required, it is a problem to improve the electrical characteristics of the thin film probe.

  An object of one typical invention disclosed in the present application is to provide a technique capable of improving the electrical characteristics of a thin film probe having a probe formed by a manufacturing technique of a semiconductor integrated circuit device.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

1. A method for manufacturing a semiconductor integrated circuit device according to the present invention includes the following steps.
(A) Partitioned into a plurality of chip regions, a semiconductor integrated circuit is formed in each of the plurality of chip regions, and a plurality of first electrodes electrically connected to the semiconductor integrated circuit are formed on the main surface Preparing a semiconductor wafer;
(B) A first wiring board on which a plurality of first wirings are formed, a plurality of contact terminals for contacting the plurality of first electrodes, and a plurality of second wirings electrically connected to the plurality of contact terminals. And one or more fifth wirings arranged around the plurality of second wirings and electrically connected to a reference potential are formed, and the plurality of second wirings and the fifth wiring are the plurality of second wirings. A first sheet that is electrically connected to one wiring and that has tips of the plurality of contact terminals held on the first wiring board so as to face the main surface of the semiconductor wafer; and the plurality of the first sheets A step of preparing a first card having a pressing mechanism for pressing the region where the contact terminals are formed from the back surface;
(C) A step of performing electrical inspection of the semiconductor integrated circuit by bringing the tips of the plurality of contact terminals into contact with the plurality of first electrodes.

2. The method for manufacturing a semiconductor integrated circuit device according to the present invention includes the following steps.
(A) Partitioned into a plurality of chip regions, a semiconductor integrated circuit is formed in each of the plurality of chip regions, and a plurality of first electrodes electrically connected to the semiconductor integrated circuit are formed on the main surface Preparing a semiconductor wafer;
(B) A first wiring board on which a plurality of first wirings are formed, a plurality of contact terminals for contacting the plurality of first electrodes, and a plurality of second wirings electrically connected to the plurality of contact terminals. The plurality of second wirings are electrically connected to the plurality of first wirings, and the tips of the plurality of contact terminals are held on the first wiring substrate so as to face the main surface of the semiconductor wafer. Preparing a first card having the first sheet and a pressing mechanism that presses the region of the first sheet where the plurality of contact terminals are formed from the back surface;
(C) A step of performing electrical inspection of the semiconductor integrated circuit by bringing the tips of the plurality of contact terminals into contact with the plurality of first electrodes.

Here, among the plurality of second wirings, the plurality of third wirings having the same power source are connected and integrated with each other at a second position in the extending direction from the first position connected to the contact terminal. Pattern.

3. The method for manufacturing a semiconductor integrated circuit device according to the present invention includes the following steps.
(A) Partitioned into a plurality of chip regions, a semiconductor integrated circuit is formed in each of the plurality of chip regions, and a plurality of first electrodes electrically connected to the semiconductor integrated circuit are formed on the main surface Preparing a semiconductor wafer;
(B) A first wiring board on which a plurality of first wirings are formed, a plurality of contact terminals for contacting the plurality of first electrodes, and a plurality of second wirings electrically connected to the plurality of contact terminals. The plurality of second wirings are electrically connected to the plurality of first wirings, and the tips of the plurality of contact terminals are held on the first wiring substrate so as to face the main surface of the semiconductor wafer. Preparing a first card having the first sheet and a pressing mechanism that presses the region of the first sheet where the plurality of contact terminals are formed from the back surface;
(C) A step of performing electrical inspection of the semiconductor integrated circuit by bringing the tips of the plurality of contact terminals into contact with the plurality of first electrodes.

Here, among the plurality of second wirings, a plurality of fourth wirings same electrical signal is transmitted, connected together and integrated at a second location on the extending direction from the first position to be connected to the contact terminal It has a converted pattern.

4). The method for manufacturing a semiconductor integrated circuit device according to the present invention includes the following steps.
(A) Partitioned into a plurality of chip regions, a semiconductor integrated circuit is formed in each of the plurality of chip regions, and a plurality of first electrodes electrically connected to the semiconductor integrated circuit are formed on the main surface Preparing a semiconductor wafer;
(B) A first wiring board on which a plurality of first wirings are formed, a plurality of contact terminals for contacting the plurality of first electrodes, and a plurality of second wirings electrically connected to the plurality of contact terminals. The plurality of second wirings are electrically connected to the plurality of first wirings, and the tips of the plurality of contact terminals are held on the first wiring substrate so as to face the main surface of the semiconductor wafer. Preparing a first card having the first sheet and a pressing mechanism that presses the region of the first sheet where the plurality of contact terminals are formed from the back surface;
(C) A step of performing electrical inspection of the semiconductor integrated circuit by bringing the tips of the plurality of contact terminals into contact with the plurality of first electrodes.

Here, the plurality of second wirings are formed of a plurality of wiring layers,
The plurality of second wirings include a plurality of third wirings for supplying power and a plurality of fourth wirings for signal transmission,
The plurality of third wirings are formed in a first wiring layer,
The plurality of fourth wirings are formed in a second wiring layer different from the first wiring layer.

5. The method for manufacturing a semiconductor integrated circuit device according to the present invention includes the following steps.
(A) Partitioned into a plurality of chip regions, a semiconductor integrated circuit is formed in each of the plurality of chip regions, and a plurality of first electrodes electrically connected to the semiconductor integrated circuit are formed on the main surface Preparing a semiconductor wafer;
(B) A first wiring board on which a plurality of first wirings are formed, a plurality of contact terminals for contacting the plurality of first electrodes, and a plurality of second wirings electrically connected to the plurality of contact terminals. The plurality of second wirings are electrically connected to the plurality of first wirings, and the tips of the plurality of contact terminals are held on the first wiring substrate so as to face the main surface of the semiconductor wafer. Preparing a first card having the first sheet and a pressing mechanism that presses the region of the first sheet where the plurality of contact terminals are formed from the back surface;
(C) A step of performing electrical inspection of the semiconductor integrated circuit by bringing the tips of the plurality of contact terminals into contact with the plurality of first electrodes.

Here, the plurality of second wirings include a plurality of third wirings for supplying power,
One said 3rd wiring is electrically connected with the 2 or more said 1st wiring whose power supply is the same system | strain.

  Further, other outlines disclosed in the present application will be briefly described as follows.

Item 1. A first wiring board on which a plurality of first wirings are formed;
A plurality of contact terminals for contacting a plurality of first electrodes formed on the main surface of the semiconductor wafer and a plurality of second wirings electrically connected to the plurality of contact terminals are formed, and the plurality of second wirings One or more fifth wirings arranged around and electrically connected to a reference potential are formed, and the plurality of second wirings and the fifth wiring are electrically connected to the plurality of first wirings, A first sheet held on the first wiring board with tips of a plurality of contact terminals facing the main surface of the semiconductor wafer;
The probe card which has a pressing mechanism which presses the area | region in which the said several contact terminal was formed among the said 1st sheets from the back surface.

Item 2. In the probe card according to Item 1,
The fifth wiring is formed of the same wiring layer as the second wiring.

Item 3. In the probe card according to Item 1,
The reference potential is a ground potential.

Item 4. In the probe card according to Item 1,
The semiconductor wafer is partitioned into a plurality of chip regions, a semiconductor integrated circuit is formed in each of the plurality of chip regions, and the plurality of first electrodes electrically connected to the semiconductor integrated circuit on a main surface Formed,
When electrical inspection of the semiconductor integrated circuit is performed by bringing the tips of the plurality of contact terminals into contact with the plurality of first electrodes, an electrical signal is transmitted to the plurality of second wirings.

Item 5. In the probe card according to Item 4,
The semiconductor integrated circuit operates at a high frequency.

Item 6. A first wiring board on which a plurality of first wirings are formed;
A plurality of contact terminals for contacting a plurality of first electrodes formed on the main surface of the semiconductor wafer and a plurality of second wirings electrically connected to the plurality of contact terminals are formed, and the plurality of second wirings Electrically connected to the plurality of first wirings, and a first sheet held on the first wiring substrate with tips of the plurality of contact terminals facing the main surface of the semiconductor wafer;
A pressing mechanism that presses the region of the first sheet where the plurality of contact terminals are formed from the back surface;
Among the plurality of second wirings, a plurality of third wirings having the same power source are connected and integrated with each other at a second position in the extending direction from the first position connected to the contact terminal. Having probe card.

Item 7. In the probe card according to Item 6,
The third wiring at the second position has a relatively larger width than the first position.

Item 8. In the probe card according to Item 6,
The semiconductor wafer is partitioned into a plurality of chip regions, a semiconductor integrated circuit is formed in each of the plurality of chip regions, and the plurality of first electrodes electrically connected to the semiconductor integrated circuit on a main surface Formed,
The semiconductor integrated circuit operates at a high frequency.

Item 9. A first wiring board on which a plurality of first wirings are formed;
A plurality of contact terminals for contacting a plurality of first electrodes formed on the main surface of the semiconductor wafer and a plurality of second wirings electrically connected to the plurality of contact terminals are formed, and the plurality of second wirings Electrically connected to the plurality of first wirings, and a first sheet held on the first wiring substrate with tips of the plurality of contact terminals facing the main surface of the semiconductor wafer;
A pressing mechanism that presses the region of the first sheet where the plurality of contact terminals are formed from the back surface;
Wherein among the plurality of second wirings, a plurality of fourth wirings same electrical signal is transmitted, the pattern connected and integrated with each other at a second position on the extending direction from the first position to be connected to the contact terminal A probe card.

Item 10. Item 9. The probe card according to Item 9,
The fourth wiring in the second position has a relatively larger width than the first position.

Item 11. Item 10. The probe card according to Item 10,
The semiconductor wafer is partitioned into a plurality of chip regions, a semiconductor integrated circuit is formed in each of the plurality of chip regions, and the plurality of first electrodes electrically connected to the semiconductor integrated circuit on a main surface Formed,
When performing electrical inspection of the semiconductor integrated circuit by bringing the tips of the plurality of contact terminals into contact with the plurality of first electrodes, the plurality of contact terminals are arranged in two chip regions. In contact with the first electrode.

Item 12. Item 9. The probe card according to Item 9,
Around the fourth wiring, one or more fifth wirings that are electrically connected to a reference potential are formed.

Item 13. Item 12. The probe card according to Item 12,
The reference potential is a ground potential.

Item 14. Item 9. The probe card according to Item 9,
The semiconductor wafer is partitioned into a plurality of chip regions, a semiconductor integrated circuit is formed in each of the plurality of chip regions, and the plurality of first electrodes electrically connected to the semiconductor integrated circuit on a main surface Formed,
The semiconductor integrated circuit operates at a high frequency.

Item 15. A first wiring board on which a plurality of first wirings are formed;
A plurality of contact terminals for contacting a plurality of first electrodes formed on the main surface of the semiconductor wafer and a plurality of second wirings electrically connected to the plurality of contact terminals are formed, and the plurality of second wirings Electrically connected to the plurality of first wirings, and a first sheet held on the first wiring substrate with tips of the plurality of contact terminals facing the main surface of the semiconductor wafer;
A pressing mechanism that presses the region of the first sheet where the plurality of contact terminals are formed from the back surface;
The plurality of second wirings are formed of a plurality of wiring layers,
The plurality of second wirings include a plurality of third wirings for supplying power and a plurality of fourth wirings for signal transmission,
The plurality of third wirings are formed in a first wiring layer,
The plurality of fourth wirings are probe cards formed in a second wiring layer different from the first wiring layer.

Item 16. Item 15. The probe card according to Item 15,
The semiconductor wafer is partitioned into a plurality of chip regions, a semiconductor integrated circuit is formed in each of the plurality of chip regions, and the plurality of first electrodes electrically connected to the semiconductor integrated circuit on a main surface Formed,
When performing electrical inspection of the semiconductor integrated circuit by bringing the tips of the plurality of contact terminals into contact with the plurality of first electrodes, the plurality of contact terminals are arranged in two chip regions. In contact with the first electrode.

Item 17. Item 15. The probe card according to Item 15,
Among the plurality of third wirings, those having the same power source have a pattern that is connected and integrated with each other at a second position in the extending direction from the first position connected to the contact terminal.

Item 18. Item 17. The probe card according to Item 17,
The third wiring at the second position has a relatively larger width than the first position.

Item 19. Item 15. The probe card according to Item 15,
Among the plurality of fourth wirings, the same electrical signal is transmitted, and has a pattern that is connected and integrated with each other at a second position in the extending direction from the first position connected to the contact terminal.

Item 20. Item 19. The probe card according to Item 19,
The fourth wiring in the second position has a relatively larger width than the first position.

Item 21. Item 15. The probe card according to Item 15,
The plurality of third wirings include one or more fifth wirings that are electrically connected to a reference potential.

Item 22. Item 21. The probe card according to Item 21,
The reference potential is a ground potential.

Item 23. Item 15. The probe card according to Item 15,
The semiconductor wafer is partitioned into a plurality of chip regions, a semiconductor integrated circuit is formed in each of the plurality of chip regions, and the plurality of first electrodes electrically connected to the semiconductor integrated circuit on a main surface Formed,
The semiconductor integrated circuit operates at a high frequency.

Item 24. A first wiring board on which a plurality of first wirings are formed;
A plurality of contact terminals for contacting a plurality of first electrodes formed on the main surface of the semiconductor wafer and a plurality of second wirings electrically connected to the plurality of contact terminals are formed, and the plurality of second wirings Electrically connected to the plurality of first wirings, and a first sheet held on the first wiring substrate with tips of the plurality of contact terminals facing the main surface of the semiconductor wafer;
A pressing mechanism that presses the region of the first sheet where the plurality of contact terminals are formed from the back surface;
The plurality of second wirings include a plurality of third wirings for supplying power,
One said 3rd wiring is a probe card electrically connected with two or more said 1st wirings from which the power supply is the same system | strain.

Item 25. Item 24. The probe card according to Item 24,
Among the plurality of third wirings, those having the same power source have a pattern that is connected and integrated with each other at a second position in the extending direction from the first position connected to the contact terminal.

Item 26. Item 25. The probe card according to Item 25,
The third wiring at the second position has a relatively larger width than the first position.

Item 27. Item 24. The probe card according to Item 24,
The plurality of third wirings include one or more fifth wirings that are electrically connected to a reference potential.

Item 28. Item 27. The probe card according to Item 27,
The reference potential is a ground potential.

Item 29. Item 24. The probe card according to Item 24,
The semiconductor wafer is partitioned into a plurality of chip regions, a semiconductor integrated circuit is formed in each of the plurality of chip regions, and the plurality of first electrodes electrically connected to the semiconductor integrated circuit on a main surface Formed,
The semiconductor integrated circuit operates at a high frequency.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  In other words, the electrical characteristics of the thin film probe having the probe formed by the manufacturing technology of the semiconductor integrated circuit device can be improved.

  Before describing the present invention in detail, the meaning of terms in the present application will be described as follows.

  A wafer is a single crystal silicon substrate (generally a substantially planar circular shape) used in the manufacture of integrated circuits, an SOI (Silicon On Insulator) substrate, a sapphire substrate, a glass substrate, other insulating, anti-insulating or semiconductor substrates, and their composites. A special substrate. The term “semiconductor integrated circuit device” as used herein refers not only to a semiconductor integrated circuit device such as a silicon wafer or a sapphire substrate, but also to a TFT (Thin Film Transistor) unless otherwise specified. ) And STN (Super-Twisted-Nematic) liquid crystal or the like made on other insulating substrates such as glass.

  The device surface is a main surface of a wafer on which a device pattern corresponding to a plurality of chip regions is formed by lithography.

  A contact terminal or probe is a wafer process similar to that used for manufacturing a semiconductor integrated circuit, that is, a patterning technique that combines photolithography technology, CVD (Chemical Vapor Deposition) technology, sputtering technology, and etching technology. The wiring layer and the tip part electrically connected thereto are integrally formed.

  The thin film probe, the thin film probe card, or the protruding needle wiring sheet composite is provided with the contact terminal (protruding needle) that comes into contact with the object to be inspected and the wiring drawn from the contact terminal. A thin film on which a contact electrode is formed, for example, a thickness of about 10 μm to 100 μm.

  A probe card refers to a structure having contact terminals and a multilayer wiring board that come into contact with a wafer to be inspected. A prober or a semiconductor inspection apparatus refers to a wafer stage on which a frog ring, a probe card and a wafer to be inspected are placed. An inspection apparatus having a sample support system including

  The probe inspection is an electrical test performed with a prober on a wafer for which a wafer process has been completed. The semiconductor integrated circuit is configured by applying the tip of the contact terminal to an electrode formed on the main surface of the chip region. In other words, a non-defective product / defective product is discriminated by performing a function test for confirming whether or not the device operates in accordance with a predetermined function and a DC operation characteristic and an AC operation characteristic test. This is distinguished from a screening test (final test) that is performed after dividing into chips (or after packaging is completed).

  A POGO pin or a spring probe has a structure in which a contact pin (plunger (contact needle)) is pressed against an electrode (terminal) by the elastic force of a spring (coil spring). The contact needle is adapted to make an electrical connection. For example, a spring arranged in a metal tube (holding member) transmits an elastic force to the contact pin via a metal ball.

  A tester (Test System) is for electrically inspecting a semiconductor integrated circuit and generates a signal such as a predetermined voltage and a reference timing.

  The tester head is electrically connected to the tester, receives the voltage and signal transmitted from the tester, generates a signal such as voltage and detailed timing to the semiconductor integrated circuit, and sends it to the probe card via a pogo pin or the like. The one that sends a signal.

  The frog ring is a device that is electrically connected to a tester head and a probe card via a pogo pin or the like, and sends a signal sent from the tester head to a probe card to be described later.

  A jumper wire is a wire formed by covering the periphery of a conductor wire such as copper with an insulating material, for example. In a two-dimensional (planar) pattern of a circuit, the wire must be crossed so as not to be electrically connected. It is used where it must be.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say.

  Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Also, components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted.

  Further, in all the drawings for explaining the present embodiment, hatching may be given even in a plan view for easy understanding of the configuration of each member.

  Further, the details of the thin film probe by the semiconductor lithography technique used in the present application are disclosed in the following patent application by the present inventor and related inventors, and therefore, the contents thereof are repeated unless particularly necessary. Absent. Japanese Patent Application No. 6-22885, Japanese Patent Application Laid-Open No. 7-283280, Japanese Patent Application Laid-Open No. 8-50146, Japanese Patent Application Laid-Open No. 8-201427, Japanese Patent Application No. 9-119107. Japanese Unexamined Patent Publication No. 11-23615, Japanese Unexamined Patent Publication No. 2002-139554, Japanese Unexamined Patent Publication No. 10-308423, Japanese Patent Application No. 9-189660, Japanese Unexamined Patent Publication No. 11-97471, Japanese Unexamined Patent Publication 2000. -150594, Japanese Patent Application Laid-Open No. 2001-159543, Japanese Patent Application No. 2002-289377 (corresponding US Application No. 10 / 6676,609; US Application Date 2003.10.2), Japanese Patent Application Laid-Open No. 2004-2004. No. 132699, Japanese Unexamined Patent Publication No. 2005-24377, Japanese Unexamined Patent Publication No. 2004-288672 (corresponding to US No. 10 / 765,917; U.S. application date 2004.1.29), Japanese Unexamined Patent Publication No. 2004-144742 (corresponding U.S. Publication No. 2004 / 070,413), Japanese Unexamined Patent Publication No. 2004-157127, Japanese Unexamined Patent Publication No. 2004-144742 (corresponding US Publication No. 2004 / 070,413), Japanese Unexamined Patent Publication No. 2004-157127, Japanese Patent Application No. 2003-371515 (corresponding US Application No. 10 / 968,215). No .; US application date 2004.10.20), Japanese Patent Application No. 2003-372323 (corresponding US Application No. 10 / 968,431; US Application Date 2004.10.20), Japanese Patent Application No. 2004-1105048 PCT application number PCT / JP2004 / 17160, PCT application number PCT / JP200 / No. 4344, Japanese Patent Application No. 2004-378504, Japanese Patent Application No. 2005-109350, a and Japanese Patent Application No. 2005-168112 Japanese Patent Application No. 2005-181085.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
FIG. 1 is a cross-sectional view of a main part of the probe card (first card) of the first embodiment. As shown in FIG. 1, the probe card of the first embodiment includes a multilayer wiring board (first wiring board) 1, a thin film sheet (first sheet) 2, a tester head THD, a frog ring FGR, a card holder CHD, and the like. Is formed. The tester head THD and the frog ring FGR, and the frog ring FGR and the multilayer wiring board 1 are electrically connected via a plurality of pogo pins PGP, respectively, whereby the tester head THD and the multilayer wiring board 1 are connected. Is electrically connected. The card holder CHD mechanically connects the multilayer wiring board 1 to the prober, and has mechanical strength that prevents the multilayer wiring board 1 from being warped by the pressure from the pogo pins PGP.

  FIG. 2 is a plan view of the main part of the lower surface of the probe card of the present embodiment, and FIG. 3 is a cross-sectional view taken along the line AA in FIG.

  As shown in FIGS. 2 and 3, the probe card of the present embodiment includes, for example, a plunger 3 in addition to the members shown in FIG. The thin film sheet 2 is fixed to the lower surface of the multilayer wiring board 1 by a pressing ring 4, and the plunger 3 is attached to the upper surface of the multilayer wiring board 1. An opening 5 is provided at the center of the multilayer wiring board 1, and the thin film sheet 2 and the plunger 3 are bonded to each other through an adhesive ring 6 in the opening 5.

  On the lower surface of the thin film sheet 2, for example, a plurality of probes (contact terminals) 7 having a quadrangular pyramid shape or a quadrangular pyramid shape are formed. In the thin film sheet 2, a plurality of wirings (second wirings) that are electrically connected to each of the probes 7 and extend from each probe 7 to the probe portion of the thin film sheet 2 are formed. A plurality of receiving portions (not shown) that are in electrical contact with the ends of the plurality of wirings are formed on the lower surface or the upper surface of the multilayer wiring substrate 1, respectively. 1 is electrically connected to a plurality of pogo (POGO) seats 8 provided on the upper surface of the multilayer wiring board 1 through wirings (first wirings) formed in the wiring board 1. The pogo seat 8 has a function of receiving a pin for introducing a signal from the tester to the probe card.

  In the first embodiment, the thin film sheet 2 is formed of a thin film mainly composed of polyimide, for example. Since such a thin film sheet 2 has flexibility, in the first embodiment, in order to bring all the probes 7 into contact with pads of a chip (semiconductor integrated circuit device), a thin film in a region where the probes 7 are formed. The plunger 3 is configured to press the sheet 2 from the upper surface (back surface) via a pressing tool (pressing mechanism) 9. That is, a constant pressure is applied to the pressing tool 9 by the elastic force of the spring 3 </ b> A disposed in the plunger 3. In the present embodiment, 42 alloy can be exemplified as the material of the pressing tool 9.

  Here, when the number of test pads (bonding pads) formed on the chip surface to be inspected increases, the number of pogo pins PGP for sending signals to the respective test pads increases accordingly. Further, as the number of pogo pins PGP increases, the pressure from the pogo pins PGP applied to the multilayer wiring board 1 also increases, so that the card holder CHD needs to be thickened to prevent the multilayer wiring board 1 from warping. Further, in order to ensure that each probe 7 formed on the thin film sheet 2 is brought into contact with the corresponding test pad, the central area IA (see FIG. 3) of the thin film sheet 2 and the central area IA on the outer peripheral side with the adhesive ring as a boundary. In the case of a structure in which tension is applied to each of the surrounding outer peripheral areas OA (see FIG. 3), there is a limit on the height HT (see FIG. 1) from the surface of the multilayer wiring board 1 to the probe surface of the thin film sheet 2. If the thickness of the card holder CHD becomes larger than the limit value of the height HT, the thin film sheet 2 will be buried in the card holder CHD, and the probe 7 is surely brought into contact with the test pad. There is a concern that it will not be possible.

  Therefore, in the first embodiment, the thin film sheet 2 and the adhesive ring 6 are bonded in a state where tension is applied only to the central region IA of the thin film sheet 2, and no tension is applied to the outer peripheral region OA. At this time, as a material of the adhesive ring 6, a metal having a thermal expansion coefficient similar to that of Si (silicon) (for example, 42 alloy) is selected, and as an adhesive for bonding the thin film sheet 2 and the adhesive ring 6, The use of an epoxy adhesive can be exemplified. Thereby, since the height of the adhesive ring 6 that defines the height HT to the probe surface of the thin film sheet 2 can be increased, the height HT is also increased, and the thin film sheet 2 is buried in the card holder CHD. It is possible to avoid malfunctions that occur. That is, even when the card holder CHD becomes thick, the probe 7 can be reliably brought into contact with the test pad.

  Instead of using the above means, as shown in FIG. 4, the surface of the multilayer wiring board 1 is structured such that the auxiliary board SB is attached to the center of the multilayer wiring board 1 and the thin film sheet 2 is attached to the auxiliary board SB. The height HT from the thin film sheet 2 to the probe surface may be improved. Similar to the multilayer wiring substrate 1, a plurality of wirings are formed in the auxiliary substrate SB, and a plurality of receiving portions (not shown) that are in electrical contact with the ends of these wirings are formed. Corresponding portions of the receiving portion provided on the multilayer wiring board 1 and the receiving portion provided on the auxiliary substrate SB are electrically connected to each other by solder, for example. Instead of using solder, means for pressure-bonding the multilayer wiring board 1 and the auxiliary board SB via an anisotropic conductive rubber, or electrically connecting the receiving portion to the respective surfaces of the multilayer wiring board 1 and the auxiliary board SB A means for forming a protrusion made of Cu (copper) plating and crimping the corresponding protrusions may be used.

  In the first embodiment, as an object to be subjected to probe inspection (electrical inspection) using the probe card, a chip on which an LCD (Liquid Crystal Display) driver is formed can be exemplified. FIG. 5 is a plan view of the wafer WH in which the plurality of chips (chip regions) 10 are partitioned. The probe inspection using the probe card of the first embodiment is performed on the wafer WH in which the plurality of chips 10 are partitioned. FIG. 6 shows a plan view of the chip 10 and an enlarged view of a part thereof. The chip 10 is made of, for example, a single crystal silicon substrate, and an LCD driver circuit is formed on the main surface thereof. In addition, a large number of pads (test pads (first electrodes)) 11 and 12 that are electrically connected to the LCD driver circuit are arranged on the periphery of the main surface of the chip 10. Pads 11 arranged along the upper long side and both short sides serve as output terminals, and pads 12 arranged along the lower long side of chip 10 serve as input terminals. Since the number of output terminals of the LCD driver is larger than the number of input terminals, the pads 11 are arranged in two rows along the upper long side and both short sides of the chip 10 in order to widen the interval between adjacent pads 11 as much as possible. The pads 11 in the respective rows are arranged alternately along the upper long side and both short sides of the chip 10. In the first embodiment, the pitch LP at which the adjacent pads 11 are arranged is, for example, about 68 μm. Further, in the first embodiment, the pad 11 is a planar rectangle, the length LA of the long side extending in the direction intersecting (orthogonal) with the outer periphery of the chip 10 is about 63 μm, and along the outer periphery of the chip 10. The length LB of the short side that extends is about 34 μm. Further, since the pitch LP where the adjacent pads 11 are arranged is about 68 μm and the length LB of the short side of the pads 11 is about 34 μm, the interval between the adjacent pads 11 is about 34 μm.

  The pads 11 and 12 are bump electrodes (projection electrodes) formed of, for example, Au (gold), and a method such as electrolytic plating, electroless plating, vapor deposition, or sputtering on the input / output terminals (bonding pads) of the chip 10. It is formed by. FIG. 7 is a perspective view of the pad 11. The height LC of the pad 11 is about 15 μm, and the pad 12 has the same height.

  Further, the chip 10 forms an LCD driver circuit (semiconductor integrated circuit) and input / output terminals (bonding pads) using a semiconductor manufacturing technique in a large number of chip regions partitioned on the main surface of the wafer, and then inputs / output terminals. After the pads 11 and 12 are formed by the above method, the wafer can be diced to divide the chip region into pieces. In the first embodiment, the probe inspection is performed on each chip area before dicing the wafer. In the following description of the probe inspection (the step in which the pads 11 and 12 and the probe 7 are in contact), unless otherwise specified, the chip 10 indicates each chip area before dicing the wafer.

  FIG. 8 is a cross-sectional view of a principal part showing a method for connecting the chip 10 to the liquid crystal panel. As shown in FIG. 8, the liquid crystal panel is disposed so as to face the glass substrate 16 through the glass substrate 16, the liquid crystal layer 17, and the liquid crystal layer 17 having the pixel electrodes 14 and 15 formed on the main surface, for example. It is formed from a glass substrate 18 or the like. In the first embodiment, the chip 10 is face-down bonded to the pixel electrodes 14 and 15 of the glass substrate 16 of the liquid crystal panel so that the pads 11 and 12 are connected to the chip 10, respectively. The connection to can be illustrated.

  FIG. 9 is an enlarged plan view of a main part showing a part of the area on the lower surface of the thin film sheet 2 where the probe 7 is formed, and FIG. 10 is a cross-sectional view of the main part along the line BB in FIG. FIG. 11 is a cross-sectional view of an essential part taken along line CC in FIG.

  The probe 7 is a part of the metal films 21A and 21B patterned into a planar hexagonal shape in the thin film sheet 2, and a tetragonal pyramid or a quadrangular pyramid trapezoid is formed on the lower surface of the thin film sheet 2 of the metal films 21A and 21B. It is the part that pops out into the mold. The probes 7 are arranged on the main surface of the thin film sheet 2 in accordance with the positions of the pads 11 and 12 formed on the chip 10, and FIG. 9 shows the arrangement of the probes 7 corresponding to the pads 11. Among these probes 7, the probe 7 </ b> A corresponds to the pad 11 in an array (hereinafter referred to as the first row) that is relatively close to the outer periphery of the chip 10 among the pads 11 arranged in two rows, and the probe 7 </ b> B is Of the pads 11 arranged in two rows, the pads 11 correspond to the pads 11 that are relatively far from the outer periphery of the chip 10 (hereinafter referred to as the second row). Further, the distance between the probe 7A and the probe 7B present at the closest position is defined by the distance LX in the left-right direction and the distance LY in the up-down direction on the paper surface illustrated in FIG. This is about 34 μm, which is half of the pitch LP where the matching pads 11 are arranged. In the first embodiment, the distance LY is about 93 μm.

  The metal films 21A and 21B are formed, for example, by sequentially laminating a rhodium film and a nickel film from the lower layer. A polyimide film 22 is formed on the metal films 21A and 21B, and wirings (second wirings) 23 that are electrically connected to the metal films 21A and 21B are formed on the polyimide film 22. The wiring 23 is in contact with the metal films 21 </ b> A and 21 </ b> B at the bottom of the through hole 24 formed in the polyimide film 22. A polyimide film 25 is formed on the polyimide film 22 and the wiring 23.

  As described above, a part of the metal films 21A and 21B becomes the probes 7A and 7B formed in a quadrangular pyramid shape or a quadrangular pyramid trapezoidal shape, and a through hole 24 reaching the metal films 21A and 21B is formed in the polyimide film 22. The Therefore, if the planar pattern of the metal film 21A and the through hole 24 in which the probe 7A is formed and the planar pattern of the metal film 21B and the through hole 24 in which the probe 7B is formed are arranged in the same direction, they are adjacent to each other. There is a concern that the metal film 21A and the metal film 21B come into contact with each other, so that independent input / output cannot be obtained from the probes 7A and 7B. Therefore, in the first embodiment, as shown in FIG. 9, the planar pattern of the metal film 21B and the through hole 24 in which the probe 7B is formed is the planar pattern of the metal film 21A and the through hole 24 in which the probe 7A is formed. Is a pattern rotated by 180 °. Thereby, a wide area of the metal film 21A in which the probe 7A and the through hole 24 are arranged in a plane and a wide area of the metal film 21B in which the probe 7B and the through hole 24 are arranged in a plane are left and right in the drawing. Are not arranged on the straight line, and the planarly tapered regions of the metal film 21A and the metal film 21B are arranged on the straight line in the left-right direction on the paper surface. As a result, it is possible to prevent a problem that the adjacent metal film 21A and the metal film 21B come into contact with each other. Even if the pads 11 (see FIG. 6) are arranged at a narrow pitch, the probes 7A and 7B can be arranged at positions corresponding to the pads 11 (see FIG. 6).

  In the present embodiment, the case where the pads 11 are arranged in two rows has been described with reference to FIG. 6, but there are also chips arranged in one row as shown in FIG. Such a chip can be dealt with by using a thin film sheet 2 in which the wide region of the metal film 21A is arranged on a straight line in the horizontal direction of the paper as shown in FIG. Further, the pads 11 are arranged in a row in this way, and the length LA of the long side extending in the direction intersecting (orthogonal to) the outer periphery of the chip 10 is about 140 μm, and extends along the outer periphery of the chip 10. FIG. 6 shows the case where the short side length LB is about 19 μm, the pitch LP where the adjacent pads 11 are arranged is about 34 μm, and the interval between the adjacent pads 11 is about 15 μm. Since the long side is about twice or more compared to the pad 11 and the center position of the pad 11 in the short side direction can be aligned with the center position of the pad 11 shown in FIG. 6, FIG. 9 to FIG. 11 are used. The thin film sheet 2 described above can be used, and the probes 7A and 7B come into contact with the pad 11 at the positions POS1 and POS2 shown in FIG.

  In addition, when the number of pads 11 is larger, the pads 11 may be arranged in three or more rows. FIG. 15 is a main part plan view of the thin film sheet 2 corresponding to the pads 11 arranged in three rows, and FIG. 16 is a main part plan view of the thin film sheet 2 corresponding to the pads 11 arranged in four rows. If the size of the chip 10 is the same, the distance LX described with reference to FIG. 9 becomes further narrower as the number of pads 11 arranged increases, so that the metal film including the metal films 21A and 21B comes into contact. There is further concern. Therefore, as shown in FIGS. 15 and 16, the metal films 21A, 21B, 21C, and 21D are obtained by rotating the planar pattern of the metal film 21A shown in FIG. 9 by 45 °, for example. , 21B, 21C, 21D can be prevented from contacting each other. Further, here, an example in which the planar pattern of the metal film 21A shown in FIG. 9 is rotated by 45 ° has been described, but the embodiment is not limited to 45 °, and the metal films 21A, 21B, 21C, and 21D are in contact with each other. Other rotation angles may be used as long as they can be prevented. The metal film 21C is provided with a probe 7C corresponding to the pad 11 disposed inside the chip 10 further than the pad 11 to which the probe 7B corresponds, and the metal film 21D has a pad 11 to which the probe 7C corresponds. Further, a probe 7D corresponding to the pad 11 arranged inside the chip 10 is formed.

  Here, FIG. 17 is a fragmentary cross-sectional view along the line DD in FIG. 16, and FIG. 18 is a fragmentary cross-sectional view along the line EE in FIG. As shown in FIG. 16, when the metal films 21A to 21D having the probes 7A to 7D corresponding to the four rows of pads 11 are arranged, wirings electrically connected to the metal films 21A to 21D from the upper layer, respectively. It is difficult to form all of the above with the same wiring layer. This is because when the distance LX is reduced, the metal films 21A to 21D may be brought into contact with each other, and wirings electrically connected to the metal films 21A to 21D may be brought into contact with each other. is there. Therefore, in the present embodiment, as shown in FIGS. 17 and 18, it can be exemplified that these wirings are formed from two wiring layers (wirings 23 and 26). A polyimide film 27 is formed on the wiring (second wiring) 26 and the polyimide film 25. The relatively lower wiring 23 is in contact with the metal films 21A and 21C at the bottom of the through hole 24 formed in the polyimide film 22, and the relatively upper wiring 26 is a through hole 28 formed in the polyimide films 22 and 25. In contact with the metal films 21B and 21D. As a result, in the same wiring layer, it is possible to ensure a large interval between the adjacent wirings 23 or 26, thereby preventing a problem that the adjacent wirings 23 or 26 are in contact with each other. In addition, when the pads 11 have five or more rows and the number of probes corresponding to the pads 11 increases and the distance LX becomes narrow, the wiring interval may be widened by forming wiring layers in multiple layers.

  Next, the structure of the thin film sheet 2 of the first embodiment will be described with reference to FIGS. 19 to 26 (excluding FIGS. 23 and 24) show the production of the thin film sheet 2 having the probes 7A and 7B corresponding to the two rows of pads 11 (see FIG. 6) described with reference to FIGS. It is principal part sectional drawing in the process. The structure of the thin film sheet, the manufacturing process of the thin film sheet, and the structure and manufacturing process of the probe similar to the probe 7 (probes 7A to 7D) are described in Japanese Patent Application Nos. 2003-75429 and 2003-371515. Japanese Patent Application No. 2003-372323, Japanese Patent Application No. 2004-115048, PCT Application No. PCT / JP2004 / 17160, PCT Application No. PCT / JP2005 / 4344, Japanese Patent Application No. 2005-109350, Japanese Patent Application No. 2005-168112, and Japanese Patent Application No. 2005. There is also a description in -181085.

  First, as shown in FIG. 19, a wafer 31 made of silicon having a thickness of about 0.2 mm to 0.6 mm is prepared, and a silicon oxide film 32 having a thickness of about 0.5 μm is formed on both surfaces of the wafer 31 by a thermal oxidation method. Form. Subsequently, the silicon oxide film 32 on the main surface side of the wafer 31 is etched using the photoresist film as a mask, and an opening reaching the wafer 31 is formed in the silicon oxide film 32 on the main surface side of the wafer 31. Next, using the remaining silicon oxide film 32 as a mask, the wafer 31 is anisotropically etched using a strong alkaline aqueous solution (for example, potassium hydroxide aqueous solution), so that the main surface of the wafer 31 is surrounded by the (111) plane. A quadrangular pyramid type or quadrangular pyramid shaped hole 33 is formed.

  Next, as shown in FIG. 20, the silicon oxide film 32 used as a mask when forming the hole 33 is removed by wet etching using a mixed solution of hydrofluoric acid and ammonium fluoride. Subsequently, a silicon oxide film 34 having a thickness of about 0.5 μm is formed on the entire surface of the wafer 31 including the inside of the hole 33 by performing a thermal oxidation process on the wafer 31. Next, a conductive film 35 is formed on the main surface of the wafer 31 including the inside of the hole 33. The conductive film 35 can be formed, for example, by sequentially depositing a chromium film having a thickness of about 0.1 μm and a copper film having a thickness of about 1 μm by a sputtering method or a vapor deposition method. Next, a photoresist film is formed on the conductive film 35, and the photoresist film in a region where the metal films 21A and 21B (see FIGS. 9 to 11) are formed in a later process by a photolithography technique is removed. An opening is formed.

  Next, a conductive film 37 and a conductive film 38 having high hardness are sequentially deposited on the conductive film 35 appearing at the bottom of the opening of the photoresist film by an electrolytic plating method using the conductive film 35 as an electrode. . In the first embodiment, the conductive film 37 may be a rhodium film and the conductive film 38 may be a nickel film. Through the steps so far, the above-described metal films 21A and 21B can be formed from the conductive films 37 and 38. Further, the conductive films 37 and 38 in the hole 33 become the above-described probes 7A and 7B. The conductive film 35 is removed in a later step, which will be described later.

  In the metal films 21 </ b> A and 21 </ b> B, when the above-described probes 7 </ b> A and 7 </ b> B are formed in a later process, the conductive film 37 formed from the rhodium film becomes the surface, and the conductive film 37 is in direct contact with the pad 11. become. For this reason, it is preferable to select a material having high hardness and excellent wear resistance as the conductive film 37. Further, since the conductive film 37 is in direct contact with the pad 11, if the chips 11 scraped by the probes 7 </ b> A and 7 </ b> B adhere to the conductive film 37, a cleaning process is required to remove the chips, and the probe inspection process. There is a concern that it will extend. Therefore, as the conductive film 37, it is preferable to select a material to which the material forming the pad 11 is difficult to adhere. Therefore, in Embodiment 1, a rhodium film that satisfies these conditions is selected as the conductive film 37. Thereby, the cleaning process can be omitted.

  Next, after removing the photoresist film used to form the metal films 21A and 21B (conductive films 37 and 38), the metal films 21A and 21B and the conductive film 35 are covered as shown in FIG. Thus, a polyimide film 22 (see also FIGS. 10 and 11) is formed. Subsequently, the aforementioned through hole 24 reaching the metal films 21 </ b> A and 21 </ b> B is formed in the polyimide film 22. The through hole 24 can be formed by drilling using a laser or dry etching using an aluminum film as a mask.

  Next, as shown in FIG. 22, a conductive film 42 is formed on the polyimide film 22 including the inside of the through hole 24. The conductive film 42 can be formed, for example, by sequentially depositing a chromium film having a thickness of about 0.1 μm and a copper film having a thickness of about 1 μm by a sputtering method or a vapor deposition method. Subsequently, after a photoresist film is formed on the conductive film 42, the photoresist film is patterned by a photolithography technique, and an opening reaching the conductive film 42 is formed in the photoresist film. Next, a conductive film 43 is formed on the conductive film 42 in the opening by plating. In the first embodiment, as the conductive film 43, a copper film, or a laminated film in which a copper film and a nickel film are sequentially deposited from the lower layer can be exemplified.

  Next, after removing the photoresist film, the conductive film 42 is etched using the conductive film 43 as a mask, thereby forming the wiring 23 composed of the conductive films 42 and 43. The wiring 23 can be electrically connected to the metal films 21 </ b> A and 21 </ b> B at the bottom of the through hole 24.

  Here, FIG. 23 shows a principal plane pattern of the wiring 23 in a region corresponding to one chip 10. In FIG. 23, the above-described through hole 24 is disposed under the wiring 23 in the region indicated by THA, and the metal films 21A and 21B are disposed under the through hole 24. The plurality of wirings 23 shown in FIG. 23 include those formed to give rigidity to the thin film sheet 2 and not electrically connected to the probes 7A and 7B. FIG. 24 is an enlarged view of the area indicated by PSL in FIG.

In the first embodiment, among the plurality of wirings 23, the wiring ( fifth wiring) 23G electrically connected to the reference potential (ground potential) is between the plurality of wirings ( fourth wiring) 23S used for signal transmission. Is arranged. The wiring 23G is arranged so as to extend as close as possible to the probes 7A and 7B. By adopting such a layout of the wirings 23G and 23S, the wiring 23G that electrically connects the wiring 23S used for signal transmission to the reference potential (ground potential) is shielded, so that it is formed in the chip 10. Even when the semiconductor integrated circuit performs high-speed operation at, for example, an operating frequency of 100 MHz or more, noise can be hardly generated in the wiring 23S. Thereby, the yield of probe inspection using the probe card of the first embodiment can be improved.

Among the plurality of wirings 23, a plurality of power supply system wirings ( third wirings) 23P that are electrically connected to the power supply of the same system are connected to the metal films 21A and 21B including the probes 7 (7A and 7B). They are connected to each other at a second position in the extending direction from the position (first position (through hole 24)). As a result, the plurality of power supply wirings 23 </ b> P are mutually complemented in electrical characteristics. That is, according to the first embodiment, it is possible to enhance the electrical characteristics of the power supply wiring 23P. As a result, it is possible to make it difficult for noise to be generated in the wiring 23P, thereby improving the yield of probe inspection using the probe card of the first embodiment.

  Although not shown, the wiring 23S used for signal transmission may be connected to each other in the same way as the wiring 23P when the same signal is transmitted. As a result, the plurality of wirings 23S to which the same signal is transmitted can be made to complement each other in electrical characteristics, and the electrical characteristics can be enhanced. As a result, noise can be made less likely to occur in the plurality of wirings 23S to which the same signal is transmitted, so that the yield of probe inspection using the probe card of the first embodiment can be further improved.

  After the wiring 23 is formed, the polyimide film 25 is formed on the main surface of the wafer 31 as shown in FIG. Subsequently, as shown in FIG. 26, the silicon oxide film 34 on the back surface of the wafer 31 is removed by etching using, for example, a mixed solution of hydrofluoric acid and ammonium fluoride. Subsequently, the wafer 31 which is a mold material for forming the thin film sheet 2 is removed by etching using a strong alkaline aqueous solution (for example, potassium hydroxide aqueous solution). Next, the silicon oxide film 34 and the conductive film 35 are sequentially removed by etching to manufacture the thin film sheet 2 of the first embodiment. At this time, the silicon oxide film 34 is etched using a mixed solution of hydrofluoric acid and ammonium fluoride, and the chromium film contained in the conductive film 35 is etched using a potassium permanganate aqueous solution and contained in the conductive film 35. The copper film to be etched is etched using an alkaline copper etchant. Through the steps so far, the rhodium film, which is the conductive film 37 (see FIG. 20) forming the probes 7A and 7B, appears on the surfaces of the probes 7A and 7B. As described above, in the probes 7A and 7B having the rhodium film formed on the surface, Au or the like, which is the material of the pad 11 that the probes 7A and 7B are in contact with, is less likely to adhere, has a higher hardness than Ni, and is not easily oxidized. Contact resistance can be stabilized.

  If necessary, wiring may be formed in multiple layers by repeating the process of forming the through hole 24, the wiring 23 and the polyimide film 25.

  First, as shown in FIG. 27, the pressing tool 9 described above with reference to FIG. 3 is prepared. Next, the main surface of the pressing tool 9 is directed upward, and a sheet-like elastomer 45 having a thickness of about 50 μm is disposed on the main surface of the pressing tool 9. The elastomer 45 absorbs variations in the heights of the tips of the individual probes 7A and 7B by local deformation while reducing the impact when the tips of the multiple probes 7A and 7B come into contact with the pad 11. The contact between the probe 7A and 7B and the pad 11 is realized by uniform biting in accordance with the height variation of 11.

  Subsequently, a polyimide sheet 46 having a thickness of about 12.5 μm is disposed on the elastomer 45. At this time, the elastomer 45 under the polyimide sheet 46 is attracted to the main surface of the pressing tool 9 by electrostatic attracting force, and the polyimide sheet 46 is also attracted to the elastomer 45 by electrostatic attracting force. Therefore, the elastomer 45 and the polyimide sheet 46 do not fall off the pressing tool 9 as long as the pressing tool 9 is inverted.

  Next, as shown in FIG. 28, with the elastomer 45 and the polyimide sheet 46 electrostatically adsorbed to the pressing tool 9, the main surface of the pressing tool 9 is the back surface of the thin film sheet 2 (the main surface on which the probe 7 is formed). On the opposite side). At this time, the region where the pressing tool 9 is bonded is a region where the probe 7 is formed on the main surface side.

  Thereafter, the thin film sheet 2 to which the pressing tool 9 is bonded as described above is attached to the probe card of the first embodiment, and adjustment is performed. The adjustment performed here is the amount of extrusion of the thin film sheet 2 from the surface of the multilayer wiring board 1 by the pressing force from the pressing tool 9 (the height HT from the surface of the multilayer wiring board 1 to the probe surface of the thin film sheet 2 (FIG. 1 Adjustment) and alignment of the tip of each probe 7 (alignment in the plane with the height and corresponding pads 11 and 12).

(Embodiment 2)
In the second embodiment, the plurality of probes 7 formed on the thin film sheet 2 are brought into contact with the wafer WH to be inspected (see FIG. 5) in one contact with the two chips 10 (see FIGS. 6 and 12). The layout of the wiring 23 in the case of contacting with will be described.

  FIG. 29 is an explanatory diagram for explaining the layout of the wirings 23 in the second embodiment. In FIG. 29, an area surrounded by a one-dotted line is an area corresponding to the outer shape of the chip 10 to be inspected, and the two chips 10 to be inspected are adjacent to each other in the extending direction of the diagonal lines. Is the case.

  In the first embodiment, a plurality of power supply system wirings 23P that are electrically connected to the power supply of the same system are connected to each other using FIG. 24, and the plurality of power supply system wirings 23P are mutually supplemented for electrical characteristics. Explained the case. Also in the second embodiment, as shown in FIG. 29, a pattern in which a plurality of power supply lines 23P that are electrically connected to a power supply of the same system are connected to each other is used. One wiring 23W having a relatively wider width than the wiring 23P is disposed up to the vicinity of the probe 7P to be electrically connected, and a pattern branches into a plurality of wirings 23P in the vicinity of the probe 7P. In the second embodiment, for example, when the layout is such that one wiring 23W branches to two wirings 23P, it can be exemplified that the width of the wiring 23W is about twice the width of the wiring 23P. When the plurality of probes 7 formed on the thin film sheet 2 come into contact with the two chips 10 in one contact with the wafer WH to be inspected, the number of wirings 23 provided in the thin film sheet 2 increases. There is a concern that it becomes difficult to route each wiring 23 in the thin film sheet 2. However, by adopting the layout of the wirings 23W and 23P of the second embodiment, the plurality of power supply system wirings 23P electrically connected to the power supply of the same system are combined into one by the relatively wide wirings 23. Since they extend together, the wiring in the thin film sheet 2 can be facilitated while strengthening the electrical characteristics.

  In addition, in the case where the relatively wide wiring 23W extends to the probe 7P and is electrically connected to the probe 7P through the through hole 24 (see FIG. 22), Since the wide wiring 23W is arranged, the rigidity of the thin film sheet 2 at the position where the probe 7P is arranged becomes high, and there is a concern that the probe 7P cannot contact the pads 11 and 12 (see FIGS. 6 and 12). Is done. However, according to the second embodiment, the wiring 23W branches to a plurality of relatively narrow wirings 23P in the vicinity of the probe 7P, and the probe 7P is arranged under each wiring 23P. The rigidity of the thin film sheet 2 at the position where the probe 7P is disposed can be prevented from increasing. That is, during probe inspection, the probe 7P can be reliably brought into contact with the corresponding pads 11 and 12.

  In the above-described second embodiment, the layout of the wiring 23 in the case where the probe inspection is performed on the two chips 10 has been described. However, even in the case where the probe inspection is performed on one chip 10, the present embodiment is described. The layout of the two wirings 23W and 23P may be applied.

  According to the second embodiment as described above, the same effect as in the first embodiment can be obtained.

(Embodiment 3)
Next, the probe card according to the third embodiment will be described.

  FIG. 30 is a plan view of the main part of the lower surface of the probe card compared to the probe card of the third embodiment, and the wiring 23 extending into the thin film sheet 2 and the terminals (pogo seats 8) of the multilayer wiring board 1 are shown. This explains the electrical connection relationship. In FIG. 30, a terminal indicated by “S” is a signal system terminal electrically connected to the wiring 23S used for signal transmission in the wiring 23 (see FIG. 24), and is indicated by “V”. The terminal is a power supply system terminal electrically connected to the wiring 23V (including the wiring 23P (see FIG. 24) and the wiring 23G (see FIG. 24)) used for power supply among the wiring 23.

  As shown in FIG. 30, the signal system terminals and the power system terminals are arranged along the outer periphery of the multilayer circuit board 1 within the plane of the multilayer circuit board 1. Further, in the arrangement of the signal system terminals and the power system terminals along the outer periphery of the multilayer wiring board 1, the signal system terminals and the power system terminals are arranged, for example, by three signal system terminals in succession. It is a regular arrangement in which a certain number of terminals are successively arranged, such that two power supply terminals are arranged in succession later.

  By the way, in the thin film sheet 2, when the signal system wiring 23S and the power system wiring 23V are formed in the same wiring layer, the signal system wiring 23S is arranged in accordance with the arrangement of the signal system terminals and the power system terminals. In addition, it becomes difficult to draw out the power supply wiring 23V toward the outer periphery of the thin film sheet 2. Therefore, the signal system wiring 23S and the power system wiring 23V routed to the outer periphery of the thin film sheet 2 are electrically connected to the corresponding signal system terminals or power system terminals via the jumper wires 51, respectively. . As a result, there may be a portion where a plurality of jumper lines 51 intersect on the plane, which may cause a problem that the connection state and the arrangement state of the jumper lines 51 become complicated. This tendency becomes more prominent as the number of wirings 23S and 23V increases.

  Therefore, in the third embodiment, as shown in FIG. 31, in the thin film sheet 2, the wiring 23 is formed by a plurality of wiring layers (for example, two layers), and the signal wiring 23S and the power supply wiring 23V are formed. Are formed with different wiring layers. That is, the wiring 23S is formed of the first wiring layer, and the wiring 23V is formed of the second wiring layer. The wiring 23V is electrically connected to the probe 7 (7A, 7B) via a relay wiring 23M formed of the same wiring layer as the wiring 23S. Note that a polyimide film 25 </ b> A is formed on the wiring 23 </ b> V and the polyimide film 25. Thereby, since the number of wirings in each wiring layer can be significantly reduced, the degree of freedom of routing of the wirings 23S and 23V in the thin film sheet 2 can be greatly improved. As a result, as shown in FIG. 32, the wirings 23 </ b> S and 23 </ b> V can be drawn toward the outer periphery of the thin film sheet 2 in accordance with the arrangement of the signal system terminals and the power system terminals of the multilayer wiring board 1. That is, in the multilayer wiring board 1, it is possible to arrange a plurality of jumper wires 51 so as not to cross each other on a plane, or to omit the jumper wires 51 themselves, so that the connection state and arrangement state of the jumper wires 51 are greatly increased. Can be simplified.

  Alternatively, the signal line 23S may be an upper layer and the power line 23V may be a lower layer. In that case, the signal wiring 23S is configured to be electrically connected to the probe 7 (7A, 7B) via the relay wiring 23M.

  According to the third embodiment as described above, the same effect as in the first and second embodiments can be obtained.

(Embodiment 4)
FIG. 33 is a plan view of a main part of the lower surface of the probe card according to the fourth embodiment.

  As shown in FIG. 33, the fourth embodiment has a corresponding power supply system terminal (Pogo seat 8) on the multilayer wiring board 1 side with respect to the number of the plurality of probes 7 electrically connected to the power supply of the same system. ) Is a large number. In such a case, a wiring pattern is formed so that each of the probes 7 is electrically connected to a plurality of power supply system terminals on the multilayer wiring board 1 side. That is, the power supply system wiring 23P drawn from the probe 7 (see also FIG. 24) and the wiring 23P2 electrically connected to the plurality of power supply system terminals on the multilayer wiring board 1 side are formed, and the plurality of wirings 23P2 are formed. The pattern of the wiring 23 in the thin film sheet 2 is formed so as to be connected to one wiring 23P. As a result, the allowable current value for one probe 7 electrically connected to the wiring 23P can be increased, so that the electrical characteristics of the power supply wiring 23P can be enhanced. As a result, noise can be hardly generated in the wiring 23P, and the yield of probe inspection using the probe card of the fourth embodiment can be improved.

  In addition, since a plurality of wirings 23P2 are connected to one wiring 23P, even if one wiring 23P2 is cut off, power can be supplied to the probe 7 from the other wiring 23P2. Thus, it is possible to prevent a decrease in the yield of probe inspection using the probe card No. 4.

  According to the fourth embodiment as described above, the same effects as those of the first to third embodiments can be obtained.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the above-described embodiment, the case where the chip on which the LCD driver is formed is a target for probe inspection using a thin film probe, but a memory circuit such as a logic circuit and a DRAM (Dynamic Random Access Memory), etc. A probe inspection using a thin film probe may also be performed on the chip on which is formed.

  The method for manufacturing a semiconductor integrated circuit device of the present invention can be widely applied to a probe inspection process in the manufacturing process of a semiconductor integrated circuit device.

It is principal part sectional drawing of the probe card which is Embodiment 1 of this invention. It is a principal part top view of the lower surface of the probe card which is Embodiment 1 of this invention. It is sectional drawing along the AA line in FIG. It is principal part sectional drawing of the probe card which is Embodiment 1 of this invention. It is a top view of the semiconductor wafer in which the semiconductor chip area | region of the object which carries out a probe test | inspection using the probe card which is Embodiment 1 of this invention was formed. It is a top view of the semiconductor chip of the object which carries out a probe test using the probe card which is Embodiment 1 of the present invention. FIG. 7 is a perspective view of pads formed on the semiconductor chip shown in FIG. 6. It is principal part sectional drawing which shows the connection method to the liquid crystal panel of the semiconductor chip shown in FIG. It is a principal part top view of the thin film sheet which forms the probe card which is Embodiment 1 of this invention. It is sectional drawing along the BB line in FIG. It is sectional drawing along CC line in FIG. It is a top view of the semiconductor chip of the object which carries out a probe test using the probe card which is Embodiment 1 of the present invention. It is a principal part top view of the thin film sheet which forms the probe card which is Embodiment 1 of this invention. It is a principal part top view which showed the position where a probe contacts on the bump electrode provided in the semiconductor chip of the object which carries out a probe test | inspection using the probe card which is Embodiment 1 of this invention. It is a principal part top view of the thin film sheet which forms the probe card which is Embodiment 1 of this invention. It is a principal part top view of the thin film sheet which forms the probe card which is Embodiment 1 of this invention. It is sectional drawing along the DD line in FIG. It is sectional drawing along the EE line in FIG. It is principal part sectional drawing explaining the manufacturing process of the thin film sheet which forms the probe card which is Embodiment 1 of this invention. It is principal part sectional drawing in the manufacturing process of the thin film sheet following FIG. It is principal part sectional drawing in the manufacturing process of the thin film sheet following FIG. It is principal part sectional drawing in the manufacturing process of the thin film sheet following FIG. It is a principal part top view explaining the wiring pattern formed in the thin film sheet which forms the probe card which is Embodiment 1 of this invention. FIG. 24 is an essential part plan view showing a part of FIG. 23 in an enlarged manner. It is principal part sectional drawing in the manufacturing process of the thin film sheet following FIG. It is principal part sectional drawing in the manufacturing process of the thin film sheet following FIG. It is principal part sectional drawing explaining the process of attaching the thin film sheet manufactured at the process of FIGS. 19-26 to a probe card. It is principal part sectional drawing explaining the process of attaching the thin film sheet following FIG. 27 to a probe card. It is explanatory drawing explaining the layout of the wiring formed in the thin film sheet which forms the probe card which is Embodiment 2 of this invention. It is a principal part top view of the lower surface of the probe card compared with the probe card which is Embodiment 3 of this invention. It is principal part sectional drawing of the thin film sheet which forms the probe card which is Embodiment 3 of this invention. It is a principal part top view of the lower surface of the probe card which is Embodiment 3 of this invention. It is a principal part top view of the lower surface of the probe card which is Embodiment 4 of this invention.

Explanation of symbols

1 Multilayer wiring board (first wiring board)
2 Thin film sheet (first sheet)
3 Plunger 3A Spring 4 Holding ring 5 Opening 6 Adhesive ring 7, 7A, 7B, 7C, 7D, 7P Probe (contact terminal)
8 Pogo seat 9 Pressing tool (pressing mechanism)
10 chips (chip area)
11, 12 Pad (Test pad (first electrode))
14, 15 Pixel electrode 16 Glass substrate 17 Liquid crystal layer 18 Glass substrate 21A, 21B, 21C, 21D Metal film 22 Polyimide film 23 Wiring (second wiring)
23G wiring ( 5th wiring)
23M wiring 23P wiring ( third wiring)
23P2 wiring 23S wiring ( fourth wiring)
23V, 23W Wiring 24 Through hole (first position)
24A Through hole 25, 25A Polyimide film 26 Wiring (second wiring)
27 Polyimide film 28 Through hole 31 Wafer 32 Silicon oxide film 33 Hole 34 Silicon oxide film 35, 37, 38, 42, 43 Conductive film 45 Elastomer 46 Polyimide sheet 51 Jumper wire CHD Card holder FGR Frog ring IA Central area OA Outer peripheral area PGP Pogo pins POS1, POS2 Position PSL area SB Auxiliary substrate THA area THD Tester head WH Wafer

Claims (19)

A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) Partitioned into a plurality of chip regions, a semiconductor integrated circuit is formed in each of the plurality of chip regions, and a plurality of first electrodes electrically connected to the semiconductor integrated circuit are formed on the main surface Preparing a semiconductor wafer;
(B) A first wiring board on which a plurality of first wirings are formed, a plurality of contact terminals for contacting the plurality of first electrodes, and a plurality of second wirings electrically connected to the plurality of contact terminals. The plurality of second wirings are electrically connected to the plurality of first wirings, and the tips of the plurality of contact terminals are held on the first wiring substrate so as to face the main surface of the semiconductor wafer. Preparing a first card having the first sheet and a pressing mechanism that presses the region of the first sheet where the plurality of contact terminals are formed from the back surface;
(C) a step of performing electrical inspection of the semiconductor integrated circuit by bringing the tips of the plurality of contact terminals into contact with the plurality of first electrodes;
Here, among the plurality of second wirings, the plurality of third wirings having the same power source are directed from the first position where the power supply is connected to the inside of the region where the plurality of contact terminals are formed. It has a pattern which is connected and integrated with each other at a second position which is on the extending direction and located further inside than the inner end portion of the second wiring arranged between the third wirings. . The method of manufacturing a semiconductor integrated circuit device according to claim 1,
The third wiring at the second position has a relatively larger width than the first position. The method of manufacturing a semiconductor integrated circuit device according to claim 1,
One said 3rd wiring is electrically connected with the 2 or more said 1st wiring whose power supply is the same system | strain. The method of manufacturing a semiconductor integrated circuit device according to claim 1,
Wherein between the plurality of third wirings, the plurality of second wirings, wherein said second wiring different current flows through the plurality of third wirings are disposed. A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) Partitioned into a plurality of chip regions, a semiconductor integrated circuit is formed in each of the plurality of chip regions, and a plurality of first electrodes electrically connected to the semiconductor integrated circuit are formed on the main surface Preparing a semiconductor wafer;
(B) A first wiring board on which a plurality of first wirings are formed, a plurality of contact terminals for contacting the plurality of first electrodes, and a plurality of second wirings electrically connected to the plurality of contact terminals. The plurality of second wirings are electrically connected to the plurality of first wirings, and the tips of the plurality of contact terminals are held on the first wiring substrate so as to face the main surface of the semiconductor wafer. Preparing a first card having the first sheet and a pressing mechanism that presses the region of the first sheet where the plurality of contact terminals are formed from the back surface;
(C) a step of performing electrical inspection of the semiconductor integrated circuit by bringing the tips of the plurality of contact terminals into contact with the plurality of first electrodes;
Here, among the plurality of second wirings, the plurality of fourth wirings to which the same electrical signal is transmitted are on the extending direction from the first position connected to the contact terminal, and the fourth wirings It has a pattern which is connected and integrated with each other at a second position located further inside than the inner end portion of the second wiring disposed therebetween. In the manufacturing method of the semiconductor integrated circuit device according to claim 5,
The fourth wiring in the second position has a relatively larger width than the first position. The method of manufacturing a semiconductor integrated circuit device according to claim 6.
In the step (c), the plurality of contact terminals are in contact with the plurality of first electrodes arranged in the two chip regions. In the manufacturing method of the semiconductor integrated circuit device according to claim 5,
Around the fourth wiring, one or more fifth wirings that are electrically connected to a reference potential are formed. The method of manufacturing a semiconductor integrated circuit device according to claim 6.
The plurality of second wirings include a plurality of third wirings for supplying power,
One said 3rd wiring is electrically connected with the 2 or more said 1st wiring whose power supply is the same system | strain. In the manufacturing method of the semiconductor integrated circuit device according to claim 9,
Among the plurality of third wirings, those having the same power source have a pattern that is connected and integrated with each other at a second position in the extending direction from the first position connected to the contact terminal. A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) Partitioned into a plurality of chip regions, a semiconductor integrated circuit is formed in each of the plurality of chip regions, and a plurality of first electrodes electrically connected to the semiconductor integrated circuit are formed on the main surface Preparing a semiconductor wafer;
(B) A first wiring board on which a plurality of first wirings are formed, a plurality of contact terminals for contacting the plurality of first electrodes, and a plurality of second wirings electrically connected to the plurality of contact terminals. The plurality of second wirings are electrically connected to the plurality of first wirings, and the tips of the plurality of contact terminals are held on the first wiring substrate so as to face the main surface of the semiconductor wafer. Preparing a first card having the first sheet and a pressing mechanism that presses the region of the first sheet where the plurality of contact terminals are formed from the back surface;
(C) a step of performing electrical inspection of the semiconductor integrated circuit by bringing the tips of the plurality of contact terminals into contact with the plurality of first electrodes;
Here, the plurality of second wirings are formed of a plurality of wiring layers,
The plurality of second wirings include a plurality of third wirings for supplying power and a plurality of fourth wirings for signal transmission,
The plurality of third wirings are formed in a first wiring layer,
The plurality of fourth wirings are formed in a second wiring layer different from the first wiring layer,
One said 3rd wiring is branched between the 1st position connected with the said contact terminal, and the said 1st wiring board, and the power supply is electrically connected with two or more said 1st wirings which are the same system | strains. Yes. In the manufacturing method of the semiconductor integrated circuit device according to claim 11,
Among the plurality of third wirings, the power source having the same system is on the extending direction from the first position connected to the contact terminal, and is arranged between the third wirings. Patterns are connected and integrated with each other at a second position located further inside than the inner end of the wiring . In the manufacturing method of the semiconductor integrated circuit device according to claim 11,
Among the plurality of fourth wirings, the same electrical signal is transmitted on the extending direction from the first position connected to the contact terminal and between the fourth wirings. Two wirings have patterns that are connected and integrated with each other at a second position located further inside than the inner end of the wiring . A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) Partitioned into a plurality of chip regions, a semiconductor integrated circuit is formed in each of the plurality of chip regions, and a plurality of first electrodes electrically connected to the semiconductor integrated circuit are formed on the main surface Preparing a semiconductor wafer;
(B) A first wiring board on which a plurality of first wirings are formed, a plurality of contact terminals for contacting the plurality of first electrodes, and a plurality of second wirings electrically connected to the plurality of contact terminals. The plurality of second wirings are electrically connected to the plurality of first wirings, and the tips of the plurality of contact terminals are held on the first wiring substrate so as to face the main surface of the semiconductor wafer. Preparing a first card having the first sheet and a pressing mechanism that presses the region of the first sheet where the plurality of contact terminals are formed from the back surface;
(C) a step of performing electrical inspection of the semiconductor integrated circuit by bringing the tips of the plurality of contact terminals into contact with the plurality of first electrodes;
Here, the plurality of second wirings include a plurality of third wirings for supplying power,
One said 3rd wiring is branched between the 1st position connected with the said contact terminal, and the said 1st wiring board, and the power supply is electrically connected with two or more said 1st wirings which are the same system | strains. Yes. 15. The method of manufacturing a semiconductor integrated circuit device according to claim 14,
Among the plurality of third wirings, the power source having the same system is on the extending direction from the first position connected to the contact terminal, and is arranged between the third wirings. Patterns are connected and integrated with each other at a second position located further inside than the inner end of the wiring . The method of manufacturing a semiconductor integrated circuit device according to claim 15,
The third wiring at the second position has a relatively larger width than the first position. 15. The method of manufacturing a semiconductor integrated circuit device according to claim 14,
The plurality of third wirings include one or more fifth wirings that are electrically connected to a reference potential. The method of manufacturing a semiconductor integrated circuit device according to claim 17.
The reference potential is a ground potential. 15. The method of manufacturing a semiconductor integrated circuit device according to claim 14,
The semiconductor integrated circuit operates at a high frequency.

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