JP4769474B2 - Manufacturing method of semiconductor integrated circuit device - Google Patents

Description

  The present invention relates to a technology for manufacturing a semiconductor integrated circuit device, and more particularly to a technology effective when applied to the manufacture of an insulated gate field effect transistor formed in a semiconductor thin film on an insulating film.

  In Japanese Patent Application Laid-Open No. 8-220138 (Patent Document 1), when measuring the electrical characteristics of a semiconductor element using a membrane type probe card, the warping of the pressing plate due to the load from the shaft and the tension of the thin film is disclosed. In order to prevent contact and obtain good contact with the semiconductor element, the presser plate has an upper side that receives the shaft, a cylindrical side surface, and a lower surface that presses a metal protrusion that is formed in a thin film and is brought into contact with the semiconductor element. And an inclined surface formed between the lower surface and the cylindrical side surface.

  Japanese Patent Application Laid-Open No. 7-135240 (Patent Document 2) discloses a probe apparatus for inspecting electrical characteristics by using bumps formed on an anisotropic conductive thin film to connect to electrodes of a measured object. In this technique, air is blown into the gap between the object to be measured and the thin film on the apparatus table, the bending of the thin film is removed by the rebounding air pressure, and contact other than the bump is excluded from the surface of the object to be measured. Yes.

Also, Japanese Patent Application Laid-Open No. 7-283280 (Patent Document 3), Japanese Patent Application Laid-Open No. 8-50146 (Patent Document 4 (corresponding PCT International Publication WO95-34000)), Japanese Patent Application Laid-Open No. 8-2014427 (Patent Document). 5), Japanese Unexamined Patent Publication No. 10-308423 (Patent Document 6), Japanese Unexamined Patent Publication No. 11-23615 (Patent Document 7 (corresponding US Patent Publication USP 6,305,230)), Japanese Unexamined Patent Publication No. 11-97471. (Patent Document 8 (corresponding European publication EP1022775)), Japanese Unexamined Patent Publication No. 2000-150594 (patent literature 9 (corresponding European publication EP099451)), and Japanese Unexamined Patent Publication No. 2001-159443 (patent literature 10). It has a probe (contact terminal), insulating film, and lead-out wiring formed using integrated circuit device manufacturing technology Prober structure, its manufacturing method, the test pad and technology that enables the implementation of probe testing is disclosed by using the prober against narrow pitch chips.
JP-A-8-220138 JP 7-135240 A JP-A-7-283280 JP-A-8-50146 JP-A-8-201427 JP-A-10-308423 Japanese Patent Laid-Open No. 11-23615 Japanese Patent Laid-Open No. 11-97471 JP 2000-150594 A JP 2001-159634 A

  There is a probe inspection as an inspection technique for a semiconductor integrated circuit device. This probe inspection includes a function test for confirming whether or not the device operates according to a predetermined function, a test for determining a non-defective product / defective product by performing a DC operation characteristic and an AC operation characteristic test, and the like.

  In recent years, semiconductor integrated circuit devices have become more multifunctional, and it has been promoted to create a plurality of circuits on one semiconductor chip (hereinafter simply referred to as a chip). In addition, in order to reduce the manufacturing cost of the semiconductor integrated circuit device, the semiconductor elements and wirings are miniaturized to reduce the area of the semiconductor chip (hereinafter simply referred to as “chip”) and increase the number of acquired chips per wafer. Is underway. Therefore, not only the number of test pads (bonding pads) is increased, but also the arrangement of test pads is narrowed and the area of the test pads is also reduced. When a prober having a cantilever-like probe is used for the probe inspection as the pitch of the test pad is reduced, it is difficult to install the probe in accordance with the position of the test pad. There is a problem that becomes.

  The present inventors have studied a technique that can realize a probe inspection even for a chip having a narrow test pad pitch by using a prober having a probe formed by using a manufacturing technique of a semiconductor integrated circuit device. ing. Among them, the present inventors have found the following problems.

  That is, the probe is a part of a thin film probe formed by depositing a metal film and a polyimide film using a manufacturing technique of a semiconductor integrated circuit device, patterning them, and the like, and is an inspection object. It is provided on the main surface side of the thin film probe facing the chip. At the time of probe inspection, the thin film probe in the region where the probe is formed is pressed from the back surface opposite to the main surface with a pressing tool made of 42 alloy or the like and having a flat pressing surface. Due to this pressing, the thin film probe is moved in the outer peripheral direction of the pressing surface of the pressing tool while receiving the frictional resistance from the pressing tool. At this time, since the tension distribution of the thin film probe from the center to the outer peripheral direction changes abruptly around the outer peripheral portion of the pressing surface of the pressing tool, the thin film probe is located at a portion where the tension is weak or the portion where the out-of-plane deformation synthesis is weak. It will be deformed out of the plane and become unstable such as wrinkles. In particular, in the outer peripheral portion of the pressing surface of the pressing tool, the frictional force between the pressing tool and the thin film probe increases, and the remaining portion of the thin film probe may not be able to move in the outer peripheral direction of the pressing surface of the pressing tool. In such a case, the thin film probe is further greatly deformed. When such deformation occurs, the tension is reduced at the deformed portion. Therefore, the probe existing in the vicinity of the outer peripheral portion of the pressing surface of the pressing tool is affected by the deformation of the thin film probe. There is a possibility that the contact pressure with the test pad is far from the desired state. In such a state, the electrical contact resistance of the contact portion between the probe and the test pad becomes large, and it becomes impossible to accurately inspect the electrical resistance of the circuit inside the chip. In addition, when the deformation of the thin film probe is large, it is impossible to align the probe with the corresponding test pad.

  In the technique disclosed in Patent Document 1, the shape of the lower surface of the above-described holding plate facing the semiconductor element (chip) to be measured is substantially the same as the outer shape of the semiconductor element to be measured, and the upper surface is the object to be measured. It is larger and circular than the semiconductor element. In the case of such a structure, the distance from the outer portion of the semiconductor element to be measured to the translation base to which the thin film is attached is not equal in the entire thin film. For this reason, the tension acting on the thin film at all positions of the translation table on which the thin film is adhered becomes non-uniform, and the thin film is deformed at the time of probe inspection as in the technique studied by the present inventors. As a result, the probe and the test pad may not be able to contact with high accuracy.

  Further, in the technique disclosed in Patent Document 2, when a wavy shape such as a wrinkle is generated in the thin film, the thin film is sucked into the air suction hole, and the thin film is further deformed. Therefore, there is a possibility that the alignment between the probe and the corresponding test pad cannot be performed accurately. In addition, even if the thin film is adsorbed to the holding table with air, the part loosened by scissors or the like will remain loose, and the probe placed in the concave part will not be able to contact the test pad. Or contact pressure between the desired probe and the test pad may not be obtained.

  An object of one representative invention disclosed in the present application is to provide a probe and a test pad to which the probe corresponds in probe inspection using a thin film probe formed by using a manufacturing technique of a semiconductor integrated circuit device. It is an object to provide a technique capable of bringing a contact at a desired contact pressure.

  Another object of the present invention disclosed in this application is that the probe and the probe correspond to the probe inspection using the thin film probe formed by using the manufacturing technology of the semiconductor integrated circuit device. It is an object of the present invention to provide a technique capable of bringing a test pad into contact with accuracy.

  The outline of one representative one of the inventions disclosed in the present application will be briefly described as follows.

A method for manufacturing a semiconductor integrated circuit device according to the present invention includes the following steps.
(A) Partitioned into a plurality of chip regions, a semiconductor integrated circuit is formed in each of the plurality of chip regions, and a plurality of first electrodes electrically connected to the semiconductor integrated circuit are formed on the main surface Preparing a semiconductor wafer;
(B) a first wiring board on which the first wiring is formed, a plurality of contact terminals for contacting the plurality of first electrodes, and a second wiring electrically connected to the plurality of contact terminals are formed; A first sheet in which the second wiring is electrically connected to the first wiring and the tips of the plurality of contact terminals are held on the first wiring substrate so as to face a main surface of the semiconductor wafer; A first fixing jig for fixing the first sheet to a first surface of the wiring board facing the first sheet; and a plane disposed inside the first fixing jig, wherein the first sheet includes the first sheet. A step of preparing a first card having a pressing mechanism that presses a first region formed with a plurality of contact terminals from the back surface;
(C) A step of performing electrical inspection of the semiconductor integrated circuit by bringing the tips of the plurality of contact terminals into contact with the plurality of first electrodes.

  Here, the first contour of the pressing mechanism on which the stress from the first sheet acts is in a form along the second contour on the inside of the first fixing jig on which the stress from the first sheet acts. is there.

The method for manufacturing a semiconductor integrated circuit device according to the present invention includes the following steps.
(A) Partitioned into a plurality of chip regions, a semiconductor integrated circuit is formed in each of the plurality of chip regions, and a plurality of first electrodes electrically connected to the semiconductor integrated circuit are formed on the main surface Preparing a semiconductor wafer;
(B) a first wiring board on which the first wiring is formed, a plurality of contact terminals for contacting the plurality of first electrodes, and a second wiring electrically connected to the plurality of contact terminals are formed; A first sheet in which the second wiring is electrically connected to the first wiring and the tips of the plurality of contact terminals are held on the first wiring substrate so as to face a main surface of the semiconductor wafer; A first fixing jig for fixing the first sheet to a first surface of the wiring board facing the first sheet; and a plane disposed inside the first fixing jig, wherein the first sheet includes the first sheet. A step of preparing a first card having a pressing mechanism that presses a first region formed with a plurality of contact terminals from the back surface;
(C) A step of performing electrical inspection of the semiconductor integrated circuit by bringing the tips of the plurality of contact terminals into contact with the plurality of first electrodes.

Here, a second fixing jig for keeping the first region flat at a position corresponding to the first region is attached to the back surface of the first sheet,
The third contour of the second fixing jig has a shape along the second contour inside the first fixing jig on which the stress from the first sheet acts.

  Further, other outlines disclosed in the present application will be briefly described as follows.

1. A first wiring board on which a first wiring is formed;
A plurality of contact terminals for contacting the plurality of first electrodes formed on the main surface of the semiconductor wafer and a second wiring electrically connected to the plurality of contact terminals are formed, and the second wiring is the first wiring A first sheet electrically connected to the wiring and held by the first wiring board with tips of the plurality of contact terminals facing the main surface of the semiconductor wafer;
A first fixing jig for fixing the first sheet to a first surface of the first wiring board facing the first sheet;
A pressing mechanism that is disposed on the inside of the first fixing jig in a plane and presses the first region of the first sheet where the plurality of contact terminals are formed from the back surface;
The first contour of the pressing mechanism on which the stress from the first sheet acts is a probe card having a shape along the second contour inside the first fixing jig on which the stress from the first sheet acts. .

2. In the probe card according to Item 1,
The first contour of the pressing mechanism and the second contour inside the first fixing jig are circular or elliptical.

3. In the probe card according to Item 1,
The semiconductor wafer is partitioned into a plurality of chip regions, a semiconductor integrated circuit is formed in each of the plurality of chip regions, and the plurality of first electrodes electrically connected to the semiconductor integrated circuit on a main surface Formed,
At the time of electrical inspection of the semiconductor integrated circuit, the tips of the plurality of contact terminals are brought into contact with the plurality of first electrodes in the two or more chip regions,
The first contour of the pressing mechanism surrounds the two or more chip regions that are in contact with the plurality of contact terminals.

4). In the probe card according to Item 1,
The first contour of the pressing mechanism and the second contour inside the first fixing jig are polygonal and the corners of the polygon are chamfered.

5). In the probe card according to Item 1,
A second fixing jig for keeping the first region flat at a position corresponding to the first region is attached to the back surface of the first sheet,
The third contour of the second fixing jig has a shape along the second contour inside the first fixing jig on which the stress from the first sheet acts.

6). In the probe card according to Item 5,
The semiconductor wafer is partitioned into a plurality of chip regions, a semiconductor integrated circuit is formed in each of the plurality of chip regions, and the plurality of first electrodes electrically connected to the semiconductor integrated circuit on a main surface Formed,
At the time of electrical inspection of the semiconductor integrated circuit, the tips of the plurality of contact terminals are brought into contact with the plurality of first electrodes in the two or more chip regions,
The third contour of the second fixing jig surrounds the two or more chip regions that are in contact with the plurality of contact terminals.

7). In the probe card according to Item 1,
In the plane, an expansion mechanism is disposed between the pressing mechanism and the first fixing jig,
The expansion mechanism extends the slackness of the first region of the first sheet by pressing the first sheet from the back surface, and then the pressing mechanism presses the first region of the first sheet from the back surface.

8). A first wiring board on which a first wiring is formed;
A plurality of contact terminals for contacting the plurality of first electrodes formed on the main surface of the semiconductor wafer and a second wiring electrically connected to the plurality of contact terminals are formed, and the second wiring is the first wiring A first sheet electrically connected to the wiring and held by the first wiring board with tips of the plurality of contact terminals facing the main surface of the semiconductor wafer;
A first fixing jig for fixing the first sheet to a first surface of the first wiring board facing the first sheet;
A pressing mechanism that is disposed on the inside of the first fixing jig in a plane and presses the first region of the first sheet where the plurality of contact terminals are formed from the back surface;
A second fixing jig for keeping the first region flat at a position corresponding to the first region is attached to the back surface of the first sheet,
The third contour of the second fixing jig is a probe card having a shape along the second contour inside the first fixing jig on which stress from the first sheet acts.

9. Item 8. The probe card according to Item 8,
The second outline inside the first fixing jig and the third outline of the second fixing jig are circular or elliptical.

10. Item 9. The probe card according to Item 9,
The semiconductor wafer is partitioned into a plurality of chip regions, a semiconductor integrated circuit is formed in each of the plurality of chip regions, and the plurality of first electrodes electrically connected to the semiconductor integrated circuit on a main surface Formed,
At the time of electrical inspection of the semiconductor integrated circuit, the tips of the plurality of contact terminals are brought into contact with the plurality of first electrodes in the two or more chip regions,
The third contour of the second fixing jig surrounds the two or more chip regions that are in contact with the plurality of contact terminals.

11. Item 8. The probe card according to Item 8,
The second outline inside the first fixing jig and the third outline of the second fixing jig are polygonal and the corner portions of the polygon are chamfered.

12 Item 8. The probe card according to Item 8,
In the plane, an expansion mechanism is disposed between the pressing mechanism and the first fixing jig,
The expansion mechanism extends the slackness of the first region of the first sheet by pressing the first sheet from the back surface, and then the pressing mechanism presses the first region of the first sheet from the back surface.

Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.
(1) In probe inspection performed using a thin film probe formed by using a manufacturing technology of a semiconductor integrated circuit device, a probe (probe) and a test pad corresponding to the probe are brought into contact with each other at a desired contact pressure. Can do.
(2) In a probe inspection performed using a thin film probe formed using a manufacturing technique of a semiconductor integrated circuit device, the probe and the test pad corresponding to the probe can be brought into contact with each other with high accuracy.

  Before describing the present invention in detail, the meaning of terms in the present application will be described as follows.

  A wafer is a single crystal silicon substrate (generally a substantially planar circular shape) used in the manufacture of integrated circuits, an SOI (Silicon On Insulator) substrate, a sapphire substrate, a glass substrate, other insulating, anti-insulating or semiconductor substrates, and their composites. A special substrate. The term “semiconductor integrated circuit device” as used herein refers not only to a semiconductor integrated circuit device such as a silicon wafer or a sapphire substrate, but also to a TFT (Thin Film Transistor) unless otherwise specified. ) And STN (Super-Twisted-Nematic) liquid crystal or the like made on other insulating substrates such as glass.

  The device surface is a main surface of a wafer on which a device pattern corresponding to a plurality of chip regions is formed by lithography.

  Contact terminals are the same as those used in the manufacture of semiconductor integrated circuits for silicon wafers. Wiring is performed by a patterning method that combines photolithography, CVD (Chemical Vapor Deposition), sputtering, and etching. A layer and a tip electrically connected thereto are integrally formed.

  The thin film probe, the thin film probe card, or the protruding needle wiring sheet composite is provided with the contact terminal (protruding needle) that comes into contact with the object to be inspected and the wiring drawn from the contact terminal. A thin film on which a contact electrode is formed, for example, a thickness of about 10 μm to 100 μm.

  The probe card refers to a structure having a contact terminal that contacts a wafer to be inspected and a multilayer wiring board, and the semiconductor inspection apparatus refers to an inspection apparatus having a sample support system on which the probe card and the wafer to be inspected are placed. Say.

  The probe inspection is an electrical test performed with a prober on a wafer for which a wafer process has been completed. The semiconductor integrated circuit is configured by applying the tip of the contact terminal to an electrode formed on the main surface of the chip region. In other words, a non-defective product / defective product is discriminated by performing a function test for confirming whether or not the device operates in accordance with a predetermined function and a DC operation characteristic and an AC operation characteristic test. This is distinguished from a screening test (final test) that is performed after dividing into chips (or after packaging is completed).

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say.

  Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Also, components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted.

  Further, in all the drawings for explaining the present embodiment, hatching may be given even in a plan view for easy understanding of the configuration of each member.

  In the present embodiment, the insulated gate field effect transistor including the MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is called a MISFET (Metal Insulator Semiconductor Field Effect Transistor).

  Further, the details of the thin film probe by the semiconductor lithography technique used in the present application are disclosed in the following patent application by the present inventor and related inventors, and therefore, the contents thereof are repeated unless particularly necessary. Absent. Japanese Patent Application No. 6-22885, Japanese Patent Application Laid-Open No. 7-283280, Japanese Patent Application Laid-Open No. 8-50146, Japanese Patent Application Laid-Open No. 8-201427, Japanese Patent Application No. 9-119107. Japanese Unexamined Patent Publication No. 11-23615, Japanese Unexamined Patent Publication No. 2002-139554, Japanese Unexamined Patent Publication No. 10-308423, Japanese Patent Application No. 9-189660, Japanese Unexamined Patent Publication No. 11-97471, Japanese Unexamined Patent Publication 2000. -150594, Japanese Patent Application Laid-Open No. 2001-159543, Japanese Patent Application No. 2002-289377 (corresponding US Application No. 10 / 6676,609; US Application Date 2003.10.2), Japanese Patent Application Laid-Open No. 2004-2004. No. 132699, Japanese Unexamined Patent Publication No. 2005-24377, Japanese Unexamined Patent Publication No. 2004-288672 (corresponding to US No. 10 / 765,917; U.S. application date 2004.1.29), Japanese Unexamined Patent Publication No. 2004-144742 (corresponding U.S. Publication No. 2004 / 070,413), Japanese Unexamined Patent Publication No. 2004-157127, Japanese Unexamined Patent Publication No. 2004-144742 (corresponding US Publication No. 2004 / 070,413), Japanese Unexamined Patent Publication No. 2004-157127, Japanese Patent Application No. 2003-371515 (corresponding US Application No. 10 / 968,215). No .; US application date 2004.10.20), Japanese Patent Application No. 2003-372323 (corresponding US Application No. 10 / 968,431; US Application Date 2004.10.20), Japanese Patent Application No. 2004-1105048 PCT application number PCT / JP2004 / 17160, PCT application number PCT / JP200 / Nos 4344, and Japanese Patent Application No. 2004-378504.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
FIG. 1 is a plan view of the main part of the lower surface of the probe card according to the first embodiment, and FIG.

  As shown in FIGS. 1 and 2, the probe card of the first embodiment is formed of, for example, a multilayer wiring board (first wiring board) 1, a thin film sheet (thin film probe, first sheet) 2, a plunger 3, and the like. ing. The thin film sheet 2 is fixed to the lower surface (first surface) of the multilayer wiring substrate 1 by a pressing ring (first fixing jig) 4, and the plunger 3 is attached to the upper surface of the multilayer wiring substrate 1. An opening 5 is provided at the center of the multilayer wiring board 1, and the thin film sheet 2 and the plunger 3 are bonded to each other through an adhesive ring 6 in the opening 5. In FIG. 1, an area corresponding to a chip (chip area) 10 to be probed, which will be described in detail later, is indicated by a dotted line.

  On the lower surface of the thin film sheet 2, for example, a plurality of probes 7 having a quadrangular pyramid shape or a quadrangular pyramid trapezoid shape are formed. In the thin film sheet 2, a plurality of wirings (second wirings) that are electrically connected to each of the probes (contact terminals) 7 and extend from each probe 7 to the probe portion of the thin film sheet 2 are formed. . A plurality of receiving portions (not shown) that are in electrical contact with the ends of the plurality of wirings are formed on the lower surface of the multilayer wiring substrate 1, and the plurality of receiving portions are formed in the multilayer wiring substrate 1. The plurality of pogo (POGO) seats 8 provided on the upper surface of the multilayer wiring board 1 are electrically connected to each other through wiring (first wiring) formed on the wiring board 1. The pogo seat 8 has a function of receiving a pin for introducing a signal from the tester to the probe card.

  In the first embodiment, the thin film sheet 2 is formed of a thin film mainly composed of polyimide, for example. Since such a thin film sheet 2 has flexibility, in the first embodiment, in order to bring all the probes 7 into contact with the pads of the chip (semiconductor integrated circuit device), the region where the probes 7 are formed (first The plunger 3 is configured to press the thin film sheet 2 in one region from the upper surface (back surface) via a pressing tool (pressing mechanism) 9. That is, a constant pressure is applied to the pressing tool 9 by the elastic force of the spring 3 </ b> A disposed in the plunger 3. In the first embodiment, the alloy of the pressing tool 9 can be exemplified by 42 alloy.

  As shown in FIG. 1, the pressing tool 9 and a metal sheet 45 described in detail later are arranged on the plane so as to surround the chip 10. The metal sheet 45 has substantially the same planar shape as the pressing tool 9 and is disposed between the pressing tool 9 and the thin film sheet 2. Further, the adhesive ring 6 is disposed so as to surround the pressing tool 9 and the metal sheet 45 inside the pressing ring 4. The bonding portion between the bonding ring 6 and the thin film sheet 2 is a position protruding from the lower surface of the multilayer wiring board 1, and the position corresponding to the chip 10 of the thin film sheet 2 on which the contact terminals 7 are further formed is the pressing tool 9. By pressing, the position corresponding to the chip 10 of the thin film sheet 2 on which the contact terminal 7 is formed can be reliably projected to the lower surface of the multilayer wiring board 1. Moreover, tension is applied to the thin film sheet 2 by pressing from the pressing tool 9, and the thin film sheet is stretched by this tension, and the positions of the contact terminals 7 and the pads on the corresponding chip main surface can be aligned.

  At the time of the probe inspection, the pressing tool 9 having a flat pressing surface presses the thin film sheet 2 in the region where the probe 7 is formed from the back surface opposite to the main surface where the probe 7 is formed. By this pressing, the thin film sheet 2 moves in the outer peripheral direction of the pressing surface of the pressing tool 9 while receiving the frictional resistance from the pressing tool 9. At this time, the tension distribution of the thin film sheet 2 from the center to the outer peripheral direction changes abruptly around the outer peripheral portion of the pressing surface of the pressing tool 9, so that the thin film is in a portion where the tension is weak or the portion where the out-of-plane deformation synthesis is weak. The sheet 2 is deformed out of the plane and becomes unstable such as wrinkles. In particular, the frictional force between the pressing tool 9 and the thin film sheet 2 increases at the outer peripheral portion of the pressing surface of the pressing tool 9, and the remaining portion of the thin film sheet 2 can move in the outer peripheral direction of the pressing surface of the pressing tool 9. In some cases, the thin film sheet 2 is further deformed. When such a deformation occurs, the tension is reduced at the deformed portion. Therefore, the probe 7 existing in the vicinity of the outer peripheral portion of the pressing surface of the pressing tool 9 is affected by the deformation of the thin film sheet 2, and the pad There is a possibility that the contact pressure between 11 and 12 will be far from the desired state. In such a state, the electrical contact resistance of the contact portion between the probe 7 and the pads 11 and 12 becomes large, and it becomes impossible to accurately test the electrical resistance of the circuit inside the chip. In addition, when the deformation of the thin film sheet 2 is large, the alignment between the probe 7 and the corresponding pads 11 and 12 cannot be performed.

  In the first embodiment, as an object to be subjected to probe inspection (electrical inspection) using the probe card, a chip on which an LCD (Liquid Crystal Display) driver is formed can be exemplified. FIG. 3 illustrates a plane of the chip (chip region) 10 and a part thereof enlarged. The chip 10 is made of, for example, a single crystal silicon substrate, and an LCD driver circuit is formed on the main surface thereof. In addition, a large number of pads (first electrodes) 11 and 12 that are electrically connected to the LCD driver circuit are arranged on the periphery of the main surface of the chip 10, and the upper long side of the chip 10 in FIG. The pads 11 arranged along both short sides serve as output terminals, and the pads 12 arranged along the lower long sides of the chip 10 serve as input terminals. Since the number of output terminals of the LCD driver is larger than the number of input terminals, the pads 11 are arranged in two rows along the upper long side and both short sides of the chip 10 in order to widen the interval between adjacent pads 11 as much as possible. The pads 11 in the respective rows are arranged alternately along the upper long side and both short sides of the chip 10. In the first embodiment, the pitch LP at which the adjacent pads 11 are arranged is, for example, about 68 μm. Further, in the first embodiment, the pad 11 is a planar rectangle, the length LA of the long side extending in the direction intersecting (orthogonal) with the outer periphery of the chip 10 is about 63 μm, and along the outer periphery of the chip 10. The length LB of the short side that extends is about 34 μm. Further, since the pitch LP where the adjacent pads 11 are arranged is about 68 μm and the length LB of the short side of the pads 11 is about 34 μm, the interval between the adjacent pads 11 is about 34 μm.

  The pads 11 and 12 are bump electrodes formed of, for example, Au (gold), and are formed on the input / output terminals (bonding pads) of the chip 10 by a method such as electrolytic plating, electroless plating, vapor deposition, or sputtering. Is. FIG. 4 is a perspective view of the pad 11. The height LC of the pad 11 is about 15 μm, and the pad 12 has the same height.

  Further, the chip 10 forms an LCD driver circuit (semiconductor integrated circuit) and input / output terminals (bonding pads) using a semiconductor manufacturing technique in a large number of chip regions partitioned on the main surface of the wafer, and then inputs / output terminals. After the pads 11 are formed by the above method, the wafer can be diced to divide the chip area into pieces. In the first embodiment, the probe inspection is performed on each chip area before dicing the wafer. In the following description of the probe inspection (the step in which the pads 11 and 12 and the probe 7 are in contact), unless otherwise specified, the chip 10 indicates each chip area before dicing the wafer.

  FIG. 5 is a cross-sectional view of a principal part showing a method for connecting the chip 10 to the liquid crystal panel. As shown in FIG. 5, the liquid crystal panel is disposed so as to face the glass substrate 16 through the glass substrate 16 having the pixel electrodes 14 and 15 formed on the main surface, the liquid crystal layer 17, and the liquid crystal layer 17, for example. It is formed from a glass substrate 18 or the like. In the first embodiment, the chip 10 is face-down bonded to the pixel electrodes 14 and 15 of the glass substrate 16 of the liquid crystal panel so that the pads 11 and 12 are connected to the chip 10, respectively. The connection to can be illustrated.

  FIG. 6 is an enlarged plan view of a main part showing a part of the area on the lower surface of the thin film sheet 2 where the probe 7 is formed. FIG. 7 is a cross-sectional view of the main part along the line BB in FIG. FIG. 8 is a cross-sectional view of an essential part taken along line CC in FIG.

  The probe 7 is a part of the metal films 21A and 21B patterned into a planar hexagonal shape in the thin film sheet 2, and a tetragonal pyramid or a quadrangular pyramid trapezoid is formed on the lower surface of the thin film sheet 2 of the metal films 21A and 21B. It is the part that pops out into the mold. The probes 7 are arranged on the main surface of the thin film sheet 2 in accordance with the positions of the pads 11 and 12 formed on the chip 10, and FIG. 6 shows the arrangement of the probes 7 corresponding to the pads 11. Among these probes 7, the probe 7 </ b> A corresponds to the pad 11 in an array (hereinafter referred to as the first row) that is relatively close to the outer periphery of the chip 10 among the pads 11 arranged in two rows, and the probe 7 </ b> B is Of the pads 11 arranged in two rows, the pads 11 correspond to the pads 11 that are relatively far from the outer periphery of the chip 10 (hereinafter referred to as the second row). Further, the distance between the probe 7A and the probe 7B present at the closest position is defined by the distance LX in the left-right direction and the distance LY in the up-down direction on the paper surface illustrated in FIG. This is about 34 μm, which is half of the pitch LP where the matching pads 11 are arranged. In the first embodiment, the distance LY is about 93 μm. Further, as shown in FIG. 9, the height LZ (needle height) from the surface of the polyimide film 22 to the tips of the probes 7A and 7B is 50 μm or less (at most 90 μm or less), more preferably 30 μm or less. ing.

  The metal films 21A and 21B are formed, for example, by sequentially laminating a rhodium film and a nickel film from the lower layer. A polyimide film 22 is formed on the metal films 21A and 21B, and wirings (second wirings) 23 that are electrically connected to the metal films 21A and 21B are formed on the polyimide film 22. The wiring 23 is in contact with the metal films 21 </ b> A and 21 </ b> B at the bottom of the through hole 24 formed in the polyimide film 22. A polyimide film 25 is formed on the polyimide film 22 and the wiring 23.

  As described above, a part of the metal films 21A and 21B becomes the probes 7A and 7B formed in a quadrangular pyramid shape or a quadrangular pyramid trapezoidal shape, and a through hole 24 reaching the metal films 21A and 21B is formed in the polyimide film 22. The Therefore, if the planar pattern of the metal film 21A and the through hole 24 in which the probe 7A is formed and the planar pattern of the metal film 21B and the through hole 24 in which the probe 7B is formed are arranged in the same direction, they are adjacent to each other. There is a concern that the metal film 21A and the metal film 21B come into contact with each other, so that independent input / output cannot be obtained from the probes 7A and 7B. Therefore, in the first embodiment, as shown in FIG. 6, the planar pattern of the metal film 21B and the through hole 24 where the probe 7B is formed is the same as the planar pattern of the metal film 21A and the through hole 24 where the probe 7A is formed. Is a pattern rotated by 180 °. Thereby, a wide area of the metal film 21A in which the probe 7A and the through hole 24 are arranged in a plane and a wide area of the metal film 21B in which the probe 7B and the through hole 24 are arranged in a plane are left and right in the drawing. Are not arranged on the straight line, and the planarly tapered regions of the metal film 21A and the metal film 21B are arranged on the straight line in the left-right direction on the paper surface. As a result, it is possible to prevent a problem that the adjacent metal film 21A and the metal film 21B come into contact with each other. Even if the pads 11 (see FIG. 3) are arranged at a narrow pitch, the probes 7A and 7B can be arranged at positions corresponding to the pads 11 (see FIG. 3).

  In the first embodiment, the case where the pads 11 are arranged in two rows has been described with reference to FIG. 3, but there are also chips arranged in one row as shown in FIG. Such a chip can be dealt with by using a thin film sheet 2 in which the wide region of the metal film 21A is arranged on a straight line in the horizontal direction of the paper as shown in FIG. Further, the pads 11 are arranged in a row in this way, and the length LA of the long side extending in the direction intersecting (orthogonal to) the outer periphery of the chip 10 is about 140 μm, and extends along the outer periphery of the chip 10. FIG. 3 shows a case where the short side length LB is about 19 μm, the pitch LP where the adjacent pads 11 are arranged is about 34 μm, and the interval between the adjacent pads 11 is about 15 μm. Since the long side is about twice or more compared to the pad 11 and the center position of the pad 11 in the short side direction can be aligned with the center position of the pad 11 shown in FIG. 3, FIGS. The thin film sheet 2 described above can be used, and the probes 7A and 7B come into contact with the pad 11 at the positions POS1 and POS2 shown in FIG.

  In addition, when the number of pads 11 is larger, the pads 11 may be arranged in three or more rows. 13 is a plan view of a main part of the thin film sheet 2 corresponding to the pads 11 arranged in three rows, and FIG. 14 is a plan view of a main portion of the thin film sheet 2 corresponding to the pads 11 arranged in four rows. If the size of the chip 10 is the same, the distance LX described with reference to FIG. 6 is further reduced as the number of pads 11 arranged increases, so that the metal film including the metal films 21A and 21B comes into contact. There is further concern. Therefore, as shown in FIGS. 13 and 14, the metal films 21A, 21B, 21C, and 21D are obtained by, for example, rotating the planar pattern of the metal film 21A shown in FIG. , 21B, 21C, 21D can be prevented from contacting each other. Moreover, although the example which rotated the plane pattern of the metal film 21A shown in FIG. 6 45 degrees was demonstrated here, it is not limited to 45 degrees, The mutual contact of metal film 21A, 21B, 21C, 21D is carried out. Other rotation angles may be used as long as they can be prevented. The metal film 21C is provided with a probe 7C corresponding to the pad 11 disposed inside the chip 10 further than the pad 11 to which the probe 7B corresponds, and the metal film 21D has a pad 11 to which the probe 7C corresponds. Further, a probe 7D corresponding to the pad 11 arranged inside the chip 10 is formed.

  Here, FIG. 15 is a fragmentary sectional view taken along line DD in FIG. 14, and FIG. 16 is a fragmentary sectional view taken along line EE in FIG. As shown in FIG. 14, when the metal films 21 </ b> A to 21 </ b> D having the probes 7 </ b> A to 7 </ b> D corresponding to the four rows of pads 11 are arranged, wirings that are electrically connected to the metal films 21 </ b> A to 21 </ b> D from the upper layer, respectively. It is difficult to form all of the above with the same wiring layer. This is because when the distance LX is reduced, the metal films 21A to 21D may be brought into contact with each other, and wirings electrically connected to the metal films 21A to 21D may be brought into contact with each other. is there. Therefore, in the first embodiment, as shown in FIGS. 15 and 16, it can be exemplified that these wirings are formed from two wiring layers (wirings 23 and 26). A polyimide film 27 is formed on the wiring 26 and the polyimide film 25. The relatively lower wiring 23 is in contact with the metal films 21A and 21C at the bottom of the through hole 24 formed in the polyimide film 22, and the relatively upper wiring 26 is a through hole 28 formed in the polyimide films 22 and 25. In contact with the metal films 21B and 21D. As a result, in the same wiring layer, it is possible to ensure a large interval between the adjacent wirings 23 or 26, thereby preventing a problem that the adjacent wirings 23 or 26 are in contact with each other. In addition, when the pads 11 have five or more rows and the number of probes corresponding to the pads 11 increases and the distance LX becomes narrow, the wiring interval may be widened by forming wiring layers in multiple layers.

  Next, the structure of the thin film sheet 2 of the first embodiment will be described with reference to FIGS. 17 to 25 are cross-sectional views of the main part during the manufacturing process of the thin film sheet 2 having the probes 7A and 7B corresponding to the two rows of pads 11 (see FIG. 3) described with reference to FIGS. .

  First, as shown in FIG. 17, a wafer 31 made of silicon having a thickness of about 0.2 mm to 0.6 mm is prepared, and a silicon oxide film 32 having a thickness of about 0.5 μm is formed on both surfaces of the wafer 31 by a thermal oxidation method. Form. Subsequently, the silicon oxide film 32 on the main surface side of the wafer 31 is etched using the photoresist film as a mask, and an opening reaching the wafer 31 is formed in the silicon oxide film 32 on the main surface side of the wafer 31. Next, using the remaining silicon oxide film 32 as a mask, the wafer 31 is anisotropically etched using a strong alkali aqueous solution (for example, potassium hydroxide aqueous solution), so that the main surface of the wafer 31 is surrounded by the (111) plane. A quadrangular pyramid type or quadrangular pyramid shaped hole 33 is formed.

  Next, as shown in FIG. 18, the silicon oxide film 32 used as a mask when forming the hole 33 is removed by wet etching using a mixed solution of hydrofluoric acid and ammonium fluoride. Subsequently, a silicon oxide film 34 having a thickness of about 0.5 μm is formed on the entire surface of the wafer 31 including the inside of the hole 33 by performing a thermal oxidation process on the wafer 31. Next, a conductive film 35 is formed on the main surface of the wafer 31 including the inside of the hole 33. The conductive film 35 can be formed, for example, by sequentially depositing a chromium film having a thickness of about 0.1 μm and a copper film having a thickness of about 1 μm by a sputtering method or a vapor deposition method. Next, a photoresist film is formed on the conductive film 35, and the photoresist film in a region where the metal films 21A and 21B (see FIGS. 6 to 8) are formed in a later process by a photolithography technique is removed. An opening is formed.

  Next, a conductive film 37 and a conductive film 38 having high hardness are sequentially deposited on the conductive film 35 appearing at the bottom of the opening of the photoresist film by an electrolytic plating method using the conductive film 35 as an electrode. . In the first embodiment, the conductive film 37 may be a rhodium film and the conductive film 38 may be a nickel film. Through the steps so far, the above-described metal films 21A and 21B can be formed from the conductive films 37 and 38. Further, the conductive films 37 and 38 in the hole 33 become the above-described probes 7A and 7B. The conductive film 35 is removed in a later step, which will be described later.

  In the metal films 21 </ b> A and 21 </ b> B, when the above-described probes 7 </ b> A and 7 </ b> B are formed in a later process, the conductive film 37 formed from the rhodium film becomes the surface, and the conductive film 37 is in direct contact with the pad 11. become. For this reason, it is preferable to select a material having high hardness and excellent wear resistance as the conductive film 37. Further, since the conductive film 37 is in direct contact with the pad 11, if the chips 11 scraped by the probes 7 </ b> A and 7 </ b> B adhere to the conductive film 37, a cleaning process is required to remove the chips, and the probe inspection process. There is a concern that it will extend. Therefore, as the conductive film 37, it is preferable to select a material to which the material forming the pad 11 is difficult to adhere. Therefore, in Embodiment 1, a rhodium film that satisfies these conditions is selected as the conductive film 37. Thereby, the cleaning process can be omitted.

  Next, after removing the photoresist film used to form the metal films 21A and 21B (conductive films 37 and 38), the metal films 21A and 21B and the conductive film 35 are covered as shown in FIG. Thus, a polyimide film 22 (see also FIGS. 7 and 8) is formed. Subsequently, the aforementioned through hole 24 reaching the metal films 21 </ b> A and 21 </ b> B is formed in the polyimide film 22. The through hole 24 can be formed by drilling using a laser or dry etching using an aluminum film as a mask.

  Next, as shown in FIG. 20, a conductive film 42 is formed on the polyimide film 22 including the inside of the through hole 24. The conductive film 42 can be formed, for example, by sequentially depositing a chromium film having a thickness of about 0.1 μm and a copper film having a thickness of about 1 μm by a sputtering method or a vapor deposition method. Subsequently, after a photoresist film is formed on the conductive film 42, the photoresist film is patterned by a photolithography technique, and an opening reaching the conductive film 42 is formed in the photoresist film. Next, a conductive film 43 is formed on the conductive film 42 in the opening by plating. In the first embodiment, as the conductive film 43, a copper film, or a laminated film in which a copper film and a nickel film are sequentially deposited from the lower layer can be exemplified.

  Next, after removing the photoresist film, the conductive film 42 is etched using the conductive film 43 as a mask, thereby forming the wiring 23 composed of the conductive films 42 and 43. The wiring 23 can be electrically connected to the metal films 21 </ b> A and 21 </ b> B at the bottom of the through hole 24.

  Next, as shown in FIG. 21, the polyimide film 25 described above is formed on the main surface of the wafer 31. The polyimide film 25 functions as an adhesive layer for a metal sheet that is fixed to the main surface of the wafer 31 in a later step.

Next, as shown in FIG. 22, a metal sheet (second fixing jig) 45 is fixed to the upper surface of the polyimide film 25. As the metal sheet 45, a material having a low linear expansion coefficient and close to the linear expansion coefficient of the wafer 31 formed of silicon is selected. In the first embodiment, for example, 42 alloy (42% nickel and iron Examples include 58% alloy with a linear expansion coefficient of 4 ppm / ° C. or Invar (36% nickel and 64% iron with a linear expansion coefficient of 1.5 ppm / ° C.). Further, instead of using the metal sheet 45, a silicon film made of the same material as the wafer 31 may be formed, or a material having a linear expansion coefficient similar to that of silicon, for example, an alloy of iron, nickel and cobalt, or ceramic A mixed material with resin may be used. In order to fix such a metal sheet 45, the metal sheet 45 is superposed while being aligned with the main surface of the wafer 31, and heated at a temperature equal to or higher than the glass transition temperature of the polyimide film 25 while being pressurized at about 10 to 200 kgf / cm ^2. This can be realized by performing heating and pressure bonding.

  By fixing such a metal sheet 45 using the polyimide film 25, the strength of the thin film sheet 2 to be formed can be improved. Further, when the metal sheet 45 is not fixed, the relative positions of the probes 7A and 7B and the corresponding pads 11 are caused by the expansion or contraction of the thin film sheet 2 and the inspection target wafer due to the temperature at the time of probe inspection. There is a concern that the probes 7A and 7B will not be able to contact the corresponding pads 11 due to displacement. On the other hand, according to the first embodiment, since the metal sheet 45 is fixed, the expansion amount or the contraction amount of the thin film sheet 2 and the inspection target wafer due to the temperature during the probe inspection can be made uniform. Thereby, it is possible to prevent the relative positions of the probes 7A and 7B and the corresponding pads 11 from shifting. That is, it is possible to always keep electrical contact between the probes 7A and 7B and the corresponding pad 11 regardless of the temperature during probe inspection. In addition, it is possible to secure a relative position system between the thin film sheet 2 and the inspection target wafer under various circumstances.

  Next, the metal sheet 45 is etched using a photoresist film patterned by the photolithography technique as a mask to form an opening 46 in the metal sheet 45 on the probes 7A and 7B. In the first embodiment, this etching can be spray etching using a ferric chloride solution.

  Next, after removing the photoresist film, an elastomer 48 is formed in the opening 46 as shown in FIG. At this time, the elastomer 48 is formed so that a predetermined amount goes out to the upper part of the opening 46. In the first embodiment, examples of a method for forming the elastomer 48 include a method of printing or applying a dispenser with an elastic resin in the opening 46, or a method of installing a silicon sheet. The elastomer 46 absorbs variations in the heights of the tips of the individual probes 7A and 7B by local deformation while mitigating the impact when the tips of the multiple probes 7A and 7B come into contact with the pad 11. The contact between the probes 7A and 7B and the pad 11 is realized by uniform biting in accordance with the variation in height.

  Next, as shown in FIG. 24, the silicon oxide film 34 on the back surface of the wafer 31 is removed by etching using a mixed solution of hydrofluoric acid and ammonium fluoride, for example. Subsequently, the wafer 31 which is a mold material for forming the thin film sheet 2 is removed by etching using a strong alkaline aqueous solution (for example, potassium hydroxide aqueous solution). Next, the silicon oxide film 34 and the conductive film 35 are sequentially removed by etching. At this time, the silicon oxide film 34 is etched using a mixed solution of hydrofluoric acid and ammonium fluoride, and the chromium film contained in the conductive film 35 is etched using a potassium permanganate aqueous solution and contained in the conductive film 35. The copper film to be etched is etched using an alkaline copper etchant. Through the steps so far, the rhodium film, which is the conductive film 37 (see FIG. 18) forming the probes 7A and 7B, appears on the surfaces of the probes 7A and 7B. As described above, in the probes 7A and 7B having the rhodium film formed on the surface, Au or the like, which is the material of the pad 11 that the probes 7A and 7B are in contact with, is less likely to adhere, has a higher hardness than Ni, and is not easily oxidized. Contact resistance can be stabilized.

  Next, as shown in FIG. 25, the pressing tool 9 formed of 42 alloy, for example, is bonded onto the elastomer 48 to manufacture the thin film sheet 2 of the first embodiment.

  The thin film sheet 2 according to the first embodiment manufactured by the above-described steps can improve the rigidity when the metal sheet 45 is bonded.

  Here, the pressing tool 9 and the pressing ring 4 according to the first embodiment will be described with reference to FIGS.

  At the time of the probe inspection, the pressing tool 9 having a flat pressing surface presses the thin film sheet 2 in the region where the probe 7 is formed from the back surface opposite to the main surface where the probe 7 is formed. By this pressing, the thin film sheet 2 moves in the outer peripheral direction of the pressing surface of the pressing tool 9 while receiving the frictional resistance from the pressing tool 9. At this time, the tension distribution of the thin film sheet 2 from the center to the outer peripheral direction changes abruptly around the outer peripheral portion of the pressing surface of the pressing tool 9, so that the thin film is in a portion where the tension is weak or the portion where the out-of-plane deformation synthesis is weak. The sheet 2 is deformed out of the plane and becomes unstable such as wrinkles. In particular, the frictional force between the pressing tool 9 and the thin film sheet 2 increases at the outer peripheral portion of the pressing surface of the pressing tool 9, and the remaining portion of the thin film sheet 2 can move in the outer peripheral direction of the pressing surface of the pressing tool 9. In some cases, the thin film sheet 2 is further deformed. When such a deformation occurs, the tension is reduced at the deformed portion. Therefore, the probe 7 existing in the vicinity of the outer peripheral portion of the pressing surface of the pressing tool 9 is affected by the deformation of the thin film sheet 2, and the pad There is a possibility that the contact pressure between 11 and 12 will be far from the desired state. In such a state, the electrical contact resistance of the contact portion between the probe 7 and the pads 11 and 12 becomes large, and it becomes impossible to accurately test the electrical resistance of the circuit inside the chip. In addition, when the deformation of the thin film sheet 2 is large, the alignment between the probe 7 and the corresponding pads 11 and 12 cannot be performed.

  Therefore, in the first embodiment, the contours of the pressing tool 9 and the metal sheet 45 in the plane are assumed to be along the contour of the inner periphery of the pressing ring 4. That is, as shown in FIG. 26, when the inner peripheral contour (second contour) 4A of the pressing ring 4 is circular, the respective contours (first contour) 9A of the pressing tool 9 and the metal sheet 45 are used. The contour (third contour) 45A is made circular along the contour 4A. Thereby, even if the thin film sheet 2 is pressed by the pressing tool 9, a uniform tension distribution is generated in the thin film sheet 2 and local stress can be prevented from acting. That is, since the out-of-plane deformation of the thin film sheet 2 occurs uniformly, deformation such as generation of wrinkles can be prevented. As a result, the probe 7 and the pads 11 and 12 can be reliably and stably brought into contact with each other, and the contact pressure between the probe 7 and the pads 11 and 12 can be set to a desired state. It is possible to prevent an increase in the electrical contact resistance of the contact portion with 11 and 12 and to perform an accurate inspection of the electrical resistance of the circuit inside the chip.

  Moreover, according to this Embodiment 1, even if the thin film sheet 2 is pressed with the pressing tool 9, it can prevent that a uniform tension distribution generate | occur | produces in the thin film sheet 2, and a local stress acts. When the thin film sheet 2 is pressed by the pressing tool 9, the out-of-plane deformation of each probe 7 can be made uniform. Furthermore, it is possible to prevent wrinkles and the like from being generated on the thin film sheet 2 when the thin film sheet 2 is pressed by the pressing tool 9. As a result, alignment between the probes 7 and the corresponding pads 11 and 12, adjustment of contact pressure, and the like can be performed efficiently in a short time. Thereby, the efficiency of probe inspection can be improved.

  Further, with the above configuration, the performance margin of the probe card according to the first embodiment can be ensured. Thereby, the production yield of the semiconductor integrated circuit device according to the first embodiment can be improved, and the manufacturing cost of the semiconductor integrated circuit device according to the first embodiment can be reduced.

  Even if only the contour 45A of the metal sheet 45 is circular, or the contours 9A and 45A of the pressing tool 9 and the metal sheet 45 are elliptical (see FIG. 27), it is effective with a difference in effect. Moreover, although illustration is abbreviate | omitted, also when the outline of the inner periphery of the holding | suppressing ring 4 is an ellipse, the same effect is acquired by making the outline of the pressing tool 9 and the metal sheet 45 circular or an ellipse. Can do.

  As shown in FIGS. 28 and 29, the pressing tool 9 and the metal sheet 45 are also provided when the planar shape of the pressing ring 4 is a polygon such as a rectangle (see FIG. 28) or a hexagon (see FIG. 29). The contours 9 </ b> A and 45 </ b> A are polygons along the contour 4 </ b> A on the inner periphery of the pressing ring 4. At this time, the corners 9B and 45B of the contours 9A and 45A of the pressing tool 9 and the metal sheet 45 are chamfered or gently curved. Thereby, even when the planar shape of the pressing ring 4 is a polygon, the stress acting locally on the thin film sheet 2 can be relaxed. Thereby, even when the planar shape of the pressing ring 4 is a polygon, the same effects as those described with reference to FIGS. 26 and 27 can be obtained. Moreover, since the corner | angular part 4B of the inner periphery outline of the holding | suppressing ring 4 is made into the shape where it was chamfered or made into the gentle curved surface, since the stress which acts on the thin film sheet 2 can further be relieve | moderated, more A great effect can be obtained.

  Further, even when a plurality of (for example, two) chips 10 are collectively inspected for probes, as shown in FIGS. 30 and 31, for example, in the configuration shown in FIGS. By adopting a layout in which the pressing tool 9 and the metal sheet 45 cover the plurality of chips 10 to be inspected, the same effects as those described with reference to FIGS. 26 and 27 can be obtained. Although illustration is omitted, this is the same even when the planar shape of the pressing ring 4 is a polygon.

(Embodiment 2)
FIG. 32 is a cross-sectional view of a main part of the probe card according to the second embodiment.

  The probe card of the second embodiment is obtained by adding an expansion mechanism 50 as shown in FIG. 32 to the configuration of the probe card described in the first embodiment. The expansion mechanism 50 is provided with a spherical body at the tip portion in contact with the thin film sheet 2 and pushes the thin film sheet 2 downward from above while keeping the friction between the thin film sheet 2 small and expands the thin film sheet 2 in the circumferential direction. It is the composition to do. Before the pressing tool 9 presses the thin film sheet 2, the expansion mechanism 50 expands the thin film sheet 2 to keep the area of the thin film sheet 2 in contact with the pressing tool 9 flat. Thereby, when the pressing tool 9 presses the thin film sheet 2, deformation such as generation of wrinkles in the thin film sheet 2 can be prevented more effectively than in the first embodiment. As a result, alignment between the probes 7 and the corresponding pads 11 and 12, adjustment of contact pressure, and the like can be performed more efficiently in a shorter time than in the first embodiment. Thereby, the probe inspection efficiency can be further improved as compared with the first embodiment.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The method for manufacturing a semiconductor integrated circuit device according to the present invention can be widely applied to, for example, a probe inspection process in a manufacturing process of a semiconductor integrated circuit device.

It is a principal part top view of the lower surface of the probe card which is one embodiment of this invention. It is sectional drawing along the AA line in FIG. It is a top view of the semiconductor chip of the object which carries out a probe test using the probe card which is one embodiment of the present invention. FIG. 4 is a perspective view of pads formed on the semiconductor chip shown in FIG. 3. FIG. 5 is a cross-sectional view of main parts showing a method for connecting the semiconductor chip shown in FIG. 4 to a liquid crystal panel. It is a principal part top view of the thin film sheet which forms the probe card which is one embodiment of this invention. It is sectional drawing along the BB line in FIG. It is sectional drawing along CC line in FIG. It is sectional drawing which expands and shows the principal part of the thin film sheet which forms the probe card which is one embodiment of this invention. It is a top view of the semiconductor chip of the object which carries out a probe test using the probe card which is one embodiment of the present invention. It is a principal part top view of the thin film sheet which forms the probe card which is one embodiment of this invention. It is a principal part top view which showed the position which a probe contacts on the bump electrode provided in the semiconductor chip of the object which carries out a probe test | inspection using the probe card which is one embodiment of this invention. It is a principal part top view of the thin film sheet which forms the probe card which is one embodiment of this invention. It is a principal part top view of the thin film sheet which forms the probe card which is one embodiment of this invention. It is sectional drawing along the DD line | wire in FIG. It is sectional drawing along the EE line in FIG. It is principal part sectional drawing explaining the manufacturing process of the thin film sheet which forms the probe card which is one embodiment of this invention. It is principal part sectional drawing in the manufacturing process of the thin film sheet following FIG. It is principal part sectional drawing in the manufacturing process of the thin film sheet following FIG. It is principal part sectional drawing in the manufacturing process of the thin film sheet following FIG. It is principal part sectional drawing in the manufacturing process of the thin film sheet following FIG. It is principal part sectional drawing in the manufacturing process of the thin film sheet following FIG. It is principal part sectional drawing in the manufacturing process of the thin film sheet following FIG. It is principal part sectional drawing in the manufacturing process of the thin film sheet following FIG. It is principal part sectional drawing in the manufacturing process of the thin film sheet following FIG. It is a principal part top view explaining the plane layout of the thin film sheet which forms the probe card which is one embodiment of this invention, a pressing ring, and a pressing tool. It is a principal part top view explaining the plane layout of the thin film sheet which forms the probe card which is one embodiment of this invention, a pressing ring, and a pressing tool. It is a principal part top view explaining the plane layout of the thin film sheet which forms the probe card which is one embodiment of this invention, a pressing ring, and a pressing tool. It is a principal part top view explaining the plane layout of the thin film sheet which forms the probe card which is one embodiment of this invention, a pressing ring, and a pressing tool. It is a principal part top view explaining the plane layout of the thin film sheet which forms the probe card which is one embodiment of this invention, a pressing ring, and a pressing tool. It is a principal part top view explaining the plane layout of the thin film sheet which forms the probe card which is one embodiment of this invention, a pressing ring, and a pressing tool. It is principal part sectional drawing of the probe card which is other embodiment of this invention.

Explanation of symbols

1 Multilayer wiring board (first wiring board)
2 Thin film sheet (thin film probe, first sheet)
3 Plunger 3A Spring 4 Holding ring (first fixing jig)
4A contour (second contour)
5 Opening 6 Adhesive Ring 7, 7A, 7B, 7C, 7D Probe (Contact Terminal)
8 Pogo seat 9 Pressing tool (pressing mechanism)
9A contour (first contour)
9B Corner 10 chip (chip area)
11, 12 Pad (first electrode)
14, 15 Pixel electrode 16, 18 Glass substrate 17 Liquid crystal layer 21A, 21B, 21C, 21D Metal film 22 Polyimide film 23 Wiring 24 Through hole 25 Polyimide film 26 Wiring 27 Polyimide film 28 Through hole 31 Wafer 32 Silicon oxide film 33 Hole 34 Silicon oxide films 35, 37, 38 Conductive films 42, 43 Conductive film 45 Metal sheet (second fixing jig)
45A contour (third contour)
45B Corner 46 Opening 48 Elastomer 50 Expansion Mechanism

Claims (12)

A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) Partitioned into a plurality of chip regions, a semiconductor integrated circuit is formed in each of the plurality of chip regions, and a plurality of first electrodes electrically connected to the semiconductor integrated circuit are formed on the main surface Preparing a semiconductor wafer;
(B) a first wiring board on which the first wiring is formed, a plurality of contact terminals for contacting the plurality of first electrodes, and a second wiring electrically connected to the plurality of contact terminals are formed; A first sheet in which the second wiring is electrically connected to the first wiring and the tips of the plurality of contact terminals are held on the first wiring substrate so as to face a main surface of the semiconductor wafer; A first fixing jig for fixing the first sheet to a first surface of the wiring board facing the first sheet; and a plane disposed inside the first fixing jig, wherein the first sheet includes the first sheet. A step of preparing a first card having a pressing mechanism that presses a first region formed with a plurality of contact terminals from the back surface;
(C) a step of performing electrical inspection of the semiconductor integrated circuit by bringing the tips of the plurality of contact terminals into contact with the plurality of first electrodes ;
First contour of the pressing mechanism prior Symbol stress from the first sheet to work, Ri shape der along the second contour of the inner side of the first fixture the stress exerted from the first sheet ,
In a plane, the first contour is configured to surround the first region;
In a plane, the second contour is configured to surround the first contour;
In the plane, the first sheet is uniformly arranged between the first outline and the second outline. The method of manufacturing a semiconductor integrated circuit device according to claim 1,
The first contour of the pressing mechanism and the second contour inside the first fixing jig are circular or elliptical. The method of manufacturing a semiconductor integrated circuit device according to claim 2,
In the step (c), the plurality of contact terminals are in contact with two or more of the chip regions,
The first contour of the pressing mechanism surrounds the two or more chip regions that are in contact with the plurality of contact terminals. The method of manufacturing a semiconductor integrated circuit device according to claim 1,
The first contour of the pressing mechanism and the second contour inside the first fixing jig are polygonal and the corners of the polygon are chamfered. The method of manufacturing a semiconductor integrated circuit device according to claim 1,
A second fixing jig for keeping the first region flat at a position corresponding to the first region is attached to the back surface of the first sheet,
The third contour of the second fixing jig has a shape along the second contour inside the first fixing jig on which the stress from the first sheet acts. In the manufacturing method of the semiconductor integrated circuit device according to claim 5,
In the step (c), the plurality of contact terminals are in contact with two or more of the chip regions,
The third contour of the second fixing jig surrounds the two or more chip regions that are in contact with the plurality of contact terminals. The method of manufacturing a semiconductor integrated circuit device according to claim 1,
In the plane, an expansion mechanism is disposed between the pressing mechanism and the first fixing jig,
The expansion mechanism extends the slackness of the first region of the first sheet by pressing the first sheet from the back surface, and then the pressing mechanism presses the first region of the first sheet from the back surface. A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) Partitioned into a plurality of chip regions, a semiconductor integrated circuit is formed in each of the plurality of chip regions, and a plurality of first electrodes electrically connected to the semiconductor integrated circuit are formed on the main surface Preparing a semiconductor wafer;
(B) a first wiring board on which the first wiring is formed, a plurality of contact terminals for contacting the plurality of first electrodes, and a second wiring electrically connected to the plurality of contact terminals are formed; A first sheet in which the second wiring is electrically connected to the first wiring and the tips of the plurality of contact terminals are held on the first wiring substrate so as to face a main surface of the semiconductor wafer; A first fixing jig for fixing the first sheet to a first surface of the wiring board facing the first sheet; and a plane disposed inside the first fixing jig, wherein the first sheet includes the first sheet. A step of preparing a first card having a pressing mechanism that presses a first region formed with a plurality of contact terminals from the back surface;
(C) a step of performing electrical inspection of the semiconductor integrated circuit by bringing the tips of the plurality of contact terminals into contact with the plurality of first electrodes ;
Before Symbol The the back of the first sheet, the second fixing tool to keep the first region flat in a position corresponding to the first region is attached,
The third contour of the second fixing jig, Ri shape der along the second contour of the inner side of the first fixture stress acts from the first sheet,
In a plane, the third contour is configured to surround the first region;
In a plane, the second contour is configured to surround the third contour;
In the plane, the first sheet is uniformly arranged between the third outline and the second outline. The method of manufacturing a semiconductor integrated circuit device according to claim 8.
The second outline inside the first fixing jig and the third outline of the second fixing jig are circular or elliptical. In the manufacturing method of the semiconductor integrated circuit device according to claim 9,
In the step (c), the plurality of contact terminals are in contact with two or more of the chip regions,
The third contour of the second fixing jig surrounds the two or more chip regions that are in contact with the plurality of contact terminals. The method of manufacturing a semiconductor integrated circuit device according to claim 8.
The second outline inside the first fixing jig and the third outline of the second fixing jig are polygonal and the corner portions of the polygon are chamfered. The method of manufacturing a semiconductor integrated circuit device according to claim 8.
In the plane, an expansion mechanism is disposed between the pressing mechanism and the first fixing jig,
The expansion mechanism extends the slackness of the first region of the first sheet by pressing the first sheet from the back surface, and then the pressing mechanism presses the first region of the first sheet from the back surface.

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