JP4744246B2 - Semiconductor mounting method - Google Patents

Description

The present invention relates to a semiconductor packaging method of a semiconductor device mounting a semiconductor chip on a printed wiring board.

  In recent years, bare chip mounting, in which a bare chip is mounted instead of a semiconductor package as an electronic component, has been used, and the mounting area has been greatly reduced. As shown in FIGS. 8A and 8B, the electrode pad 4 formed on the back surface of the semiconductor chip 3 is thermocompression-bonded to the conductor pattern 2 protruding from the printed wiring board 1, as shown in FIGS. It is joined with. Reference numeral 5 denotes a hole formed at the mounting position of the first and second semiconductor chips 3a and 3b on the printed wiring board 1.

In order to improve the mounting density, as shown in FIG. 9, the conductor pattern 2 protruding from the printed wiring board 1 is provided with an electrode pad 4a formed on the back surface of the first semiconductor chip 3a and a second semiconductor chip. It is also carried out by being sandwiched between electrode pads 4b formed on the back surface of 3b and bonded by thermocompression bonding.
Japanese Unexamined Patent Publication No. 64-77135

  Thus, conventionally, since the electrode pad of the semiconductor chip and the conductor pattern are bonded by thermocompression bonding, the conductor pattern must be plated with the same material as the electrode pad. Specifically, since the electrode pad is generally Au, it is necessary to apply Au plating to the conductor pattern, and the material price cannot be reduced.

In order to increase the mounting density according to the present invention, as shown in FIG. 9, an electrode pad formed on the back surface of the first semiconductor chip and an electrode pad formed on the back surface of the second semiconductor chip, when implementing across the conductive pattern protruding from, and to provide a semiconductor body implementation method can be expected to reduce the cost than before.

The semiconductor mounting method of the present invention includes a conductive pattern protruding from a printed wiring board with a gold electrode pad formed on the back surface of the first semiconductor chip and a gold electrode pad formed on the back surface of the second semiconductor chip. When mounting the electrode pad, after activating the surface of both electrode pads by irradiating with ultraviolet rays, the width between the electrode pads is different from the width of the electrode pads. The tip of one of the electrode pads is in contact with one surface of the conductor pattern, and the other surface of the conductor pattern is sandwiched between conductor patterns that are not narrow and plated with gold. When the tip of the other electrode pad of the two electrode pads is in contact with the conductor pattern, the one electrode pad and the other electrode pad are bonded by pressing the conductor pattern with the two electrode pads. Are pressed and deformed by the pressed conductor pattern, and the tip of the one electrode pad protruding from the conductor pattern and the tip of the other electrode pad are in contact with each other to wrap around the conductor pattern. It is characterized by making it.

  According to the present invention, the electrode pad formed on the back surface of the first semiconductor chip and the electrode pad formed on the back surface of the second semiconductor chip are brought into contact with each other, and the conductor of the printed wiring board is joined by both electrode pads. An electrical connection in which the pattern is sandwiched can be obtained.

Hereinafter, a semiconductor mounting method of the present invention will be described based on specific embodiments.
In addition, the same code | symbol is attached | subjected and demonstrated to what has the effect | action similar to FIG. 8, FIG. 9 which shows a prior art example.

(Embodiment 1)
1A to 1D show the steps of the semiconductor mounting method of the present invention, and FIGS. 2 and 3 show an enlarged cross-sectional view and a plan view of the finished semiconductor device.

  In FIG. 1A, ultraviolet rays UV are irradiated to the electrode pad 4a formed on the back surface of the first semiconductor chip 3a and the electrode pad 4b formed on the back surface of the second semiconductor chip 3b. Thus, the surfaces of the electrode pads 4a and 4b are activated. Here, the material of the electrode pads 4a and 4b was Au.

  In FIG. 1B, the conductor pattern 2 protruding from the printed wiring board 1 is centered and sandwiched between the electrode pad 4a of the first semiconductor chip 3a and the electrode pad 4b of the second semiconductor chip 3b. The conductor pattern 2 is made of a material harder than Au. Specifically, the conductor pattern 2 is made of a material harder than Au, such as Cu.

  In FIG.1 (c), a tool (not shown) is pressed on the back surface of the 1st, 2nd semiconductor chip 3a, 3b, and a heat | fever and the force of arrow F1, F2 are given. At this time, the electrode pads of the semiconductor chips 3a and 3b are on both sides 6 of the conductor pattern 2 as shown in FIG. 1D, and the electrodes of the electrode pads 4a and the second semiconductor chips 3b of the first semiconductor chip 3a. Pressing and heating are performed until the pad 4b comes into contact with the pad 4b and has sufficient mechanical strength, so that mechanical bonding and electrical bonding are realized simultaneously.

  When the width of the conductor pattern with both surfaces exposed is “a” and the height (thickness) is “c”, the width “b” of the electrode pads 4a and 4b is “a + 2c” and the height of the electrode pads 4a and 4b. The length d is preferably “2c” or more. Also, the conductive pattern with both surfaces of the wiring board sandwiched between them is made of a material harder than Au, such as Cu, and the deformation of the conductive pattern 2 due to the load at the time of crimping is the deformation of the electrode pads 4a and 4b of the semiconductor chip. Smaller than.

  According to this configuration, the conductor pattern 2 is sandwiched between the electrode pads 4a and 4b, and the electrode pads 4a and 4b are brought into contact with each other, so that the conductor pattern 2 is not subjected to processing such as Au plating. Also, a good bonding state can be obtained. Furthermore, since the conductor pattern 2 is wrapped by the electrode pads 4a and 4b, it can be made thinner by the thickness of the conductor pattern than in the prior art.

(Embodiment 2)
4A and 4B show (Embodiment 2) of the present invention.
In the above (Embodiment 1), the electrode pads 4a and 4b are configured to be wider than the conductor pattern 2, but in this embodiment, the electrode pads 4a and 4b are substantially the same in width as the conductor pattern 2. The notch 7 is formed from both sides to form the constricted portion 8 only at the mounting positions of the first and second semiconductor chips 3a and 3b in the conductor pattern 2, and the electrode pad 4a is formed by the pressurization and heating. , 4b are different only in that they are brought into contact with each other on both sides of the constricted portion 8.

(Embodiment 3)
FIG. 5 shows (Embodiment 3) of the present invention.
The electrode pads 4a and 4b in FIG. 4 have almost the same width as the conductor pattern 2, but in FIG. 5, only the width of the electrode pads 4a and 4b is larger than the width of the conductor pattern 2 (Embodiment 2). ) Is different.

(Embodiment 4)
FIG. 6 shows (Embodiment 4) of the present invention.
In the above (Embodiment 1), the electrode pads 4a and 4b are configured to be wider than the conductor pattern 2, but in this embodiment, the electrode pads 4a and 4b are substantially the same in width as the conductor pattern 2. A hole 9 is formed only at the mounting position of the first and second semiconductor chips 3a and 3b in the conductor pattern 2, and the electrode pads 4a and 4b come into contact with the inside of the hole 9 by the pressurization and heating. The only difference is that they are joined together.

(Embodiment 5)
FIG. 7 shows (Embodiment 5) of the present invention.
The electrode pads 4a and 4b in FIG. 6 have substantially the same width as the conductor pattern 2, but in FIG. 7, only the width of the electrode pads 4a and 4b is larger than the width of the conductor pattern 2 (Embodiment 4). ) Is different.

  With this configuration, the electrode pads 4a and 4b are brought into contact and bonded not only inside the hole 9 but also at the portion 6a protruding from both sides of the conductor pattern 2 by the pressurization and heating.

  4 and 5, the constricted portion 8 of the conductor pattern 2 is cut out from both sides of the conductive pattern 2. However, the constricted portion may be formed by cutting out from one side.

  The semiconductor device structure of the present invention can be mounted thinly and inexpensively when thin semiconductor chips are stacked and mounted, and can easily be reduced in height, and thus can be applied to a package in which semiconductors are stacked and mounted. .

Process drawing of semiconductor mounting method of the present invention AA enlarged sectional view of a completed semiconductor device Plan view of FIG. Plan view and BB enlarged sectional view of a semiconductor device according to (Embodiment 2) of the present invention The top view and CC expanded sectional view of the semiconductor device of (Embodiment 3) of this invention The top view and DD expanded sectional view of the semiconductor device of (Embodiment 4) of this invention The top view and EE expanded sectional view of the semiconductor device of (Embodiment 5) of this invention A plan view of a conventional semiconductor device and an enlarged sectional view thereof Expanded sectional view of another conventional example

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Printed wiring board 2 Conductor pattern 3a, 3b 1st, 2nd semiconductor chip 4a, 4b Electrode pad 5 Hole 7 formed in the mounting position of the semiconductor chip in the printed wiring board 1 Notch part 8 Narrow part 9 Conductor pattern Hole

Claims (3)

When mounting with the gold electrode pad formed on the back surface of the first semiconductor chip and the gold electrode pad formed on the back surface of the second semiconductor chip sandwiching the conductor pattern protruding from the printed wiring board,
After activating by irradiating the surface of both electrode pads with ultraviolet rays ,
Between the two electrode pads, smaller than the material width in rigid different materials than gold of both electrode pad width, across the conductor pattern surface is not plated with gold, one surface of the conductor pattern In the state where the tip of one of the electrode pads is in contact with the other electrode pad, and the tip of the other electrode pad of the two electrode pads is in contact with the other surface of the conductor pattern. By crimping the conductor pattern with an electrode pad, the one electrode pad and the other electrode pad are pressed and deformed by the pressed conductor pattern, and the one electrode pad protrudes from the conductor pattern. The semiconductor mounting method , wherein the tip and the tip of the other electrode pad are in contact with each other and wrap around the conductor pattern . The first in the conductive pattern, to form a narrower constricted portion than the width of the electrode pads on the bonding point of the second semiconductor chip, a semiconductor according to claim 1 Symbol placement joining both electrode pads to each other in said constricted portion Implementation method. First, by forming a hole in the junction point of the second semiconductor chip, a semiconductor packaging method of claim 1 Symbol placement joining the two electrode pads to each other in the hole in the conductor pattern.

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