JP4744470B2 - Histogram creation apparatus and method - Google Patents

Description

  The present invention relates to a histogram creation apparatus and method for creating a histogram using a memory.

  In an image processing system, when it is determined whether or not an input image is appropriately scaled to a usable density value range, the density value of input image data is calculated as a histogram.

  As a method for obtaining the histogram, a histogram memory for storing the number of data of the density value (frequency) corresponding to each density value of the image data is prepared in advance, and the image data is sequentially read from the image memory. Then, it is determined which density value the density value of the image data corresponds to. Then, the number of data (frequency) corresponding to the corresponding density value is read out, 1 is added to the frequency, and the result is written to the same address, thereby creating a histogram of the image data in the histogram memory.

A conventional histogram creation procedure will be described with reference to the flowchart of FIG. 1 and FIG.
When the address of the RAM from which data is read is input as input data in accordance with the input timing of the operation clock (step S1 / YES), the data at the corresponding address is read from the RAM in synchronization with the next rising edge of the operation clock (step S2). ). Next, 1 is added to the read data, and the added value is used as write data (step S3). The obtained write data is written into the RAM in synchronism with the rising timing of the next operation clock (step S4). This process is repeated for all pixels (step S5).

  Patent Document 1 discloses a method for converting the gradation of an image using a histogram.

JP 2001-154646 A

  However, as shown in FIG. 2, since reading data from the RAM and writing data to the RAM cannot be performed at the same time, a histogram could not be created for continuously input data. .

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a histogram creation apparatus and method capable of creating a histogram even for continuously input data.

Histogram forming apparatus of the present invention in order to achieve the above object, a plurality comprises memory means input and output terminals of the data, using the storage means, the histogram creation and a histogram generating means for generating a histogram of the input data In the apparatus, the histogram creation means includes: first determination means for determining whether or not the input data matches data input immediately before the input data; the input data; A second determination unit that determines whether or not the data input two times before the input data matches; a first holding unit that holds data to be stored in the storage unit; and the first Second holding means for further holding the data held by the holding means, wherein the histogram creating means determines that the first determining means is coincident. A histogram is created using the data held in the first holding unit, and when it is determined that the second determination unit matches, the histogram is held in the second holding unit. A histogram is created using data.
According to the present invention, even when data stored in the same storage area of the storage unit is continuously used to create a histogram, the histogram can be created accurately.

The histogram creation device may include an analysis unit that analyzes the histogram created by the histogram creation unit, and a correction unit that corrects input data according to the analysis result of the analysis unit.
Therefore, input data can be analyzed based on the created histogram.

The histogram creation method of the present invention is a histogram creation method for creating a histogram of input data using a storage means having a plurality of data input / output terminals . The input data and the input data are one before the input data. A first determination step for determining whether or not the input data matches, and a first determination step for determining whether or not the input data matches data input two times before the input data; 2 determination steps, a first holding step for holding data stored in the storage means in a first holding means, and a second holding of the data held in the first holding means in the first holding step. A second holding step held in the first holding means, and when it is determined that the two match in the first determination step, the data is stored using the data held in the first holding means. Create a ram, the second when it is determined that they match determination step is characterized by generating a histogram by using the data held in the second holding means.

  According to the present invention, it is possible to create a histogram even for continuously input data.

  The best embodiment of the present embodiment will be described with reference to the accompanying drawings.

  First, the configuration of the present embodiment will be described with reference to FIG. FIG. 3 shows a configuration of the electronic device 1 formed on one substrate. As shown in FIG. 3, the electronic device 1 includes a histogram creation unit 2, a dual port RAM 3, an image analysis unit 4, and an image correction unit 5.

  The histogram creation unit 2 creates a histogram of the input image data using the dual port RAM 3.

The dual port RAM 3 is a RAM provided with two signal input / output ports (ports) for data input / output. For example, the dual port RAM 3 is set by a write clock signal input to a first clock input terminal. the data input to the input port D _in in timing sequentially written into a predetermined storage area, and the stored data from the storage area sequentially at the timing set by the read clock signal input to the second clock input terminal Read and output to output port _Dout .

The image analysis unit 4 analyzes the image using the histogram created by the histogram creation unit 2.
The image correction unit 5 corrects the image based on the analysis result of the image analysis unit 4. For example, the histogram shown in FIG. 4A is created for each color component of the input image data, and correction is performed so that the density gradation of the image becomes 256 gradations from 0 to 255 as shown in FIG. 4B. I do. By performing such correction, color reproducibility can be improved.

  FIG. 5 shows the configuration of the histogram creation unit 2. As shown in FIG. 5, the histogram creation unit 2 includes a first FF (flip-flop) 21, a second FF22, a third FF23, a fourth FF24, a fifth FF (corresponding to the holding means of the present invention) 27, and a sixth FF (holding of the present invention). 30 (corresponding to the means), a first comparator (corresponding to the determining means of the present invention) 25, a second comparator (corresponding to the determining means of the present invention) 26, a selector 28, an adder 29, have.

The first FF 21 latches the read address (input data) input to the histogram creation unit 2. The read address latched by the first FF 21 is output to the second FF 22.
The second FF 22 latches the read address output from the first FF 21. The read address latched by the second FF 22 is output to the first comparator 25, the second comparator 26, and the third FF 23 as a read address (latch).

  The third FF 23 latches the read address (latch) output from the second FF 22. The read address (latch) stored in the third FF 23 is output as a write address to the dual port RAM 3 and also to the first comparator 25 and the fourth FF 24.

The fourth FF 24 latches the write address output from the third FF 23. Write address to store the first 4FF24 is output as Lai preparative address (latched) to the second comparator 26.

  The first comparator 25 compares the read address (latch) output from the second FF 22 with the write address output from the third FF 23. The first comparator 25 determines whether or not the input data (read address (latch)) matches the input data (write address) immediately before this input data. The first comparator 25 outputs a signal representing the comparison result to the selector 28.

  The second comparator 26 compares the read address (latch) output from the second FF 22 with the write address (latch) output from the fourth FF 24. The second comparator 26 determines whether or not the input data (read address (latch)) matches the input data two times before the input data (write address (latch)). The second comparator 26 outputs a signal representing the comparison result to the selector 28.

  In the selector 28, the read data read from the dual port RAM 3, the write data which is the output of the histogram creating unit 2 and is written to the dual port RAM 3, and the write output from the fifth FF 27 which latches the write data. Data (latch) and comparison results of the first comparator 25 and the second comparator 26 are input. The selector 28 selects any one of read data, write data, and write data (latch) based on the comparison result of the first comparator 25 and the second comparator 26 and outputs the selected data to the adder 29 in the subsequent stage. . The adder 29 adds 1 to the data output from the selector 28 and outputs the result to the sixth FF 30. The data latched in the sixth FF 30 is output to the dual port RAM 3 as write data.

The histogram creation procedure of the histogram creation unit 2 will be described with reference to FIG.
Since the histogram creation unit 2 is a functional unit that creates a histogram of image data, when a read address is input, the value of the data stored in the dual port RAM 3 at that address is read, and 1 is added to the read value. Write to the same address in the dual port RAM 3.

  A read address (input data) is input to the histogram creation unit 2 in synchronization with the falling edge of the operation clock (see FIG. 6A) indicating the operation timing. The histogram creation unit 2 latches this read address in the first FF 21. In the following description, the read address data to be input is “1, 3, 5, 7, 7, 7, 5, 7, 5, 3”, and is input to the histogram creation unit 2 in this order. And

  The second FF 22 latches the read address output from the first FF 21. The second FF 22 outputs the latched read address as a read address (latch) to the first comparator 25, the second comparator 26, and the third FF 23. FIG. 6C shows the read address (latch) output from the second FF 22. The read address (latch) is data delayed by one clock of the operation clock from the read address shown in FIG.

  FIG. 6D shows read data read from the dual port RAM 3 using the read address (latch). For example, in the example shown in FIG. 6, the data written to the read address (latch) [1] of the dual port RAM 3 is [5], and the data written to the read address (latch) [3] of the dual port RAM 3 Is [2].

  The third FF 23 latches the read address (latch) output from the second FF 22. The read address (latch) latched by the third FF 23 is output to the first comparator 25 and the fourth FF 24 as a write address. The write address output from the third FF 23 is supplied to the dual port RAM 3 as a write address of the dual port RAM 3. FIG. 6E shows the write address output from the third FF 23. The write address is data delayed by 2 clocks of the operation clock from the read address.

FIG. 6F shows data written to the dual port RAM 3 as write data. In order to create a histogram, 1 is added to the read data read from the dual port RAM 3, and the value is written to the same address of the dual port RAM 3 where the read data has been written.
The selector 28 selects data to be output to the adder 29 based on the comparison results of the first comparator 25 and the second comparator 26. Here, it is assumed that read data is selected by the selector 28 and output to the adder 29. The adder 29 adds 1 to the read data read from the dual port RAM 3 and outputs the result to the sixth FF 30. Data output from the sixth FF 30 is output to the dual port RAM 3 as write data.
FIG. 6G shows the data of the write address (latch) output to the second comparator 26 by the fourth FF 24 that latches the write address, and FIG. 6H shows the output of the fifth FF 27 that latches the write data. Write data (latch) is shown.

  The above is the processing when the read address continuously input is data that does not need to access the same address of the dual port memory.

Next, a case where the same read address is continuously input as shown in FIG. 6B will be described. In this case, since the same storage area of the dual port RAM 3 is continuously accessed, writing to the previous read data may not be completed when data is read according to the subsequent read address. In such a case, the write data may not be counted up correctly.
Therefore, the first comparator 25 determines whether or not the input data (read address (latch)) matches the previous input data (write address). In addition, the second comparator 26 determines whether or not the input data (read address (latch)) matches the previous input data (write address (latch)).

When the first comparator 25 detects a match between the read address (latch) and the write address immediately before this data, the selector 28 outputs the write data to the adder 29 as shown in FIG. The selector 28 is irrespective of the comparison result of the second comparator 2 6, when the comparison result of the first comparator 25 match, outputs the write data to the adder 29. In this case, since 1 is added to the write data, not the read data, an accurate value can be written to the corresponding address even when the same read address is read continuously. In the example shown in FIG. 6, the read address (latch) data [7, 7] shown in (C) and the write address data [7, 7] shown in (E) match. In this case, the write data is selected by the selector 28, and 1 is added to the write data as shown in (F).

  When the second comparator 26 detects a match between the read address (latch) and the write address (latch) two times before this data, the selector 28 outputs the write data (latch) to the adder 29. To do. Since 1 is added to the write data (latch) latched in the fifth FF 27 and this is output to the dual port RAM 3 as write data, the input data is the same as the previous input data. Even if it exists, an accurate value can be written in the corresponding address. In the example shown in FIG. 6, the read address (latch) data [7, 5] shown in (C) and the write address (latch) data [7, 5] shown in (G) match. In this case, write data (latch) is selected by the selector 28, and 1 is added to the write data latch as shown in (H) and (F).

The processing procedure of the histogram creation unit 2 will be described with reference to the flowchart shown in FIG.
When the read address is input as data (step S11), the first comparator 25 of the histogram creation unit 2 compares the read address (latch) output from the second FF 22 with the write address output from the third FF 23. (Step S12). When the read address (latch) and the write address which is the address immediately before this read address (latch) match (step S12 / YES), a signal indicating the match is output to the selector 28. Is done. When a signal indicating that the read address (latch) matches the write address is input to the selector 28, the selector 28 outputs write data that is the output of the histogram creation unit 2 to the adder 29. The adder 29 adds 1 to the previous write data, and this is output to the dual port RAM 3 as new write data.

If no match between the read address (latch) and the write address is detected (step S12 / NO), a signal indicating a mismatch between the two signals is input from the first comparator 25 to the selector 28.
The second comparator 26 receives a comparison result between the read address (latch) and the write address (latch) . When the read address (latch) and the write address (latch), which is the address two times before the read address (latch), are coincident (step S14 / YES), a signal indicating the coincidence of the two is displayed. 2 is output from the comparator 26 to the selector 28. When the signal indicating that the read address (latch) matches the write address (latch) is input to the selector 28, the selector 28 inputs the write data (latch), which is the output of the fifth FF 27, to the adder 29. Output. The adder 29 adds 1 to the write data (latch) that is the previous write data, and outputs this to the dual port RAM 3 as new write data.

  If the read address (latch) and the write address (latch) do not match (step S14 / NO), the second comparator 26 outputs a signal indicating the mismatch between the two to the selector 28. . When a signal indicating a mismatch is input from the first comparator 25 and the second comparator 26, the selector 28 selects read data and outputs it to the adder 29. The adder 29 adds 1 to the read data, and this is output to the dual port RAM 3 as new write data.

As described above, in this embodiment, the dual port RAM 3 can be used to create a histogram for data that is continuously input.
Further, even if the continuously input data is data designating the same address of the dual port RAM 3, accurate data can be written to the dual port RAM 3.

  The embodiment described above is a preferred embodiment of the present invention. However, the present invention is not limited to this, and various modifications can be made without departing from the scope of the present invention.

It is a flowchart which shows the conventional process sequence. It is a figure which shows the read-out timing of the data from the conventional dual port RAM, and the write-in timing. It is a figure which shows the structure of an electronic device. It is a figure for demonstrating the process of an image correction part. It is a figure which shows the structure of a histogram preparation part. It is a figure which shows the process sequence of a histogram preparation part. It is a figure which shows the comparison result of a 1st comparator and a 2nd comparator, and the selection output of the selector according to a comparison result. It is a flowchart which shows the process sequence of a histogram preparation part.

Explanation of symbols

1 Electronic Device 2 Histogram Generation Unit 3 Dual Port RAM
4 Image analysis unit 5 Image correction unit 21 1st FF
22 2nd FF
23 3rd FF
24 4th FF
25 1st comparator 26 2nd comparator 27 5th FF
28 Selector 29 Adder 30 6th FF

Claims (3)

A histogram creation device comprising storage means having a plurality of data input / output terminals and histogram creation means for creating a histogram of input data using the storage means ,
The histogram creation means includes: first determination means for determining whether or not the input data matches data input immediately before the input data; the input data; and the input data 2nd determination means for determining whether or not the data input two times before matches, a first holding means for holding data stored in the storage means, and holding by the first holding means Second holding means for further holding the data being stored,
The histogram creation means creates a histogram using the data held in the first holding means when the first determination means determines that they match, and the second determination means If it is determined that they match , a histogram creation apparatus is characterized in that a histogram is created using data held in the second holding means . Analyzing means for analyzing the histogram created by the histogram creating means;
Correction means for correcting input data according to the analysis result of the analysis means;
The histogram generating apparatus according to claim 1, wherein: A histogram creation method for creating a histogram of input data using storage means having a plurality of data input / output terminals ,
A first determination step for determining whether or not the input data matches the data input immediately before the input data;
A second determination step of determining whether or not the input data matches data input two times before the input data;
A first holding step for holding data stored in the storage means in a first holding means;
A second holding step for holding data held in the first holding means in the first holding step in a second holding means;
If it is determined in the first determination step that the data match, a histogram is created using the data held in the first holding means, and it is determined that the data matches in the second determination step. In this case, a histogram creation method is characterized in that a histogram is created using data held in the second holding means .

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