JP4760956B2 - Rotation detection device signal processing circuit - Google Patents

Description

  According to the present invention, when rectangular wave-shaped first and second sensor signals having different phases are output from a plurality of magnetic sensors arranged to face a rotating body on which gear teeth are formed, the first and second sensor signals are output. The present invention relates to a signal processing circuit of a rotation detection device that outputs a detection signal for detecting the rotation of a rotating body based on the sensor signal.

  As a signal processing circuit of a conventional rotation detection device, for example, one described in Patent Document 1 is known. The rotation detection device of Patent Document 1 includes two magnetic sensors that output rotation detection signals Sa and Sb having different phases when a rotor on which gear teeth are formed rotates. The signal processing circuit determines that the rotation direction of the rotor is reversed based on the change of the relative phases of the rotation detection signals Sa and Sb as shown in FIG. Extract edges.

  Then, a switching inactive signal is generated that prohibits switching of the signal level in synchronization with both the first rising edge and the first falling edge timing of the rotation detection signal Sa after the rotor reverse rotation determination. Based on this switching inactive signal, the first output signal OUT1 is generated and output by masking one pulse of the signal Sa immediately after the rotor reverse rotation determination. Further, based on the first output signal OUT1 and the reverse signal, when the rotor is rotating forward, the magnitude changes between two values of high and low, and when the rotor is rotating reversely, the high and middle A second output signal OUT2 whose magnitude changes between the two values is generated and output.

JP 2007-170922 A

  However, if one pulse of the rotation detection signal Sa immediately after the determination of the reverse rotation of the rotor is masked as in the prior art described above, the rotation of the rotor is accurately determined from the second output signal OUT2 that is finally generated and output. It may be difficult to detect well.

  For example, when switching of the rotation direction of the rotor is repeated in a short cycle, if one pulse of the rotation detection signal Sa after switching of the rotation direction is masked as in Patent Document 1, the switching of the rotation direction is repeated. During this time, the second output signal OUT2 remains unchanged. For this reason, the signal processing circuit of Patent Document 1 cannot detect the rotational movement of the rotor even though the rotor is actually rotating so as to repeatedly switch the rotation direction.

  The present invention has been made in view of the above-described points, and even when a rotating body repeatedly rotates in a short cycle so as to switch the rotating direction, a rotation that outputs a detection signal that can detect the rotating motion of the rotating body. An object of the present invention is to provide a signal processing circuit of a detection device.

In order to achieve the above object, the signal processing circuit of the rotation detection device according to claim 1 comprises:
Different from the plurality of magnetic sensors arranged opposite to the rotating body on which the gear teeth are formed, as the crests and troughs of the gear teeth move as the rotating body rotates in the forward or reverse direction. When a rectangular wave-shaped first and second sensor signal having a phase is output, a detection signal for detecting the rotational position of the rotating body is output based on the first and second sensor signals. There,
Based on the phase relationship between the first and second sensor signals, a rotation direction determination unit that determines whether the rotation direction of the rotating body is the forward rotation direction or the reverse rotation direction;
In one rotation direction, when the rotation direction of the rotating body is the normal rotation direction and when the rotation direction is the reverse rotation direction, the change of the first sensor signal due to the tip side edge of the peak portion in the one rotation direction is It is defined as a signal change due to an effective edge in one rotation direction, and in the other rotation direction, a change in the first sensor signal due to the rear end edge of the peak in the other rotation direction is effective in the other rotation direction. Effective edge determination means for determining whether or not the change in the first sensor signal is due to an effective edge, and determining that the signal is changed due to an edge
On the condition that the rotation direction discriminating means discriminates that the rotation direction is the normal rotation direction, and the effective edge discrimination means discriminates that the change in the first sensor signal is due to the effective edge, the rotating body rotates forward. Forward rotation pulse output request holding means for holding a forward rotation pulse output request signal indicating rotation in the direction;
On the condition that the rotation direction discriminating means discriminates that the rotation direction is the reverse rotation direction, and the effective edge discrimination means discriminates that the change of the first sensor signal is due to the effective edge, the rotating body moves in the reverse rotation direction. A reverse pulse output request holding means for holding a reverse pulse output request signal indicating that it is rotating;
When the output request signal is held in either the forward pulse output request holding means or the reverse pulse output request holding means, the held output request signal is output, and the forward pulse output request holding means is reversely rotated. When the output request signal is held in one of the pulse output request holding means and the other is held in the other, until the output request signal held in one is reset Output request signal output means for waiting for output of the output request signal received,
In accordance with the output request signal output from the output request signal output means, pulse output means for outputting a forward pulse signal or a reverse pulse signal as a detection signal;
After the output of the forward rotation pulse signal or the reverse rotation pulse signal by the pulse output means, the forward rotation pulse or reverse rotation that is held in one of the normal rotation pulse output request holding means and the reverse rotation pulse output request holding means and whose output has ended. First reset means for resetting a pulse output request signal;
While the output request signal is held in one of the forward pulse output request holding means and the reverse pulse output request holding means, the output request signal is also held in the other, and the output request already held in one And a second reset means for resetting the output request signal held in the other when a condition for holding the output request signal is satisfied.

  Thus, according to the first aspect of the present invention, when the rotation direction of the rotating body is switched, the change of the first sensor signal after the switching is not masked, but the first sensor signal is not masked. When the change is a valid edge, the output request signal is held by the other of the forward pulse output request holding means and the reverse pulse output request holding means. Then, based on the output request signal held in one of the normal rotation pulse output request holding means and the reverse rotation pulse output request holding means, after the output of the normal rotation pulse or the reverse rotation pulse is finished, the first reset means When the output request signal held in one of them is reset, the forward rotation pulse or the reverse rotation is based on the output request signal held in the other of the normal rotation pulse output request holding means and the reverse rotation pulse output request holding means. Output a pulse. Therefore, when the rotating body switches the rotation direction, a reverse rotation pulse is output after the normal rotation pulse, or a normal rotation pulse is output after the reverse rotation pulse. For this reason, even when the rotating body performs a rotating motion that switches the rotating direction in a short cycle, such a rotating motion can be detected based on the detection signal output from the pulse output means.

  However, in the first aspect of the invention, when a specific condition is satisfied, the output request signal held in the other of the forward rotation pulse output request holding means and the reverse rotation pulse output request holding means is reset.

  For example, while the forward rotation pulse output request holding means holds the output request signal for outputting the forward rotation pulse, the output request signal for outputting the reverse rotation pulse is held in the reverse rotation pulse output request holding means. Furthermore, when the condition for holding the output request signal of the forward rotation pulse is satisfied, the rotating body switches the rotation direction from forward rotation → reverse rotation → forward rotation. When such switching of the rotation direction is performed while the output request signal for outputting the normal rotation pulse is held in the normal rotation pulse output request holding means, the normal rotation pulse output as the detection signal The rotating direction of the rotating body is in a consistent state. Furthermore, if the rotating body is reversed once, if a reverse rotation pulse is output after the forward rotation pulse is output, there will be a large time lag between the actual rotational motion of the rotating body and output thereafter. A time delay is caused also in the forward rotation pulse or the reverse rotation pulse.

  For this reason, in the invention of claim 1, the second reset means is provided, and the output request signal is held in one of the forward rotation pulse output request holding means and the reverse rotation pulse output request holding means. An output request signal is also held on the other side. Further, when the condition for holding the output request signal is satisfied with respect to the output request signal already held on one side, the output request signal held on the other side is reset. It is.

  When the output request signal held in the other of the normal rotation pulse output request holding means and the reverse rotation pulse output request holding means is reset by the second reset means, the normal rotation pulse output One of the request holding means and the reverse pulse output request holding means preferably holds the output request signal as it is without being affected by the establishment of the condition for holding the output request signal. In this case, only the rotation direction of the rotating body is switched twice, and the position of the gear teeth is not changed. Therefore, if the forward rotation pulse or the reverse rotation pulse is output again based on the establishment of the condition for holding the output request signal, the gear tooth position may be erroneously detected by the normal rotation pulse or the reverse rotation pulse in the detection signal. This is because it occurs.

  The timer means for measuring time as claimed in claim 3, wherein the timer means counts the elapsed time from the start of the output of the forward rotation pulse or the reverse rotation pulse from the pulse output means, and the elapsed time When the time reaches a predetermined time, it is preferable to instruct the pulse output means to end the output of the forward pulse or the reverse pulse. Thereby, the pulse width of the forward rotation pulse and the reverse rotation pulse can be easily set.

  According to a fourth aspect of the present invention, the timer means separately has a predetermined time for the forward rotation pulse and a predetermined time for the reverse rotation pulse as the predetermined time to be compared with the measured elapsed time, thereby It is preferable to make the Hals width different from the pulse width of the reverse pulse. As a result, it is possible to determine whether the pulse is a forward rotation pulse or a reverse rotation pulse from the pulse width of the pulse signal in the detection signal, and the rotation direction of the rotating body can be detected from the detection signal.

  According to a fifth aspect of the present invention, the timer means issues a reset instruction to the first reset means when a predetermined adjustment time has elapsed since the end of the output of the normal rotation pulse signal or the reverse rotation pulse signal by the pulse output means. In response to the reset instruction, the first reset means holds the normal rotation pulse or reverse pulse that has been output and is held in one of the normal rotation pulse output request holding means and the reverse rotation pulse output request holding means. It is preferable to reset the output request signal. Thereby, when a pulse signal continues in a detection signal, the space | interval between continuous pulse signals can be ensured by adjustment time. Therefore, even if the detection signal is a continuous pulse signal, it is easy to correctly recognize each pulse signal in a device that detects the rotation of the rotating body from the detection signal.

It is a block block diagram which shows the whole structure of the rotation detection apparatus which concerns on embodiment. It is explanatory drawing for demonstrating an effective edge and a non-effective edge, showing the change of the main sensor signal by the peak part and trough part of the gear teeth of a rotor, and a sub sensor signal. FIG. 3 is an explanatory diagram for explaining an effective edge and an ineffective edge together with FIG. 2. 2 is a block diagram showing a configuration of a logic circuit 20. FIG. 3 is a circuit diagram showing a detailed circuit configuration of a logic circuit 20. FIG. 4 is a waveform diagram for explaining the operation of the logic circuit 20. FIG. It is explanatory drawing for demonstrating the problem by a conventional circuit.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block configuration diagram illustrating the overall configuration of the rotation detection device according to the present embodiment.

  In FIG. 1, a main magnetic sensor 1 and a sub magnetic sensor 2 include magnetoelectric conversion elements such as a magnetoresistive element and a Hall element. The main magnetic sensor 1 and the sub magnetic sensor 2 have gear teeth formed on the outer periphery, and are arranged at a predetermined interval from each other while facing the outer peripheral surface of a rotor (not shown) made of a magnetic material. For this reason, the main magnetic sensor 1 and the sub magnetic sensor 2 output periodic signals having different phases (for example, ¼ period) when the rotor rotates.

  That is, when the rotor rotates, the crests and troughs of the gear teeth formed on the outer periphery of the rotor alternately pass in the vicinity of the main magnetic sensor 1 and the sub magnetic sensor 2. For this reason, the magnetic field which acts on each magnetoelectric conversion element of the main magnetic sensor 1 and the sub magnetic sensor 2 also changes periodically. This change in magnetic field is converted into an electrical signal by the magnetoelectric transducers of the main magnetic sensor 1 and the sub magnetic sensor 2. These electric signals are amplified by the amplifiers 3 and 4 and then input to the comparators 7 and 8. The comparators 7 and 8 binarize the input amplified electric signals by comparing them with the reference voltages generated by the resistors 5a and 5b and the resistors 6a and 6b, respectively.

  Therefore, with the above-described configuration, the main magnetic sensor 1 and the sub magnetic sensor 2 respectively have rectangular wave-shaped pulse signals (hereinafter referred to as sensor signals) that change periodically according to the passage of the crests and troughs of the gear teeth of the rotor. ) Can be obtained. These sensor signals are input to the signal processing circuit 10.

  The signal processing circuit 10 is a circuit that generates and outputs a detection signal for detecting the rotational position and the rotational direction of the rotor based on the main sensor signal and the sub sensor signal. As shown in FIG. 1, the signal processing circuit 10 is mainly composed of a filter 11, a clock signal generator 12, a timer 13, a logic circuit 20, a transistor Tr1, and a resistor R1.

  The filter 11 is for removing high frequency components in the main sensor signal and the sub sensor signal input to the signal processing circuit 10. Therefore, the main sensor signal and the sub sensor signal from which the high frequency component has been removed by the filter 11 are input to the logic circuit 20.

  Here, in the present embodiment, the concept of the effective edge and the ineffective edge is introduced with respect to the change of the main sensor signal, and in one rotation direction of the forward rotation direction and the reverse rotation direction of the rotor, The change in the main sensor signal due to the leading edge of the peak is defined as the signal change due to the effective edge in the one rotation direction, and the change in the main sensor signal due to the rear edge on the peak in the one rotation direction This is defined as a signal change due to an ineffective edge in the rotation direction. Further, in the other rotation direction of the forward rotation direction and the reverse rotation direction of the rotor, the change of the main sensor signal due to the rear end side edge of the peak portion in the other rotation direction is changed by the effective edge in the other rotation direction. And the change in the main sensor signal due to the leading edge of the peak in the other rotation direction is defined as the signal change due to the ineffective edge in the one rotation direction. That is, in this embodiment, regardless of the rotation direction of the rotor, a change in the main sensor signal due to the same edge of one of the peaks is a signal change due to the effective edge, and a change in the main sensor signal due to the other edge of the peak is not valid. It is defined as a signal change due to an edge.

  In the logic circuit 20, when a signal change occurs due to an effective edge in the main sensor signal, a forward rotation pulse is generated if the rotor rotates in the forward direction, and if the rotor rotates in the reverse direction. Generate a reverse pulse. The output signal (detection signal) of the logic circuit 20 is generated by combining these forward rotation pulse and reverse rotation pulse. The output signal of the logic circuit 20 is connected to the base of the transistor Tr1, amplified through the resistor R1, and output from the output terminal OUT to a control device (such as an ECU) (not shown) for detecting the rotation of the rotor. The Note that the configuration and operation of the logic circuit 20 will be described in detail later.

  In the signal processing circuit 10 of the present embodiment, the pulse widths of the normal rotation pulse and the reverse rotation pulse described above are different (for example, normal rotation pulse: 45 μs, reverse rotation pulse: 90 μs). In this way, by varying the pulse width of the pulse signal according to the rotation direction, the control device such as the ECU described above can also detect the rotation direction of the rotor based on the detection signal. Instead of changing the pulse width, for example, as described in Patent Document 1, when the rotor rotates in the forward direction and when the rotor rotates in the reverse direction, the detection signal is high and low. You may comprise so that it may change between two values or between two values of middle and low.

  Next, the change due to the effective edge and the change due to the ineffective edge in the main sensor signal will be described in detail with reference to FIGS.

  In the example shown in FIG. 2, when the rotor rotates in the forward rotation direction, the change in the main sensor signal due to the leading edge of the gear tooth peak in the forward rotation direction is defined as the signal change due to the effective edge, The change of the main sensor signal due to the trailing edge is defined as the signal change due to the invalid edge. In this case, as shown in FIG. 3, the falling change of the main sensor signal becomes a signal change due to the effective edge, and the rising change of the main sensor signal becomes a signal change due to the ineffective edge. On the other hand, when the rotor is rotating in the reverse rotation direction, the change in the main sensor signal due to the rear end edge of the gear tooth peak in the reverse rotation direction is the signal change due to the effective edge, and The signal change is a signal change caused by an invalid edge. In this case, the rising change of the main sensor signal becomes a signal change due to the effective edge, and the falling change of the main sensor signal becomes a signal change due to the ineffective edge.

  Thus, when the rotor is rotating forward, the change in the main sensor signal due to the leading edge of the peak is regarded as a signal change due to the effective edge. Since the change in the sensor signal is the signal change due to the effective edge, in this embodiment, the change in the main sensor signal due to the same edge of one of the peaks is the signal change due to the effective edge regardless of the rotation direction of the rotor.

  Whether the rotor is rotating forward or reverse can be determined by the phase relationship between the main sensor signal and the sub sensor signal. In the example shown in FIG. 2, when the rotor is rotating forward, the phase of the main sensor signal is ahead of the phase of the sub sensor signal. Accordingly, when the falling change of the main sensor signal occurs, the sub sensor signal becomes a high level, and when the rising change of the main sensor signal occurs, the sub sensor signal becomes a low level. Conversely, when the rotor is rotating in reverse, the phase of the sub sensor signal is ahead of that of the main sensor signal. Therefore, when the rising change of the main sensor signal occurs, the sub sensor signal becomes high level and the main sensor signal falls. When the change occurs, the sub sensor signal becomes a low level. In this way, it is possible to determine whether the rotor is rotating forward or reversely from the level of the sub sensor signal when a rising change or falling change occurs in the main sensor signal.

  FIG. 3 is a diagram summarizing these relationships. However, the present invention is not limited to the examples shown in FIGS. 2 and 3, and the relationship between the effective edge and the ineffective edge may be reversed. That is, the change in the main sensor signal due to the trailing edge of the peak in the forward rotation direction of the rotor is the signal change due to the effective edge, and the change in the main sensor signal due to the leading edge of the peak in the forward rotation direction is due to the invalid edge It may be a signal change.

  Next, the configuration and operation of the logic circuit 20 will be described in detail with reference to the block diagram of FIG. 4, the circuit diagram of FIG. 5, and the waveform diagram of FIG.

  As shown in FIG. 4, the main sensor signal is input to the edge detection circuit 21. The edge detection circuit 21 detects the rising change and the falling change of the main sensor signal due to the leading edge and the trailing edge of the gear tooth crest, and outputs an edge detection signal. This edge detection signal is input to the valid edge determination circuit 22 together with the sub sensor signal.

  Specifically, as shown in FIG. 5, the edge detection circuit 21 outputs an exclusive OR that outputs an exclusive OR of the outputs of two D flip-flops DFF1, DFF2, and two DFF1, DFF2 connected in series. A circuit EXOR1 and an inverter INV1 are included. The main sensor signal is input to the data input terminal of the preceding DFF1, and the output signal from the data output terminal of the preceding DFF1 is input to the data input terminal of the subsequent DFF2. The clock signal from the clock signal generator 12 is input to the clock terminals of the two DFF1 and DFF2. However, the phase of the clock signal of DFF1 and the phase of the clock signal of DFF2 are inverted by the inverter INV1. The frequency of the clock signal is, for example, several MHz, and is set sufficiently higher than the frequency of the main sensor signal and the sub sensor signal (about 10 kHz at the maximum).

  When a rising change or a falling change occurs in the main sensor signal, first, the output of the preceding DFF1 changes, and the output of the subsequent DFF2 also changes after a delay of one clock. Therefore, when the main sensor signal rises or falls, EXOR1 outputs a high-level edge detection signal because the output of the preceding DFF1 and the output of the succeeding DFF2 differ by one clock.

  When the edge detection signal is input from the edge detection circuit 21, the valid edge determination circuit 22 determines whether the change of the main sensor signal is due to the valid edge or the non-valid edge based on the level of the sub sensor signal input at the same time. If it is determined that the signal changes due to the effective edge, an effective edge signal is output. Specifically, as shown in FIG. 5, the valid edge determination circuit 22 includes a NAND circuit NAND1, and only when the high level edge detection signal is input and the level of the sub sensor signal is high. The low level effective edge signal is output.

  In FIG. 4, the forward rotation determination circuit 23 and the reverse rotation determination circuit 24 receive the main sensor signal and the sub sensor signal, respectively, and determine the rotation direction of the rotor based on the phase relationship between the main sensor signal and the sub sensor signal as described above. To do. The forward rotation determination circuit 23 outputs a forward rotation signal when it is determined that the rotor is rotating in the forward rotation direction, and the reverse rotation determination circuit 24 is when it is determined that the rotor is rotating in the reverse rotation direction. Outputs reverse rotation signal.

  Specifically, as shown in FIG. 5, the forward rotation determination circuit 23 includes inverters INV2 and INV3 and a D flip-flop DFF3, and the reverse rotation determination circuit 24 includes an inverter INV4 and a D flip-flop DFF4. The main sensor signal is input to the clock terminal of DFF3 via INV2 and input to the clock terminal of DFF4 as it is. In both DFF3 and DFF4, the sub sensor signal is input to the data input terminal, and INV3 and INV4 are connected to the output terminal.

  As described above, since the main sensor signal is input to the clock terminal of DFF3 via INV2, DFF3 determines the level of the sub sensor signal applied to the data input terminal when the main sensor signal falls. Capture and output the signal of the captured level from the output terminal. As shown in FIG. 3, when the rotor is rotating forward, the sub sensor signal is at the high level at the timing when the main sensor signal falls, and when the rotor is rotating in reverse, the main sensor signal is rising. The sub sensor signal is at a low level at the timing when it falls. Therefore, when the rotor is rotating forward, the high level signal output from DFF3 is converted to a low level forward signal by INV3, and when the rotor is rotating reversely, the low level signal output from DFF3 is A high-level non-forward signal is set by INV3.

  On the other hand, since the main sensor signal is directly input to the clock terminal, the DFF 4 captures the level of the sub sensor signal given to the data input terminal when the main sensor signal rises, and outputs the signal of the captured level. Output from the terminal. Therefore, contrary to the forward rotation determination circuit 23 described above, when the rotor is rotating in reverse, the high level signal output from the DFF 4 is changed to the low level reverse rotation signal by INV 4 and the rotor is rotating forward. , A high level non-inverted signal.

  In FIG. 4, the normal rotation effective edge determination circuit 25 receives the normal rotation signal from the normal rotation determination circuit 23 and when the effective edge signal is input from the effective edge determination circuit 22, the rotor moves in the normal rotation direction. Since the main sensor signal can be regarded as having undergone a signal change due to an effective edge in the rotating state, an output request signal for a forward rotation pulse is generated. The output request signal of the normal rotation pulse is input to the normal output request signal holding circuit 27. Specifically, as shown in FIG. 5, the normal rotation valid edge determination circuit 25 includes a negative OR circuit NOR1, receives a low level valid edge signal from the valid edge determination circuit 22, and determines normal rotation. When a low-level forward signal is input from the circuit 23, a high-level forward pulse output request signal is generated. Accordingly, at this time, the output level of the normal rotation valid edge determination circuit 25 changes from low to high.

  The normal rotation output request signal holding circuit 27 holds the normal rotation pulse output request signal generated by the normal rotation valid edge determination circuit 25 except when the normal rotation pulse output request signal is already held. That is, the normal output request signal holding circuit 27 comprises a D flip-flop DFF5 as shown in FIG. 5, the output from the normal rotation valid edge determination circuit 25 is input to the clock terminal, and the data input terminal is a pull-up power supply. It is connected to the. For this reason, when the level of the output signal of the normal rotation valid edge determination circuit 25 changes from low to high, the DFF 5 outputs a high level signal, that is, a normal pulse output request signal from the data output terminal. This forward pulse output request signal is held in the DFF 5 until a low-level reset signal is input to its own reset terminal.

  Note that the output of the normal rotation valid edge determination circuit 25 and the output of the normal rotation output request signal holding circuit 27 are input to the negative logical product circuit NAND2, and the output of the NAND2 is supplied to the normal rotation determination circuit via the logical product circuit AND1. 23 is connected to the reset terminal of DFF3. As a result, at the timing when both the normal rotation valid edge determination circuit 25 and the normal rotation output request signal holding circuit 27 output the high-level normal rotation pulse output request signal, the output of the NAND2 changes to the low level and the DFF3 is reset. To do. The other input signal of AND1 is a power-on reset (POR) signal.

  In FIG. 4, in the reverse rotation effective edge determination circuit 26, when the reverse rotation signal is input from the reverse rotation determination circuit 24 and the effective edge signal is input from the effective edge determination circuit 22, the rotor rotates in the reverse rotation direction. In this state, since it can be considered that the main sensor signal has undergone a signal change due to the effective edge, an output request signal for the reverse pulse is generated. The reverse pulse output request signal is input to the reverse output request signal holding circuit 28. Specifically, as shown in FIG. 5, the reverse rotation valid edge determination circuit 26 includes a negative OR circuit NOR2, receives a low level valid edge signal from the valid edge determination circuit 22, and the reverse rotation determination circuit 24. When a low level reverse signal is input from, a high level reverse pulse output request signal is generated.

  The reverse rotation output request signal holding circuit 28 holds the reverse pulse output request signal generated by the reverse rotation valid edge determination circuit 26 except when the reverse rotation pulse output request signal is already held. That is, the reverse rotation output request signal holding circuit 28 comprises a D flip-flop DFF6 as shown in FIG. 5, the output from the reverse rotation valid edge determination circuit 26 is input to the clock terminal, and the data input terminal is connected to the pull-up power supply. Has been. For this reason, when the level of the output signal of the reverse rotation valid edge determination circuit 26 changes from low to high, the DFF 6 outputs a high level signal, that is, a reverse pulse output request signal from the data output terminal. The reverse pulse output request signal is held in the DFF 6 until a low level reset signal is input to its own reset terminal.

  As in the case of the forward rotation determination circuit 23 described above, the output of the reverse rotation valid edge determination circuit 26 and the output of the reverse rotation output request signal holding circuit 28 are input to the NAND circuit NAND3, and the output of the NAND3 is Are connected to the reset terminal of the DFF 4 of the reverse rotation determination circuit 24 via the AND circuit AND2. As a result, the DFF 4 is reset at the timing when both the reverse rotation valid edge determination circuit 26 and the reverse rotation output request signal holding circuit 28 output a high level reverse pulse output request signal.

  As shown in FIG. 4, when the normal rotation output request signal holding circuit 27 holds the normal rotation pulse output request signal, it outputs the held output request signal to the normal rotation output permission circuit 29 and the reverse rotation output permission circuit 30. . As will be described later, when the reverse rotation output request signal holding circuit 28 holds a reverse pulse output request signal, the normal rotation output permission circuit 29 also receives the reverse rotation pulse output request signal. When the output request signal of the normal rotation pulse is input when the output request signal of the reverse rotation pulse is not input, the normal rotation output permission circuit 29 outputs the input request signal of the normal rotation pulse to the subsequent circuit. Is allowed to output. On the other hand, when the output request signal for the reverse rotation pulse is input and the output request signal for the normal rotation pulse is input later than the input, the output request signal for the reverse rotation pulse in the reverse output request signal holding circuit 28. Is held, and output of the forward rotation pulse output request signal is awaited until input of the reverse rotation pulse output request signal is completed.

  Specifically, as shown in FIG. 5, the normal output permission circuit 29 includes an inverter INV5 and a negative OR circuit NOR3, and an output from the normal output request signal holding circuit 27 is input to NOR3 via INV5. . In addition, a signal from the reverse rotation output request signal holding circuit 28 and an output signal from a normal rotation pulse timing adjustment circuit 37 described later are input to NOR3. The normal rotation pulse timing adjustment circuit 37 outputs a low level signal before the start of the output of the normal rotation pulse, and outputs a high level signal when the output of the normal rotation pulse is started. Accordingly, the normal output request signal holding circuit 27 holds a high level normal pulse output request signal, the reverse output request signal hold circuit 28 does not hold a high level reverse pulse output request signal, and When the normal pulse timing adjustment circuit 37 is outputting a low level signal, the NOR 3 permits the output of a normal pulse output request signal that is a high level signal. On the other hand, when the reverse rotation output request signal holding circuit 28 holds the high level reverse pulse output request signal, the NOR 3 waits for the output of the normal rotation pulse output request signal until the reverse rotation pulse output request signal is reset. To do. Note that when the normal rotation pulse is actually output in response to the output permission of the normal rotation pulse output request signal, the normal rotation pulse timing adjustment circuit 37 outputs a high level signal. Thereafter, the circuit 29 prohibits the output of the normal rotation pulse output request signal until the output of the normal rotation pulse is completed.

  Similarly, when the reverse rotation output request signal holding circuit 28 holds the output request signal of the reverse rotation pulse, as shown in FIG. 4, the held output request signal is sent to the normal rotation output permission circuit 29 and the reverse rotation output permission circuit 30. Output. When the output request signal for the reverse rotation pulse is input when the output request signal for the normal rotation pulse is not input, the reverse rotation output permission circuit 30 outputs the input request signal for the reverse rotation pulse to the subsequent circuit. Allow to do. On the other hand, the reverse rotation output permission circuit 30 receives a normal rotation output request signal holding circuit when a reverse rotation pulse output request signal is input behind the input in a state where the normal rotation pulse output request signal is input. The holding of the forward rotation pulse output request signal is reset and the output of the reverse rotation pulse output request signal is waited until the input of the forward rotation pulse output request signal is completed.

  Specifically, as shown in FIG. 5, the reverse rotation output permission circuit 30 includes an inverter INV6 and a negative OR circuit NOR4, and an output from the reverse rotation output request signal holding circuit 28 is input to the NOR 4 via the INV6. In addition, a signal from the forward rotation output request signal holding circuit 27 and an output signal from the reverse rotation pulse timing adjustment circuit 38 to be described later are input to NOR4. The reverse pulse timing adjustment circuit 38 outputs a low level signal before starting the output of the reverse pulse, and outputs a high level signal when the output of the reverse pulse is started. Therefore, the normal output request signal holding circuit 27 does not hold the high level normal pulse output request signal, the reverse output request signal hold circuit 28 holds the high level reverse pulse output request signal, and When the reverse pulse timing adjustment circuit 38 outputs a low level signal, the NOR 4 permits the output of a reverse pulse output request signal that is a high level signal. On the other hand, when the normal rotation output request signal holding circuit 27 holds the high level normal rotation pulse output request signal, the reverse rotation output permission circuit 30 outputs the reverse rotation pulse output until the normal rotation pulse output request signal is reset. Wait for request signal output. Note that when the reverse pulse is actually output in response to the output permission of the reverse pulse output request signal, the reverse pulse timing adjustment circuit 38 outputs a high level signal. Thereafter, the output of the reverse pulse output request signal is prohibited until the reverse pulse output ends.

  In FIG. 4, when the normal rotation output permission circuit 29 permits the output of the normal rotation pulse output request signal, the normal rotation pulse output request signal is input to the normal rotation pulse output circuit 31. As shown in FIG. 5, the normal rotation pulse output circuit 31 includes a D flip-flop DFF 9, an output from the normal rotation output permission circuit 29 is input to a clock terminal, and a data input terminal is connected to a pull-up power supply. . For this reason, when the normal rotation pulse output request signal is output from the normal rotation output permission circuit 29 and the output level changes from low to high, the DFF 9 outputs a high level signal from the data output terminal.

  In FIG. 4, when the reverse rotation output permission circuit 30 permits the output of the reverse rotation pulse output request signal, the reverse rotation pulse output request signal is input to the reverse rotation pulse output circuit 32. As shown in FIG. 5, the reverse pulse output circuit 32 includes a D flip-flop DFF12. An output from the reverse output permission circuit 30 is input to a clock terminal, and a data input terminal is connected to a pull-up power supply. For this reason, when the reverse rotation pulse output request signal is output from the reverse rotation output permission circuit 30 and the output level changes from low to high, the DFF 12 outputs a high level signal from the data output terminal.

  The output of the normal rotation pulse output circuit 31 and the output of the reverse rotation pulse output circuit 32 are input to the output synthesis circuit 33, and the output synthesis circuit 33 combines the normal rotation pulse and the reverse rotation pulse. Specifically, as shown in FIG. 5, the output synthesis circuit 33 is composed of a negative OR circuit NOR7. When a high level signal is input from the normal rotation pulse output circuit 31, a low level normal rotation pulse is output. When a high level signal is input from the reverse pulse output circuit 32, a low level reverse pulse is output.

  Here, as described above, in this embodiment, the pulse width of the forward rotation pulse is different from the pulse width of the reverse rotation pulse. Such a difference between the pulse widths of the forward rotation pulse and the reverse rotation pulse is realized by using a timer function of the timer 13. Hereinafter, this point will be described.

  As shown in FIG. 4, the forward rotation output request signal holding circuit 27 and the reverse rotation output request signal holding circuit 28 are also connected to the timer start / reset circuit 34, respectively, for the forward rotation pulse output request signal and reverse rotation pulse output request signal give. The timer start / reset circuit 34 outputs a start signal to the timer 13 when either the forward pulse output request signal or the reverse pulse output request signal is input. As a result, the timer starts a time counting operation.

  Specifically, as shown in FIG. 5, the outputs of the normal rotation output request signal holding circuit 27 and the reverse rotation output request signal holding circuit 28 are input to the OR circuit OR3 of the timer start / reset circuit 34, When the output request signal is held in one of the rotation output request signal holding circuit 27 and the reverse rotation output request signal holding circuit 28, the OR 3 outputs a high level signal. As a result, as will be described in detail later, the output of the NAND circuit NAND8 that outputs the start signal or reset signal from the timer start / reset circuit 34 changes from high level to low level. This falling change from the high level to the low level forms a start signal for the timer 13, and the timer 13 outputs an output request signal to either the forward output request signal holding circuit 27 or the reverse output request signal holding circuit 28. Start counting elapsed time from the time it was held.

  The timer 13 includes a first predetermined time corresponding to the pulse width of the forward rotation pulse, a second predetermined time corresponding to the pulse width of the reverse rotation pulse, and the end of output of the forward rotation pulse and the reverse rotation pulse (that is, the first rotation time). After the predetermined time and the second predetermined time have elapsed), a third predetermined time corresponding to an adjustment time for ensuring an interval between successive pulse signals is preset. When the count time reaches a first predetermined time corresponding to the pulse width of the normal rotation pulse, the timer 13 causes the normal rotation pulse output circuit 31 to end the output of the normal rotation pulse. A reset signal TFPW is output.

  Specifically, as shown in FIG. 5, when the count time reaches the first predetermined time, the timer 13 outputs a low-level first normal rotation reset signal TFPW. The first normal rotation reset signal TFPW is connected to the reset terminal of the DFF 9 via the AND circuit AND7. A power-on reset (POR) signal is input to the other input of the AND7 via the inverter INV11. When the signal processing circuit 10 is powered on, the POR signal becomes low level to reset each D flip-flop (the actual POR signal before INV11 becomes high level), but otherwise remains high level. To do. Accordingly, when the timer 13 outputs the first normal reset signal TFPW having a low level, the low-level reset signal is input to the reset terminal of the DFF 9 and the DFF 9 is reset. As a result, the level of the output signal of the DFF 9 changes to a low level, and the output of the normal rotation pulse is terminated. In this way, the normal rotation pulse output circuit 31 outputs a normal rotation pulse signal having a pulse width corresponding to a predetermined first predetermined time.

  The timer 13 continues the counting operation even after outputting the first normal rotation reset signal TFPW to the normal rotation pulse output circuit 31. Then, when the count time from the output of the first normal rotation reset signal becomes the third predetermined time, the second normal rotation reset signal TFPWTR is output to the normal rotation output request signal holding circuit 27 and the like. The holding of the output request signal of the normal rotation pulse by the rotation output request signal holding circuit 27 is reset.

  That is, as shown in FIG. 5, the second normal reset signal TFPWTR is connected to the reset terminal of the DFF 5 of the normal output request signal holding circuit 27 via the OR circuit OR1 and the AND circuit AND3. For this reason, when the timer 13 outputs the low-level second normal rotation reset signal TFPWTR, the DFF 5 is reset, and the holding of the normal pulse output request signal by the DFF 5 is released. Accordingly, when the reverse rotation output request signal holding circuit 28 holds the reverse rotation pulse output request signal, the reverse rotation output permission circuit 30 permits the output of the reverse rotation pulse output request signal to the subsequent circuit. .

  Note that an output from the AND circuit AND6 of the second rotation direction even number switching determination circuit 36, which will be described later, is also input to OR1. The AND 6 outputs a high level signal when the reverse rotation output permission circuit 30 permits the output of the reverse rotation pulse output request signal, and then the normal rotation pulse output request signal is held in the DFF 5. By inputting the output of AND6 to OR1, the DFF5 is reset by the second normal reset signal TFPWTR when the forward rotation pulse output request signal is held in the DFF5 and waiting for the end of the reverse rotation pulse output. Is prevented.

  As shown in FIG. 4, the second normal rotation reset signal TFPWTR is also supplied to the normal rotation pulse timing adjustment circuit 37. The normal rotation pulse timing adjustment circuit 37 is supplied with an output request signal for a normal rotation pulse from the normal rotation output permission circuit 29 together with the normal rotation pulse output circuit 31. When the normal rotation pulse timing adjustment circuit 37 receives the above-described second normal rotation reset signal TFPWTR after the output request signal of the normal rotation pulse is input, the timer start / reset circuit 34 receives the timer 13 A timer reset signal for instructing to stop the counting operation is output.

  Specifically, as shown in FIG. 5, the normal rotation pulse timing adjustment circuit 37 includes two D flip-flops DFF10 and DFF11 connected in series, and a normal pulse output request signal is supplied to the clock terminal of the preceding DFF10. And a pull-up power supply is connected to the data input terminal. For this reason, when the normal rotation pulse output request signal is output from the normal rotation output permission circuit 29, the DFF 10 in the previous stage outputs a high level signal from the data output terminal. The data output terminal of the preceding DFF 10 is connected to the data input terminal of the subsequent DFF 11, and the clock signal CLK is input to the clock terminal of the DFF 11. Therefore, when the output signal of the preceding DFF 10 changes to high level, the output signal of the subsequent DFF 11 also changes from low level to high level in synchronization with the clock signal CLK. As described above, when the high-level signal is input to NOR3 of the normal rotation output permission circuit 29, the normal rotation output permission circuit 29 prohibits the output of the normal rotation pulse output request signal.

  When the second normal rotation reset signal TFPWTR is input to the normal pulse timing adjustment circuit 37, the second normal rotation reset signal TFPWTR is supplied to the reset terminal of the DFF 10 via the AND circuit AND8. For this reason, the DFF 10 is reset, and the signal level output from the data output terminal changes from the high level to the low level. Then, the DFF 11 in the subsequent stage also outputs a low level signal in synchronization with the clock signal CLK. By inputting this low level signal to the timer start / reset circuit 34, the level of the output signal of the timer start / reset circuit 34 changes from the low level to the high level to form a reset signal for the timer 13. . Hereinafter, it will be described in detail with reference to FIG.

  The output of the normal rotation pulse timing adjustment circuit 37 is input to a negative OR circuit NOR5 of the timer start / reset circuit 34. The other input of NOR5 is an output signal of the reverse rotation output request signal holding circuit 28 via the inverter INV7. The output signal of the normal output request signal holding circuit 27 is input to the inverter INV8 and is connected to the data input terminal of the D flip-flop DFF15. Since the clock signal CLK is input to the clock terminal of the DFF 15, the DFF 15 outputs the signal level input to the data input terminal from the data output terminal in synchronization with the clock signal CLK. The data output terminals of INV8 and DFF15 are connected to the NAND circuit NAND6. Therefore, when the DFF 5 is reset and the level of the output signal is switched from the high level to the low level, the NAND 6 is the low level signal until the output of the DFF 15 is switched to the low level in synchronization with the clock signal CLK. Is output.

  When the output of the DFF 5 is switched from the high level to the low level by the second normal rotation reset signal TFPWTR, that is, when the output of the DFF 10 in the previous stage of the normal rotation pulse timing adjustment circuit 37 is switched from the high level to the low level, The subsequent stage DFF 11 still outputs a high level signal. For this reason, the level of the output signal of NOR5 becomes a low level. The outputs of NOR5 and NAND6 are input to an OR circuit OR4. For this reason, OR4 is the period from when the output of DFF5 is switched from the high level to the low level by the second normal reset signal TFPWTR until the output signals of DFF11 and DFF15 are set to the low level in synchronization with the clock signal CLK. A low level signal is output only during the time. Due to the low level signal output from the OR4, the output signal of the NAND 8 changes from the low level to the high level. The rising signal from the low level to the high level becomes the reset signal of the timer 13 and resets the count operation of the timer 13.

  In the present embodiment, the DFF 5 of the normal rotation output request signal holding circuit 27 may be reset at a timing other than after the end of the output of the normal rotation pulse by the second rotation direction even number switching determination circuit 36 described later. Therefore, by using the signal from the normal rotation pulse timing adjustment circuit 37, the output of the normal rotation pulse is completed, and further, the reset signal of the timer 13 is output when the third predetermined time has elapsed from that time. I am trying to do it.

  Thus, when the timer 13 is reset after the output of the normal rotation pulse signal from the normal rotation pulse output circuit 31 is completed, the timer 13 is connected to the normal rotation output request signal holding circuit 27 or the reverse rotation output request signal holding circuit. In response to the output request signal from 28, the count operation can be restarted.

  Similarly, when the count time reaches a second predetermined time corresponding to the pulse width of the reverse pulse, the timer 13 performs a first reverse reset for terminating the reverse pulse output to the reverse pulse output circuit 32. The signal TRPW is output. As a result, the reverse pulse output circuit 32 outputs a reverse pulse signal having a pulse width corresponding to a predetermined second predetermined time.

  Specifically, as shown in FIG. 5, the timer 13 outputs a low-level first reverse reset signal TRPW when the count time reaches the second predetermined time. The first reverse reset signal TRPW is connected to the reset terminal of the DFF 12 via the AND circuit AND9. The POR signal is input to the other input of AND9. Therefore, when the timer 13 outputs the low-level first reverse reset signal TRPW, the low-level reset signal is input to the reset terminal of the DFF 12, and the DFF 12 is reset. As a result, the level of the output signal of the DFF 12 changes to a low level, and the output of the reverse pulse is terminated.

  The timer 13 continues the counting operation even after outputting the first reverse reset signal TRPW to the reverse pulse output circuit 32. When the count time from the output of the first reverse rotation reset signal becomes the third predetermined time, the second reverse rotation reset signal TRPWTR is output to the reverse rotation output request signal holding circuit 28 to hold the reverse rotation output request signal. The holding of the reverse pulse output request signal by the circuit 28 is reset.

  That is, as shown in FIG. 5, the second reverse rotation reset signal TRPWTR is connected to the reset terminal of the DFF 6 of the reverse rotation output request signal holding circuit 28 via the logical sum circuit OR2 and the logical product circuit AND4. For this reason, when the timer 13 outputs the low-level second reverse reset signal TRPWTR, the DFF 6 is reset and the holding of the reverse pulse output request signal by the DFF 6 is released. Thus, when the normal rotation output request signal holding circuit 27 holds the normal rotation pulse output request signal, the normal rotation output permission circuit 29 permits the output of the normal rotation pulse output request signal to the subsequent circuit. Become so.

  Note that an output from the logical product circuit AND5 of the first rotation direction even number switching determination circuit 35, which will be described later, is also input to the OR2. The AND 5 outputs a high level signal when the normal rotation output permission circuit 29 permits the output of the normal rotation pulse output request signal and then the reverse rotation pulse output request signal is held in the DFF 6. By inputting the output of AND5 to OR2, the DFF6 holds the reverse pulse output request signal, and the DFF6 is reset by the second reverse reset signal TRPWTR while waiting for the end of the forward pulse output. Is prevented.

  As shown in FIG. 4, the second reverse reset signal TRPWTR is also supplied to the reverse pulse timing adjustment circuit 38. The reverse pulse timing adjustment circuit 38 is supplied with a reverse pulse output request signal from the reverse rotation output permission circuit 30 together with the reverse pulse output circuit 32. When the reverse rotation pulse timing adjustment circuit 38 receives the second reverse rotation reset signal TRPWTR described above after the reverse rotation pulse output request signal is input, the timer start / reset circuit 34 performs the count operation of the timer 13. A timer reset signal is output to stop the operation.

  Specifically, as shown in FIG. 5, the reverse pulse timing adjustment circuit 38 includes two D flip-flops DFF13 and DFF14 connected in series, and the reverse pulse output request signal is input to the clock terminal of the preceding DFF 13. A pull-up power supply is connected to the data input terminal. For this reason, when the forward rotation pulse output request signal is output from the reverse rotation output permission circuit 29, the preceding stage DFF 13 outputs a high level signal from the data output terminal. The data output terminal of the preceding DFF 13 is connected to the data input terminal of the subsequent DFF 14, and the clock signal CLK is input to the clock terminal of the DFF 14. Accordingly, when the output signal of the preceding DFF 13 changes to high level, the output signal of the subsequent DFF 14 also changes from low level to high level in synchronization with the clock signal CLK. As described above, when this high level signal is input to NOR4 of the reverse rotation output permission circuit 30, the reverse rotation output permission circuit 30 prohibits the output of the reverse rotation pulse output request signal.

  When the second reverse reset signal TRPWTR is input to the reverse pulse timing adjustment circuit 38, the second reverse reset signal TRPWTR is given to the reset terminal of the DFF 13 via the AND circuit AND10. For this reason, the DFF 13 is reset, and the signal level output from the data output terminal changes from the high level to the low level. Then, the DFF 14 at the subsequent stage also outputs a low level signal in synchronization with the clock signal CLK. By inputting this low level signal to the timer start / reset circuit 34, the level of the output signal of the timer start / reset circuit 34 changes from the low level to the high level to form a reset signal for the timer 13. .

  That is, as shown in FIG. 5, the output of the reverse pulse timing adjustment circuit 38 is input to the negative OR circuit NOR6 of the timer start / reset circuit 34. The other input of NOR6 is the output signal of the normal output request signal holding circuit 27 via the inverter INV9. The output signal of the reverse rotation output request signal holding circuit 28 is input to the inverter INV10 and connected to the data input terminal of the D flip-flop DFF16. Since the clock signal CLK is input to the clock terminal of the DFF 16, the DFF 16 outputs the signal level input to the data input terminal from the data output terminal in synchronization with the clock signal CLK. The data output terminals of INV10 and DFF16 are connected to the NAND circuit NAND7. Therefore, when the DFF 6 is reset and the level of the output signal is switched from the high level to the low level, the NAND 7 is the signal of the low level until the output of the DFF 16 is switched to the low level in synchronization with the clock signal CLK. Is output.

  When the output of the DFF 6 is switched from the high level to the low level by the second reverse rotation reset signal TRPWTR, that is, when the output of the DFF 12 in the previous stage of the reverse pulse timing adjustment circuit 38 is switched from the high level to the low level. The DFF 14 is still outputting a high level signal. For this reason, the level of the output signal of the NOR 6 becomes a low level. The outputs of NOR6 and NAND7 are input to an OR circuit OR5. Therefore, OR5 is the time from when the output of DFF6 is switched from the high level to the low level by the second reverse reset signal TRPWTR until the output signals of DFF14 and DFF16 become the low level in synchronization with the clock signal CLK. A low level signal is output only during Due to the low level signal output from the OR5, the output signal of the NAND 8 changes from the low level to the high level. The rising signal from the low level to the high level becomes the reset signal of the timer 13 and resets the count operation of the timer 13.

  In the present embodiment, the DFF 6 of the reverse rotation output request signal holding circuit 28 may be reset at a timing other than after the reverse rotation pulse output ends by the first rotation direction even number switching determination circuit 35 described later. Therefore, by using the signal from the reverse pulse timing adjustment circuit 38, the output of the reverse pulse is completed, and the reset signal of the timer 13 is output when the third predetermined time has elapsed from that point. I have to.

  In this way, after the output of the reverse pulse signal from the reverse pulse output circuit 32 is completed, the timer 13 is reset, so that the timer 13 is the normal output request signal holding circuit 27 or the reverse output request signal holding circuit 28. The count operation can be restarted in response to the output request signal from.

  As described above, in the present embodiment, for example, when the rotation direction of the rotor is switched from the normal rotation direction to the reverse rotation direction while outputting the normal rotation pulse, the change in the main sensor signal after the switching is masked. Instead, when the change in the main sensor signal is a valid edge, the output request signal of the reverse pulse generated by the valid edge is held by the reverse output request signal holding circuit 28. Then, when the output request signal of the normal rotation pulse held by the normal rotation output request signal holding circuit 27 is reset based on the count operation of the timer 13, the reverse rotation output permission circuit 30 changes the reverse rotation output request signal holding circuit. The output request signal held in 28 is permitted to be output to the reverse pulse output circuit 32.

  Therefore, when the rotor switches the rotation direction from the normal rotation direction to the reverse rotation direction, the reverse rotation pulse is output after the normal rotation pulse. Similarly, when the rotor switches the rotation direction from the reverse rotation direction to the normal rotation direction, a normal rotation pulse is output after the reverse rotation pulse. For this reason, even when the rotor is performing a rotational motion that switches the rotational direction in a short cycle, the output synthesis circuit 33 can output an output signal (detection signal) indicating such a rotational motion state. .

  However, in the present embodiment, when the conditions described below are satisfied, the first and second rotation direction even number of times switching determination circuits 35 and 36 detect the normal rotation opposite to the forward rotation pulse or reverse rotation pulse being output. Reset the output request signal of the reverse pulse or reverse pulse.

  For example, in FIG. 4, a normal output request signal holding circuit 27 holds an output request signal for outputting a normal rotation pulse, and the reverse rotation output request signal holding circuit 28 is in the middle of outputting a normal rotation pulse. When the output request signal for the reverse rotation pulse is held and the output request signal for the normal rotation pulse is output from the normal rotation valid edge determination circuit 25, the rotor has switched the rotation direction from normal rotation → reverse rotation → normal rotation. become. When the switching of the rotation direction is performed even times (twice) while the normal rotation pulse output request signal is held in the normal rotation output request signal holding circuit 27, it is output as a detection signal. The forward rotation pulse and the rotational direction of the rotor are in a state of matching. In addition, if the reverse rotation pulse is output after the forward rotation pulse is output just because the rotor has been reversely rotated, a large time lag will occur between the actual rotational movement of the rotor and should be output thereafter. A time delay is also caused in the forward rotation pulse or the reverse rotation pulse.

  Therefore, in the present embodiment, the first and second rotation direction even number switching determination circuits 35 and 36 are provided. The first rotation direction even number switching determination circuit 35 holds the reverse rotation pulse output request signal in the reverse rotation output request signal holding circuit 28 after the normal rotation output permission circuit 29 outputs the normal rotation pulse output request signal. Furthermore, a reset for resetting the output request signal held by the reverse rotation output request signal holding circuit 28 based on the output of the normal rotation pulse output request signal from the normal rotation valid edge determination circuit 25 again. Output a signal. That is, the first rotation direction even number switching determination circuit 35 determines that the rotor has switched the rotation direction twice from forward rotation → reverse rotation → forward rotation, and sends a reset signal to the reverse rotation output request signal holding circuit 28. Output.

  Specifically, as shown in FIG. 5, the first rotation direction even number switching determination circuit 35 includes a D flip-flop DFF7, a logical product circuit AND5, and a negative logical product circuit NAND4. A normal pulse output request signal is input to the clock terminal of DFF7, a pull-up power supply is connected to the data input terminal, and a reset signal similar to that of DFF5 is input to the reset terminal. Therefore, the DFF 7 takes in the pull-up power source input to the data input terminal when the normal output pulse output request signal is output from the normal output permission circuit 29, and outputs the acquired signal level (high level) as data. Output from the terminal. The output from the DFF 7 and the signal from the reverse rotation output request signal holding circuit 28 are input to the AND 5. For this reason, while the normal rotation output permission circuit 29 outputs the normal rotation pulse output request signal and the normal rotation pulse output circuit 31 outputs the normal rotation pulse, the reverse rotation output request signal holding circuit 28 requests the reverse rotation pulse output. When the signal is held, the output of AND5 becomes high level. The output of the AND 5 and the output of the normal rotation valid edge determination circuit 25 are input to the NAND 4. Therefore, when the output of AND5 is at a high level, and further when the normal rotation valid edge determination circuit 25 outputs a normal pulse output request signal, the signal output of NAND4 is at a low level.

  The output of the NAND 4 is input to the AND 4 that gives a reset signal to the DFF 6 of the reverse rotation output request signal holding circuit 28. Therefore, when the NAND 4 outputs a low level signal, the DFF 6 is reset and the holding of the reverse pulse output request signal is released.

  Further, the second rotation direction even number switching determination circuit 36 outputs a forward rotation pulse output request signal to the forward rotation output request signal holding circuit 27 after the reverse rotation pulse output request signal is output from the reverse rotation output permission circuit 30. Further, based on the output of the reverse rotation pulse output request signal from the reverse rotation valid edge determination circuit 26 again, the output request signal held by the normal rotation output request signal holding circuit 27 is reset. Output a reset signal. That is, the second rotation direction even number switching determination circuit 36 determines that the rotor has switched the rotation direction twice from reverse rotation → forward rotation → reverse rotation, and sends a reset signal to the normal rotation output request signal holding circuit 27. Output.

  Specifically, as shown in FIG. 5, the second rotation direction even number switching determination circuit 36 includes a D flip-flop DFF8, a logical product circuit AND6, and a negative logical product circuit NAND5. A normal pulse output request signal is input to the clock terminal of DFF8, a pull-up power supply is connected to the data input terminal, and a reset signal similar to that of DFF6 is input to the reset terminal. Therefore, when the reverse rotation pulse output request signal is output from the reverse rotation output permission circuit 30, the DFF 8 takes in the pull-up power source input to the data input terminal and outputs the acquired signal level from the data output terminal. The output from the DFF 8 and the signal from the normal output request signal holding circuit 27 are input to the AND 6. For this reason, while the reverse rotation pulse output request signal is output from the reverse rotation output permission circuit 30 and the reverse rotation pulse is output from the reverse rotation pulse output circuit 32, the normal rotation pulse output request signal is sent to the normal rotation output request signal holding circuit 27. When held, the output of AND6 goes high. The output of the AND 6 and the output of the reverse rotation valid edge determination circuit 26 are input to the NAND 5. Therefore, when the output of the AND6 is at a high level, and further when the reverse rotation pulse output request signal is output from the reverse rotation valid edge determination circuit 26, the signal output of the NAND5 is at a low level.

  The output of the NAND 5 is input to the AND 3 that provides a reset signal to the DFF 5 of the normal output request signal holding circuit 27. For this reason, when the NAND 5 outputs a low level signal, the DFF 5 is reset, and the holding of the output request signal of the normal rotation pulse is released.

  As described above, the logic circuit 20 according to the present embodiment includes the first and second rotation direction even number of times switching determination circuits 35 and 36, so that the time deviation from the actual rotational motion of the rotor is achieved. It becomes possible to output a detection signal including a forward rotation pulse and a reverse rotation pulse that are suppressed.

  Further, in the present embodiment, when the rotation direction is switched even number of times, the output request signal of the held normal rotation pulse or reverse rotation pulse opposite to the normal rotation pulse or reverse rotation pulse being output is reset. Therefore, even when noise is applied and chattering occurs in the main sensor signal, a detection signal that is not affected by noise can be output. This is because even if chattering due to noise occurs, the main sensor signal finally returns to its original state due to the disappearance of noise, and the logic circuit 20 regards it as having been switched in an even number of rotations continuously. Because it is.

  FIG. 6 is a waveform diagram showing an example of a detection signal output by the signal processing circuit 10 of the present embodiment. FIG. 6 shows an example in which the rotor that has been rotated in the forward rotation direction repeatedly switches the rotation direction in a short cycle.

  In FIG. 6, the forward rotation pulse A is output from the signal processing circuit 10 in response to the occurrence of the forward rotation pulse output request signal due to the appearance of an effective edge when the rotor is rotating in the forward rotation direction. Even if the reverse rotation pulse output request signal is generated during the output of the forward rotation pulse A, the reverse rotation pulse a is not output immediately, but the output request signal is held in the reverse rotation output request signal holding circuit 28, Until the output of the forward rotation pulse A is completed, the output of the reverse rotation pulse a is waited.

  The output held in the reverse rotation output request signal holding circuit 28 when the output of the forward rotation pulse A is finished and the adjustment time for ensuring the interval between successive pulse signals has passed since the end of the output. Based on the request signal, a reverse pulse a is output.

  During the output of the reverse rotation pulse a (including the adjustment time after the reverse rotation pulse output is completed), the output request signal of the normal rotation pulse B is held in the normal rotation output request signal holding circuit 27, and thereafter, the output request of the reverse rotation pulse b is requested. When the signal is generated, the output request signal of the normal rotation pulse B held in the normal rotation output request signal holding circuit 27 is reset. As a result, it is possible to prevent a large time lag between the detection signal and the actual rotational motion of the rotor.

  Further, even when the output request signal for the reverse rotation pulse b is output from the reverse rotation effective edge determination circuit 26, the reverse rotation output request signal holding circuit 28 already holds the output request signal for the reverse rotation pulse a. The output request signal is maintained as it is. That is, the output request signal so far is held as it is without being affected by the generation of the output request signal of the new reverse rotation pulse b. In this case, the position of the gear teeth is not changed by merely changing the rotation direction of the rotor twice: reverse rotation → forward rotation → reverse rotation. Therefore, if a reverse rotation pulse is output again based on the output request signal of the reverse rotation pulse b, the gear tooth position may be erroneously detected by the reverse rotation pulse in the detection signal.

  For this reason, in the present embodiment, the output of the normal rotation pulse based on the output request signal of the normal rotation pulse B generated during the output of the reverse rotation pulse a and the output of the reverse rotation pulse based on the output request signal of the reverse rotation pulse b. We are trying not to do both together. As long as the rotor repeatedly switches the rotation direction in a short cycle, the signal processing operation as described above is repeatedly executed in the signal processing circuit 10.

1 Main magnetic sensor 2 Sub magnetic sensor 10 Signal processing circuit 20 Logic circuit Tr1 Transistor R1 Resistance

Claims (5)

When the crests and troughs of the gear teeth move from the plurality of magnetic sensors arranged to face the rotating body on which the gear teeth are formed, as the rotating body rotates in the normal direction or the reverse direction. When a rectangular wave-shaped first and second sensor signals having different phases are output, a detection signal for detecting the rotational position of the rotating body is output based on the first and second sensor signals. A signal processing circuit for the rotation detecting device,
Based on the phase relationship between the first and second sensor signals, a rotation direction determination unit that determines whether the rotation direction of the rotating body is a forward rotation direction or a reverse rotation direction;
In one rotation direction, when the rotation direction of the rotating body is a normal rotation direction and when the rotation direction is a reverse rotation direction, the first sensor signal of the peak portion side edge in the one rotation direction of the first sensor signal The change is defined as a signal change due to the effective edge in the one rotation direction, and in the other rotation direction, the change in the first sensor signal due to the rear end side edge of the peak portion in the other rotation direction is the other rotation direction. Effective edge determination means for determining whether or not the change in the first sensor signal is due to an effective edge, and determining that the signal change is due to an effective edge in the rotation direction;
The rotation is performed on the condition that the rotation direction discriminating means discriminates that the rotation direction is the normal rotation direction and the effective edge discrimination means discriminates that the change of the first sensor signal is due to the effective edge. Forward pulse output request holding means for holding a forward pulse output request signal indicating that the body is rotating in the forward rotation direction;
On the condition that the rotation direction discriminating means discriminates that the rotation direction is the reverse rotation direction and the effective edge discrimination means discriminates that the change of the first sensor signal is due to the effective edge. A reverse pulse output request holding means for holding a reverse pulse output request signal indicating that the motor is rotating in the reverse direction;
When the output request signal is held in one of the forward pulse output request holding means and the reverse pulse output request holding means, the held output request signal is output, and the forward pulse output request holding means When the output request signal is held in one of the other and the reverse pulse output request holding means, and the other is held in the other, until the output request signal held in one is reset Output request signal output means for waiting for output of the output request signal held in
According to the output request signal output from the output request signal output means, pulse output means for outputting a normal rotation pulse signal or a reverse rotation pulse signal as the detection signal;
After the output of the forward rotation pulse signal or the reverse rotation pulse signal by the pulse output means, the forward rotation pulse which is held in one of the normal rotation pulse output request holding means and the reverse rotation pulse output request holding means and whose output has ended. Or first reset means for resetting the output request signal of the reverse pulse;
While the output request signal is held in one of the forward pulse output request holding means and the reverse pulse output request holding means, the output request signal is also held in the other, and the output already held in one And a second reset means for resetting the output request signal held in the other when a condition for holding the output request signal is satisfied with respect to the request signal. .   When the output request signal held on the other of the forward pulse output request holding means and the reverse pulse output request holding means is reset by the second reset means, the forward pulse output request holding means and the reverse pulse 2. The signal processing of the rotation detection device according to claim 1, wherein one of the output request holding means holds the output request signal as it is without being affected by the establishment of the condition for holding the output request signal. circuit. A timer means for measuring time,
The timer means counts the elapsed time from the time when the output of the forward rotation pulse or the reverse rotation pulse is started from the pulse output means, and when the elapsed time reaches a predetermined time, the timer means The signal processing circuit of the rotation detecting device according to claim 1 or 2, wherein the end of the output of the forward rotation pulse or the reverse rotation pulse is instructed. The timer means separately has a predetermined time for a forward rotation pulse and a predetermined time for a reverse rotation pulse as a predetermined time to be compared with the elapsed time, so that the pulse width of the forward rotation pulse and the reverse rotation pulse The signal processing circuit of the rotation detecting device according to claim 3 , wherein the width is made different.   The timer means gives a reset instruction to the first reset means when a predetermined adjustment time has elapsed after the end of the output of the normal pulse signal or reverse pulse signal by the pulse output means, and the first reset In response to the reset instruction, the means resets the output request signal of the forward rotation pulse or the reverse rotation pulse that is held in one of the forward rotation pulse output request holding means and the backward rotation pulse output request holding means. The signal processing circuit of the rotation detection device according to claim 3, wherein the signal processing circuit is a rotation detection device.

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