JP4779908B2 - Circuit design support system, circuit design support method, and program - Google Patents

Description

  The present invention relates to a circuit design support system, a circuit design support method, and a program, and more particularly to a circuit design support system and a circuit design support method having a function of analyzing a circuit generated by behavioral synthesis and displaying a correction location related to a delay defect. And the program.

  In circuit design, it is important to design so as to maximize the performance of the circuit while satisfying various constraints (synthesis constraints) such as delay constraints, area constraints, and power consumption constraints given by specifications. An example of a conventional circuit design support system that supports circuit design from such a viewpoint is described in Non-Patent Document 1 and Patent Document 1. A conventional circuit design support system stores a behavioral level description (behavioral level description) as an input, an intermediate description, and a register transfer level description (register transfer level description; hereinafter simply referred to as “RTL description”) as an output. It comprises a device, a data processing device including behavioral synthesis means, an input device, and an output device such as a behavior level description display unit and an RTL description display unit.

  Here, the intermediate description is a process in which the behavioral synthesis means generates a RTL description that is a hardware description having an abstraction level from a behavioral level description that directly describes a target processing algorithm at a behavioral level. A description that expresses the specifications of a synthesis target circuit that is generated along the way.

  The circuit design in the conventional circuit design support system having such a configuration is performed as follows.

  The circuit designer describes the operation of the desired circuit in the behavior level description and transfers it to the storage unit. As this behavior level description, for example, there is a behavior level description described in one of programming languages, C language (see FIG. 3). Next, the behavioral synthesis means is operated on the stored behavior level description to perform behavioral synthesis processing (also referred to as high-level synthesis or function synthesis). The behavioral synthesis process includes a scheduling process, a binding process, an optimization process, and the like.

  In the scheduling step, the operation time is determined for each process of the operation level description for which the operation time is not determined. In the binding process, hardware resources for each process of the behavior level description are determined. The optimization process is performed at each stage of behavioral synthesis, and includes language level optimization such as loop optimization and logic optimization as a post process. In each of these behavioral synthesis processing steps, behavioral synthesis means generates an intermediate description. When all the processes are completed, an RTL description as shown in FIG. 5 is generated. The obtained RTL description is passed to a downstream design process and realized as a circuit.

  If there is a delay constraint violation, area constraint violation, power consumption constraint violation, etc. in the circuit described in the above RTL description, the realized circuit does not perform the desired operation or cannot satisfy the required specifications. It has no value as a product. Therefore, after the intermediate description and RTL description are generated, performance analysis is performed, and the generated intermediate description and RTL description have no problem. Specifically, circuit performance such as maximum delay, area used, and power consumption. Is analyzed using an analysis means.

  For example, Patent Document 2 discloses an electric circuit characteristic analysis apparatus and method for analyzing circuit area, delay, and power consumption by using an RTL description as an input. As a result of the above analysis, if the conditions required for the circuit to operate cannot be satisfied, the circuit designer performs performance in the RTL description or intermediate description to be analyzed through interactive processing with the same device. Discover places that can't be met. Then, the circuit designer specifies the location in the behavior level description or the operation of the behavioral synthesis that causes a place that does not satisfy the above performance by the correspondence table showing the correspondence between the behavior level description and the RTL description.・ It is said that the time loss during design rework can be reduced by correcting and implementing behavioral synthesis again.

  Further, for example, Patent Document 3 describes a circuit design support system having a function of displaying a delay report indicating an analysis result relating to delay among the indexes (characteristic values of Patent Document 2) to be subjected to the failure analysis. ing.

  FIG. 25 is a diagram showing a configuration of a circuit design support system equivalent to the system described in Patent Document 3. Referring to the figure, this circuit design support system includes storage units 121 to 123 that store behavior level descriptions, intermediate descriptions, and RTL descriptions, behavior synthesis means 111, display units 101 such as behavior level descriptions and RTL descriptions, In addition to 102, the delay path information display unit 103, the delay path information input unit 105, the delay path information analysis unit 112, the correspondence relationship storage unit 124, the delay path information storage unit 125, and the like are provided.

  In the circuit design support system equivalent to Patent Document 3, the result of delay analysis is displayed as follows. The result of delay analysis of the RTL description generated by behavioral synthesis is input from the delay path information input unit 105 and stored in the delay path information storage unit 125. At the same time, the delay path information is displayed on the delay path information display unit 103. In the delay path information display unit 103, when the designer or operator arbitrarily selects one delay path, the description part regarding the delay path is displayed in the behavior level description display unit 101 based on the information regarding the selected delay path. In addition, the RTL description display unit 102 displays a description portion relating to the delay path in a distinguishable manner. The designer or operator changes the description of the behavior level description so as to reduce the delay based on the distinguished display information, executes the behavioral synthesis again to generate the RTL description, and performs the delay analysis. By continuing this series of operations, it is possible to generate a circuit free from delay related problems.

JP-A-6-60143 Japanese Patent Laid-Open No. 10-187873 JP-A-2005-242812 High-Level Synthesis: Daniel Gajsky, Nikil Dutt, Allen Wu, Steve Lin: Kluwer Academic Publishers, 1992

  However, the delay circuit analysis function of the conventional circuit design support system has a problem that the number of paths that can be selected when the corresponding part is distinguished and displayed is limited to one.

  For example, when the circuit designer refers to the delay path information and selects only one path with the largest degree of delay, displays the behavior level description and RTL description related to the corresponding path separately, and makes the description improvement target think of. Here, if the circuit designer changes the behavior level description or the behavioral synthesis method in order to improve the delay value by focusing only on the route having the largest delay degree, the delay value of the corresponding route is improved. As a side effect, it may occur that the delay of a route that has not had a large degree of delay failure deteriorates. In extreme cases, a series of operations for behavioral synthesis, delay analysis, and behavior level description improvement may not converge at all.

  In the above conventional circuit design support system, it may be possible to select a plurality of delay paths, but the behavior level description and the RTL description related to the plurality of paths are all the same for unrelated parts. Will be displayed separately. Then, as the number of selected delay paths increases, the longer the longer the selected delay paths, the more description parts are displayed for distinction. As a result, there is another problem that it becomes difficult to specify the description parts to be improved. It will occur.

  The present invention has been made in view of the above-described circumstances, and for the corresponding portion in the behavior level description corresponding to a plurality of paths having a delay defect, the effectiveness of the correction of the corresponding portion and the change of the behavioral synthesis method The present invention provides a circuit design support system, a circuit design support method, and a program that can provide information related to the above.

  According to a first aspect of the present invention, there is provided a circuit design support system that presents delay path information indicating a delay state of a path in a circuit to a user and outputs a behavior level description corresponding to the delay path selected by the user. And means for accepting selection of a plurality of routes from the user, and calculating the degree of influence of the modification of the corresponding portion in the behavior level description corresponding to the selected plurality of routes or the change of the behavioral synthesis method for the corresponding portion. And a means for displaying the calculated degree of influence in association with the corresponding location in the behavior level description. A circuit design support system is provided.

  According to the second aspect of the present invention, the behavior level is presented by presenting to the user the delay route information indicating the delay state of the route in the circuit, and outputting the behavior level description corresponding to the delay route selected by the user. A circuit design support method in a circuit design support system that prompts modification of a description or a change of a behavioral synthesis method, wherein the circuit design support system analyzes the delay path information and outputs information for selecting a delay path The step of accepting selection of a plurality of paths, and the influence of the modification of the corresponding part in the behavior level description corresponding to the plurality of selected paths or the change of the behavioral synthesis method for the corresponding part by the circuit design support system A step of calculating a degree, and the circuit design support system displays the calculated degree of influence in association with the corresponding part in the behavior level description. Include Tsu and up, the circuit design support method according to claim is provided.

According to the third aspect of the present invention, the behavior level is presented by presenting to the user the delay route information indicating the delay state of the route in the circuit, and outputting the behavior level description corresponding to the delay route selected by the user. A program to be executed by a circuit design support system that prompts modification of a description or change of a behavioral synthesis method, analyzes the delay path information, outputs information for selecting a delay path, and accepts selection of a plurality of paths Processing, processing for calculating the degree of influence of the modification of the corresponding part in the behavior level description corresponding to the plurality of selected paths or the change of the behavioral synthesis method for the corresponding part, and the calculated degree of influence, There is provided a program for causing the circuit design support system to execute a process of displaying in correspondence with the corresponding portion in the behavior level description (or RTL description). The degree of influence in the first to third viewpoints described above is affected by the modification of the corresponding part in the behavior level description corresponding to the plurality of selected paths or the change of the behavioral synthesis method for the corresponding part. Either the number of paths extending, or the number of corresponding locations in the behavior level description corresponding to the plurality of selected paths appearing as nodes in the plurality of selected paths can be used.

  According to the present invention, when there is a defect related to a delay in a circuit, it is easy to determine a part (part where the defect countermeasure is most effective) on which to take a countermeasure such as improvement of behavior level description or change of a behavioral synthesis method. The The reason is that the information indicating the degree of influence when the description is improved or the behavioral synthesis method is changed is displayed in association with the corresponding part of the behavior level description.

  Further, according to the present invention, the possibility that a defect related to delay occurs in the circuit is reduced, and as a result, the circuit design period can be shortened.

Next, the best mode for carrying out the present invention will be described in detail with reference to the drawings.
FIG. 1 is a block diagram showing the configuration of a circuit design support system according to an embodiment of the present invention.

  Referring to FIG. 1, the circuit design support system according to the embodiment of the present invention includes an input / output device 100, a data processing device 110 that operates under program control, and a storage device 120.

  The input / output device 100 includes a behavior level description display unit 101, an RTL description display unit 102, a delay path information display unit 103, a delay path histogram display unit 104, and a delay path information input unit 105. Each of the former display units is configured such that the user can easily access related information by, for example, dividing / switching screens or using multi-window technology.

  The data processing device 110 includes a behavioral synthesis unit 111, a delay path information analysis unit 112, and a delay distribution calculation unit 113.

  The storage device 120 includes a behavior level description storage unit 121, an intermediate description storage unit 122, an RTL description storage unit 123, a correspondence relationship storage unit 124, and a delay path information storage unit 125.

  Each means of the data processor 110 operates as follows. The behavioral synthesis unit 111 performs behavioral synthesis on the behavioral level description of the circuit stored in the behavioral level description storage unit 121. More specifically, the process described at the operation level is executed in several states so as to satisfy the synthesis constraints such as the operation frequency and the type and number of hardware resources (registers, arithmetic units, etc.). Such conversion is performed. The behavior level description is displayed on the behavior level description display unit 101 and can be corrected by editing means such as an editor (not shown).

  The intermediate description generated in the process of behavioral synthesis is stored in the intermediate description storage unit 122, and the RTL description is stored in the RTL description storage unit 123. The generated RTL description is displayed on the RTL description display unit 102. The correspondence information between the behavior level description and the RTL description associated using the method described in Patent Document 3 is stored in the correspondence storage unit 124 by the behavioral synthesis unit 111.

  The delay path information analysis unit 112 analyzes the delay path information input from the delay path information input unit 105 and stored in the delay path information storage unit 125, and the result is displayed as a delay path information display unit 103 and a delay path histogram display unit. 104 (see FIGS. 23 and 24).

  The delay distribution calculating unit 113 refers to the delay path information and the correspondence information, and corresponds to one or more delay paths specified by the user based on the information displayed on the delay path information display unit 103 or the delay path histogram display unit 104. For the corresponding part of the behavior level description, the degree of influence of the modification of each corresponding part and the change of the behavioral synthesis method is calculated. The calculated degree of influence is displayed in the vicinity of the corresponding portion of the behavior level description displayed on the behavior level description display unit 101 directly or numerically in a manner that allows the weight to be determined directly or numerically. The

  Further, the delay distribution calculation means 113 is a behavior level description display unit that can determine a numerical value or its weight based on correspondence information between the behavior level description and the RTL description stored in the correspondence storage unit 124. The influence level displayed in 101 is also output to the corresponding part of the RTL description display unit 102.

  Next, the overall operation of this embodiment will be described in detail with reference to the flowcharts of FIGS. 1 and 2.

  First, the user uses the input / output device 100 to transfer an input behavior level description to the storage device 120 (step A1 in FIG. 2).

  The transferred behavior level description is stored in the behavior level description storage unit 121 and also displayed on the behavior level description display unit 101. The user can edit the transferred behavior level description via the behavior level description display unit 101 and editing means such as an editor (not shown).

  The user designates a behavioral synthesis method (synthesis constraint) using the behavioral synthesis unit 111 and executes behavioral synthesis processing for the stored behavior level description (step A2 in FIG. 2). The intermediate description generated in the process of the behavioral synthesis process is stored in the intermediate description storage unit 122. The RTL description generated by the behavioral synthesis process is stored in the RTL description storage unit 123 and displayed on the RTL description display unit 102.

  When the behavioral synthesis process is performed, correspondence information between the behavior level description as an input and the RTL description as an output is stored in the correspondence relationship storage unit 124. The correspondence information stored in the correspondence relationship storage unit 124 is used when grasping the correspondence relationship between the behavior level description and the RTL description.

  Next, delay path information indicating the delay status of the path included in the circuit according to the generated RTL description is acquired. The delay path information acquisition method includes a method (step A3 in FIG. 2) of calculating circuit delay path information using a delay path calculation means (static timing analysis means) (not shown) in the circuit design support system. Two kinds of methods (step A4 in FIG. 2) of inputting the delay path information calculated externally through the delay path information input unit 105 are prepared. The delay path information acquired by each method is stored in the delay path information storage unit 125 and displayed on the delay path information display unit 103.

  When the delay path information is calculated or input, the delay path information analyzing unit 112 analyzes the delay path information and displays the result on the delay path information display unit 103 and / or the delay path histogram display unit 104 ( Step A5 in FIG.

  Subsequently, the user who refers to the contents displayed on the delay path information display unit 103 or (and) the delay path histogram display unit 104 selects a path as a target for countermeasures against delay problems (step A6 in FIG. 2). ). In the circuit design support system according to the present embodiment, a plurality of paths can be selected.

  When the path is selected, the delay distribution calculating unit 113 corrects each corresponding part or changes the behavioral synthesis method for the corresponding part in the behavior level description corresponding to one or more delay paths selected by the user. The degree of influence indicating the range or degree of influence of each delay elimination measure is calculated (step A7 in FIG. 2). In the case where there are a plurality of selected routes, similarly, for the corresponding portions of the behavior level description corresponding to the plurality of routes, the influence of the modification or the behavioral synthesis method change is calculated.

  Finally, information indicating the degree of influence of the modification of the corresponding part in the behavior level description calculated in step A7 and the change of the behavioral synthesis method is reflected in the corresponding part of the behavior level description display unit 101 and the RTL description display unit 102 ( Display) (step A8 in FIG. 2). Based on this information, the user selects a corresponding portion that seems to have the highest delay improvement effect and attempts to improve the delay defect.

  As described above, according to the present embodiment, a plurality of paths of the circuit to be designed are selected, a corresponding portion of the behavior level description that greatly affects the delay is identified among the plurality of paths, and is presented to the user. It becomes possible to do. As a result, a series of flows such as behavioral synthesis, delay analysis, and behavior level description correction are converged, and the efficiency of the work for improving the delay defect is achieved.

  The influence distribution calculated by the delay distribution calculating unit 113 and reflected (displayed) on the behavior level description display unit 101 and the RTL description display unit 102 is the correspondence in the behavior level description corresponding to the selected delay path. The number of paths that are affected by correcting the location or changing the behavioral synthesis method for the corresponding location, or the number of corresponding locations in the behavior level description that appear as nodes in the selected plurality of routes ( The number of occurrences of nodes in all selected routes) can be adopted.

  Subsequently, in order to more specifically describe the operation and effect of the present invention, a detailed description will be given with a comparison with the prior art in the case of improving the delay defect of a simple circuit.

(Prerequisite)
In the following, a case where a specific delay improvement is performed from the behavior level description sample shown in FIG. 3 will be described. The behavior level description in FIG. 3 is written in C language, but other behavior level descriptions include parts such as terminals and registers and a language that has been extended for hardware so that parallel operations can be described. , C ++ language, SystemC, Verilog-HDL, VHDL, etc. are used.

  As described above, when the behavioral synthesis process is performed by the behavioral synthesis unit 111, constraint information on behavioral synthesis such as a behavioral synthesis method and parameters must be input. Various variations can be considered depending on the process, library, etc., but here, for the sake of simplicity, the operation shown in FIG. 3 under the constraint that only one of the three types of adders shown in FIG. 4 can be used. Consider the synthesis of level descriptions. One clock is 10 ns.

  As described above, when behavioral synthesis is executed, the behavioral level description is converted into the RTL description through the intermediate description, the intermediate description is stored in the intermediate description storage unit 122, and the RTL description is stored in the RTL storage unit 123. .

  FIG. 5 is an example of an RTL description generated by behavioral synthesis by specifying a condition that one adder of FIG. 4 is used for the behavior level description shown in FIG. .

  The user can view the behavior level description on the behavior level description display unit 101 and the RTL description on the RTL description display unit 102, respectively.

  In the behavior level description 300 of FIG. 3, there are three types of descriptions 301, 302, and 303 that use an adder. On the other hand, in the RTL description 304 shown in FIG. 5, a description 305 corresponding to the description 301 of the behavior level description 300 is generated, and adder3 is used as an adder. Similarly, in the description 306 corresponding to the description 302, adder5 is used as an adder. In addition, in the description 307 corresponding to the description 303, adder2 is used as an adder. The correspondence relationship between the behavior level description and the RTL description as described above is stored in the correspondence relationship storage unit 124.

  The delay path information analyzing unit 112 analyzes the delay path information stored in the delay path information storage unit 125 and displays it on the delay path information display unit 103. The delay distribution calculation means 113 refers to the delay path information stored in the delay path information storage unit 125, and the number of paths affected by the improvement of each description of the behavior level description corresponding to the delay path and the change of the synthesis method. Is calculated.

  FIG. 6 is a circuit diagram corresponding to the RTL description 304 shown in FIG. 7 and 8 show the contents displayed on the delay path information display unit 103. FIG. As shown in FIG. 7, there are four paths from the input terminals in1 and in2 to out1 and out2 in FIG. In FIG. 6, when the delay values of the wiring in1, the wiring in2, the wiring a, and the wiring out1 are 1 ns and the delay value of the wiring out2 is 2 ns, the delay values of the paths in FIG. 7 are as shown in FIG.

  Here, in FIG. 8, the value of FIG. 4 is used for the internal delay of each adder. Since one clock is set to 10 ns, the path Path1 and the path Path4 having a delay value of 11 ns have a defect related to delay. The path Path2 and the path Path3 have a delay value of 9 ns, and thus are circuits that satisfy the specifications regarding delay. In this case, it is necessary to correct the delay values of the path Path1 and the path Path4 to be 10 ns or less.

(Conventional circuit design support system)
In the conventional circuit design support system in which a plurality of delay paths cannot be selected, the delay path information display unit 103 first selects one of the path Path 1 and the path Path 4 having the largest degree of delay fault to take a countermeasure for the delay fault. Think. Here, an example in which a delay elimination measure is implemented for the path Path1 will be described.

  FIG. 9 is a diagram showing the contents displayed on the delay path information display unit 103 when the path Path1 is selected in the conventional circuit design support system. Referring to FIG. 9, the path Path1 is a path from the input terminal in1 to the output terminal out1 via the intermediate variable a.

  FIG. 10 is a diagram showing the contents displayed on the behavior level description display unit 101 when this path Path1 is selected. Referring to FIG. 10, the behavior level descriptions related to the path Path1 (the description 301 corresponding to the path from the input terminal in1 to the intermediate variable a and the description 302 corresponding to the path from the intermediate variable a to the output terminal out1) The behavior level description and the shading are displayed separately.

  The conventional circuit design support system tries to improve the description or change the synthesis method for the two descriptions 301 and 302 described above.

  Here, referring to FIG. 4, when adder3 is placed in the next stage of adder5, the delay value of adder5 becomes 4 ns, and in FIG. 6, the two adders constituting the path Path1 are added to adder3 and adder5. It can be seen that if the order of the adders is reversed, the delay value is improved by 1 ns.

  FIG. 11 shows a behavior level description in which comment is attached to a change in the behavioral synthesis method to be attempted under the above examination. As commented in FIG. 11, the delay value of the path Path1 is improved by 1 ns by performing behavioral synthesis by specifying adder5 as the adder corresponding to the description 301 and adder3 as the adder corresponding to the description 302. can do.

  FIG. 12 is an example of an RTL description obtained as a result of attempting behavioral synthesis again for the behavioral level description of FIG. 3 under the above conditions. The description 309 in the RTL description 308 of FIG. 12 uses adder5, and the description 310 uses adder3. It can be seen that the order of the path Path1 has been changed.

  FIG. 13 is a circuit diagram corresponding to the RTL description 308 of FIG. 14 and 15 show the contents displayed on the delay path information display unit 103 at this time. As shown in FIG. 14, there are four paths from the input terminals in1, in2 to out1, out2 in FIG. In FIG. 13, when the delay values of the wiring in1, the wiring in2, the wiring a, and the wiring out1 are 1 ns, and the delay value of the wiring out2 is 2 ns, the delay values of the paths in FIG. 14 are as shown in FIG.

  Referring to FIG. 15, the path Path1 and the path Path4 are improved by 1 ns and the delay value is 10 ns due to the change of the behavioral synthesis method, so that the specifications regarding the delay are satisfied. However, the path Path2 and the path Path3 that had no problem before the change of the behavioral synthesis method have a delay value of 11 ns, and a defect related to delay has newly occurred for one clock (10 ns).

  Since such a phenomenon focuses only on the improvement of the path Path1 having the greatest degree of delay failure, the improvement has affected other routes that may potentially have a delay failure. to cause. The actual problem is a case that frequently occurs when taking measures against delay defects.

  In short, it is possible to suggest a location where a countermeasure for resolving a delay defect seen from the local (specific one path) of the conventional circuit design support system can be suggested, but it is impossible to predict the effect of the countermeasure on other paths. In addition, there is a cause for the above phenomenon to occur.

(Circuit design support system of the present invention)
Next, an example will be described in which a delay elimination measure is performed using the circuit design support system according to the present invention for the state where the first behavioral synthesis trial is executed and the delay analysis result of FIG. 8 is acquired. In the design support system of the present invention, since a plurality of delay paths can be selected, the delay path information display unit 103 selects both the path Path1 having the largest degree of delay fault and the path Path2 sharing adder3, and delay faults are displayed. Can be considered. Note that the path Path2 is a path in which the delay defect is worsened when the delay defect handling of the path Path1 is performed in the conventional circuit design support system.

  FIG. 16 is a diagram showing the contents displayed on the delay path information display unit 103 when both the path Path1 and the path Path2 are selected in the circuit design support system according to the present invention. Referring to FIG. 16, the path Path1 is a path from the input terminal in1 through the intermediate variable a to the output terminal out1, and the path Path2 is a path from the input terminal in2 through the intermediate variable a to the output terminal out2. is there.

  As is apparent from FIG. 6, the description 301 corresponding to the path from the input terminal in1 to the intermediate variable a is included in both the selected path Path1 and the path Path2, but is output from the intermediate variable a. The description 302 corresponding to the route to the terminal out1 and the description 303 corresponding to the route from the intermediate variable a to the output terminal out2 are included only in the route Path1 and the route Path2, respectively.

  FIG. 17 is a diagram showing the contents displayed on the behavior level description display unit 101 when the path Path1 and the path Path2 are selected. Referring to FIG. 17, behavior level descriptions related to both the path Path1 and the path Path2 (a description 301 corresponding to a path from the input terminal in1 to the intermediate variable a, a description corresponding to a path from the intermediate variable a to the output terminal out1) 302 and description 303) corresponding to the path from the intermediate variable a to the output terminal out2 are displayed in a shaded manner with respect to other behavior level descriptions. In particular, the description 301 is highlighted with darker shades than the description 302 and the description 303.

  The shading shading is based on the number of paths affected by the improvement of each description of the behavior level description calculated by the delay distribution calculating unit 113 and the change of the synthesis method. As a result, the user is greatly affected by the improvement of the description 301 or the change of the synthesis method (path Path1 and route Path2), and the influence of the improvement of the description 302 or the description 303 or the change of the synthesis method is small (route Path1, Any one of the paths Path2) can be determined.

  Also in the RTL description display unit 102, the description 305 in FIG. 5 is darkly shaded based on the correspondence information stored in the correspondence storage unit 124 and the description 306 in FIG. The description 307 is displayed in a thin shaded manner (not shown).

  As described above, in the circuit design support system according to the present invention, the location on the behavior level description through which more delay paths pass, in the above example, the degree of influence of the countermeasures on the location is large, and the delay defect is improved. The description 301 (description 305 in FIG. 5), which has the highest overall effect when attempting to, is explicitly distinguished from the other description 302 (description 306 in FIG. 5) and description 303 (description 307 in FIG. 5). Since it is displayed, the user can easily narrow down the description candidates to try to improve the description or change the synthesis method (in this case, description 301).

  For example, according to FIG. 17, although the description 301 affects the delay values of more paths than the description 303, an adder adder3 (delay 3 ns) having a larger delay value is used. If the adder used in the description 301 is replaced with adder2 (delay 2 ns) and the adder used in the description 303 is replaced with adder3 (delay 3 ns), the delay value of the description 303 is deteriorated, but the delay value of the description 301 is improved. As a result, the delay value of the entire circuit may be improved.

  FIG. 18 shows a behavior level description in which a change in the behavioral synthesis method to be attempted is attached with comments under the above examination. As commented in FIG. 18, by specifying adder2 as the adder corresponding to the description 301 and adder3 as the adder corresponding to the description 303, and performing behavioral synthesis, the delay values of all the paths Path1 are set to 1 ns. Can be improved.

  FIG. 19 is an example of an RTL description obtained as a result of attempting behavioral synthesis again for the behavioral level description of FIG. 3 under the above conditions. The description 313 in the RTL description 312 in FIG. 19 uses adder2, the description 314 uses adder5, the description 315 uses adder3, and adder2 with the least delay is used. You can see that it was placed at the top.

  FIG. 20 is a circuit diagram corresponding to the RTL description 312 of FIG. 21 and 22 show the contents displayed on the delay path information display unit 103 at this time. As shown in FIG. 21, there are four paths from the input terminals in1 and in2 to out1 and out2. In FIG. 20, when the delay values of the wiring in1, the wiring in2, the wiring a, and the wiring out1 are 1 ns and the delay value of the wiring out2 is 2 ns, the delay values of the paths in FIG. 21 are as shown in FIG.

  Referring to FIG. 22, the delay values of all the paths Path1 to Path4 are 10 ns or less due to the change of the behavioral synthesis method, so that the specification regarding the delay is satisfied. In this way, by using the circuit design support system according to the present invention, it becomes possible to identify a place where a delay elimination measure considering many delay defects of the circuit is to be taken. It can be carried out with a shorter man-hour.

  Further, in the above-described example, it has been described that the user selects an arbitrary delay path based on the information of FIG. 7 or 8 displayed on the delay path information display unit 103. Here, FIG. As described above, in the delay path information display unit 103, all paths are aligned according to the delay value, and all paths having a delay value equal to or greater than a certain threshold value (arrow in the figure) selected by the designer can be comprehensively selected. By doing so, measures can be taken more efficiently for circuits with many delay problems.

  Also, as shown in FIG. 24, the delay values of all routes are displayed as a histogram on the delay route histogram display unit 104, and values such as 10% and 1σ (arrows in the figure) are designated, and the route belongs to the top of the histogram. It is also possible to adopt a method for comprehensive selection.

  As described above, the preferred embodiment of the present invention and specific examples thereof have been described. However, in the delay defect correcting step of the circuit, a plurality of paths can be selected, and description of the behavior level description corresponding to the plurality of paths is provided. It can be said that various modifications can be made without departing from the gist of the present invention that the degree of influence of the improvement of each description or the change of the synthesis method is presented to the user (circuit designer) every time. Not too long.

  For example, in the specific example described above, the number of paths affected by the improvement of each description or the change of the synthesis method was 1-2, so the display was made in two stages, but depending on the specific numerical display, coloring, etc. Needless to say, the corresponding portions of the behavior level description and the RTL description corresponding to the number of stages can be distinguished and displayed. Rather than being displayed or written together in the behavior level description and RTL description, the degree of influence of each description (line number, etc.), improvement of each description, and change of the synthesis method in a separate window or a predetermined display area A table or the like in which (the number of affected routes, the number of appearances of nodes on all selected routes, etc.) are associated with each other may be displayed.

  The present invention can be applied not only to a circuit design support system that supports circuit design from a behavior level description, but also to an application such as a system that analyzes the result of behavioral synthesis.

1 is a block diagram illustrating a configuration of a circuit design support system according to an embodiment of the present invention. It is a flowchart which shows operation | movement of the circuit design support system which concerns on one Embodiment of this invention. It is a sample of the behavior level description for demonstrating the Example of this invention. It is a figure which shows the constraint information (adder) input when implementing behavioral synthesis with respect to the behavior level description of FIG. It is an example of the RTL description produced | generated by the behavioral synthesis from the behavior level description of FIG. FIG. 6 is a circuit diagram corresponding to the RTL description of FIG. 5. It is a figure which shows the path | route list of the circuit diagram of FIG. 6 displayed on a delay path | route information display part. It is a figure which shows the delay value list | wrist of the path | route of the circuit diagram of FIG. 6 displayed on a delay path | route information display part. It is a figure showing the content displayed on a delay path information display part at the time of path selection in the conventional circuit design support system. It is a figure showing the content displayed on a behavior level description display part at the time of route selection in the conventional circuit design support system. It is a figure for demonstrating the improvement measure (change of the behavioral synthesis method) obtained by utilizing the conventional circuit design support system. FIG. 12 is an example of an RTL description obtained as a result of attempting behavioral synthesis again for the behavior level description of FIG. 3 under the conditions of FIG. FIG. 13 is a circuit diagram corresponding to the RTL description of FIG. 12. It is a figure which shows the path | route list of the circuit diagram of FIG. 13 displayed on a delay path | route information display part. It is a figure which shows the delay value list | wrist of the path | route of the circuit diagram of FIG. 13 displayed on a delay path | route information display part. It is the figure showing the content displayed on a delay path information display part at the time of path selection in the circuit design support system concerning the present invention. It is a figure showing the content displayed on a behavior level description display part at the time of route selection in the circuit design support system which concerns on this invention. It is a figure for demonstrating the improvement measure (change of the behavioral synthesis method) obtained by utilizing the circuit design support system which concerns on this invention. FIG. 19 is an example of an RTL description obtained as a result of another attempt to perform behavioral synthesis for the behavior level description of FIG. FIG. 21 is a circuit diagram corresponding to the RTL description of FIG. 20. It is a figure which shows the path | route list of the circuit diagram of FIG. 20 displayed on a delay path | route information display part. It is a figure which shows the delay value list | wrist of the path | route of the circuit diagram of FIG. 20 displayed on a delay path | route information display part. It is an example of the delay path | route list displayed on a delay path | route information display part. It is an example of the histogram by the delay value displayed on a delay path information display part. It is a figure showing the structure of the circuit design support system equivalent to a prior art (patent document 3).

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Input / output apparatus 101 Action level description display part 102 RTL description display part 103 Delay path information display part 104 Delay path histogram display part 105 Delay path information input part 110 Data processing apparatus 111 Behavior synthesis means 112 Delay path information analysis means 113 Delay distribution Calculation means 120 Storage device 121 Behavior level description storage unit 122 Intermediate description storage unit 123 RTL description storage unit 124 Correspondence relationship storage unit 125 Delay path information storage unit 300 Behavior level description 301 Behavior level description 302 using an adder Behavior level description 303 behavior level description 304 using an adder. Behavior synthesis of RTL description 307 corresponding to RTL description 306 302 corresponding to RTL description 305 301 obtained by behavioral synthesis of behavior level description 308 300 Obtained The RTL description 315 corresponding to the RTL description 313 301 corresponding to the RTL description 313 301 obtained by behavioral synthesis of the RTL description 311 300 corresponding to the RTL description 311 303 corresponding to the RTL description 310 302 corresponding to the RTL description 309 301. RTL description corresponding to 303

Claims (27)

A circuit design support system for presenting delay path information indicating a delay state of a path in a circuit to a user and outputting a behavior level description corresponding to the delay path selected by the user,
Means for accepting multiple route selections from the user;
Means for calculating the number of paths affected by the modification of the corresponding part in the behavior level description corresponding to the plurality of selected paths or the change of the behavioral synthesis method for the corresponding part;
Means for displaying the calculated number of paths in association with the corresponding part in the behavior level description;
A circuit design support system characterized by A circuit design support system for presenting delay path information indicating a delay state of a path in a circuit to a user and outputting a behavior level description corresponding to the delay path selected by the user,
Means for accepting multiple route selections from the user;
Means for calculating the number of corresponding portions in the behavior level description corresponding to the plurality of selected paths appearing as nodes in the plurality of selected paths;
Means for displaying the calculated number of nodes in association with the corresponding part in the behavior level description;
A circuit design support system characterized by A circuit design support system for presenting delay path information indicating a delay state of a path in a circuit to a user and outputting an RTL description (register transfer level description) corresponding to the delay path selected by the user,
Means for accepting multiple route selections from the user;
Means for calculating the number of paths affected by the modification of the corresponding part in the behavior level description corresponding to the plurality of selected paths or the change of the behavioral synthesis method for the corresponding part;
Means for displaying the calculated number of paths in association with the RTL description corresponding to the corresponding part in the behavior level description;
A circuit design support system characterized by A circuit design support system for presenting delay path information indicating a delay state of a path in a circuit to a user and outputting an RTL description (register transfer level description) corresponding to the delay path selected by the user,
Means for accepting multiple route selections from the user;
Means for calculating the number of corresponding portions in the behavior level description corresponding to the plurality of selected paths appearing as nodes in the plurality of selected paths;
Means for displaying the calculated number of nodes in association with the RTL description corresponding to the corresponding location in the behavior level description;
A circuit design support system characterized by A circuit design support system for presenting delay path information indicating a delay state of a path in a circuit to a user and outputting an operation level description and an RTL description corresponding to the delay path selected by the user,
Means for accepting multiple route selections from the user;
Means for calculating the number of paths affected by the modification of the corresponding part in the behavior level description corresponding to the plurality of selected paths or the change of the behavioral synthesis method for the corresponding part;
Means for displaying the calculated number of paths in association with the corresponding part in the behavior level description and the corresponding part of the RTL description corresponding to the corresponding part in the behavior level description. ,
A circuit design support system characterized by A circuit design support system for presenting delay path information indicating a delay state of a path in a circuit to a user and outputting an operation level description and an RTL description corresponding to the delay path selected by the user,
Means for accepting multiple route selections from the user;
Means for calculating the number of corresponding portions in the behavior level description corresponding to the plurality of selected paths appearing as nodes in the plurality of selected paths;
And means for displaying the calculated number of nodes in association with the corresponding part in the behavior level description and the corresponding part of the RTL description corresponding to the corresponding part in the behavior level description, respectively. thing,
A circuit design support system characterized by Furthermore, a delay path calculation unit for calculating delay path information from the RTL description is provided.
The circuit design support system according to any one of claims 1 to 6. Furthermore, a means for displaying a delay path list created by arranging all paths in order of delay values is provided.
The circuit design support system according to claim 1, wherein: Furthermore, a means for displaying a histogram created using the delay values of all the routes is provided.
The circuit design support system according to claim 1, wherein: The delay path information indicating the delay state of the path in the circuit is presented to the user, and the behavior level description corresponding to the delay path selected by the user is output, thereby prompting the modification of the behavior level description or the behavior synthesis method. A circuit design support method in a circuit design support system,
The circuit design support system analyzes the delay path information, outputs information for selecting a delay path, and accepts selection of a plurality of paths;
The circuit design support system calculating the number of paths affected by the modification of the corresponding part in the behavior level description corresponding to the selected plurality of paths or the change of the behavioral synthesis method for the corresponding part;
The circuit design support system including displaying the calculated number of paths in association with the corresponding part in the behavior level description;
A circuit design support method characterized by the above. The delay path information indicating the delay state of the path in the circuit is presented to the user, and the behavior level description corresponding to the delay path selected by the user is output, thereby prompting the modification of the behavior level description or the behavior synthesis method. A circuit design support method in a circuit design support system,
The circuit design support system analyzes the delay path information, outputs information for selecting a delay path, and accepts selection of a plurality of paths;
The circuit design support system calculating the number of corresponding locations in the behavior level description corresponding to the plurality of selected paths appearing as nodes in the plurality of selected paths;
The circuit design support system including displaying the calculated number of nodes in association with the corresponding part in the behavior level description,
A circuit design support method characterized by the above. A circuit that presents delay path information indicating a delay state of a path in the circuit to the user and outputs an RTL description corresponding to the delay path selected by the user, thereby prompting the behavior level description to be corrected or the behavioral synthesis method to be changed. A circuit design support method in a design support system,
The circuit design support system analyzes the delay path information, outputs information for selecting a delay path, and accepts selection of a plurality of paths;
The circuit design support system calculating the number of paths affected by the modification of the corresponding part in the behavior level description corresponding to the selected plurality of paths or the change of the behavioral synthesis method for the corresponding part;
The circuit design support system including displaying the calculated number of paths in association with an RTL description corresponding to the corresponding part in the behavior level description;
A circuit design support method characterized by the above. A circuit that presents delay path information indicating a delay state of a path in the circuit to the user and outputs an RTL description corresponding to the delay path selected by the user, thereby prompting the behavior level description to be corrected or the behavioral synthesis method to be changed. A circuit design support method in a design support system,
The circuit design support system analyzes the delay path information, outputs information for selecting a delay path, and accepts selection of a plurality of paths;
The circuit design support system calculating the number of corresponding locations in the behavior level description corresponding to the plurality of selected paths appearing as nodes in the plurality of selected paths;
The circuit design support system including displaying the calculated number of nodes in association with an RTL description corresponding to the corresponding location in the behavior level description;
A circuit design support method characterized by the above. The delay level information indicating the delay state of the path in the circuit is presented to the user, and the behavior level description and the RTL description corresponding to the delay path selected by the user are output. A circuit design support method in a circuit design support system for prompting change,
The circuit design support system analyzes the delay path information, outputs information for selecting a delay path, and accepts selection of a plurality of paths;
The circuit design support system calculating the number of paths affected by the modification of the corresponding part in the behavior level description corresponding to the selected plurality of paths or the change of the behavioral synthesis method for the corresponding part;
The circuit design support system displays the calculated number of paths in association with the corresponding part in the behavior level description and the corresponding part of the RTL description corresponding to the corresponding part in the behavior level description. Including steps,
A circuit design support method characterized by the above. The delay level information indicating the delay state of the path in the circuit is presented to the user, and the behavior level description and the RTL description corresponding to the delay path selected by the user are output. A circuit design support method in a circuit design support system for prompting change,
The circuit design support system analyzes the delay path information, outputs information for selecting a delay path, and accepts selection of a plurality of paths;
The circuit design support system calculating the number of corresponding locations in the behavior level description corresponding to the plurality of selected paths appearing as nodes in the plurality of selected paths;
The circuit design support system displays the calculated number of nodes in association with the corresponding part in the behavior level description and the corresponding part of the RTL description corresponding to the corresponding part in the behavior level description. Including the steps of:
A circuit design support method characterized by the above. Further, the circuit design support system includes a step of calculating delay path information from an RTL description (register transfer level description).
The circuit design support method according to any one of claims 10 to 15. The circuit design support system displays a delay path list created by arranging all paths in order of delay values as information for selecting the delay path,
The circuit design support method according to any one of claims 10 to 16. The circuit design support system displays a histogram created using delay values of all paths as information for selecting the delay path,
The circuit design support method according to claim 10, wherein: The delay path information indicating the delay state of the path in the circuit is presented to the user, and the behavior level description corresponding to the delay path selected by the user is output, thereby prompting the modification of the behavior level description or the behavior synthesis method. A program to be executed by a circuit design support system,
Analyzing the delay path information, outputting information for selecting a delay path, and accepting selection of a plurality of paths;
Processing for calculating the number of paths affected by the modification of the corresponding part in the behavior level description corresponding to the plurality of selected paths or the change of the behavioral synthesis method for the corresponding part;
A process of displaying the calculated number of paths in association with the corresponding part in the behavior level description;
For causing the circuit design support system to execute the program. The delay path information indicating the delay state of the path in the circuit is presented to the user, and the behavior level description corresponding to the delay path selected by the user is output, thereby prompting the modification of the behavior level description or the behavior synthesis method. A program to be executed by a circuit design support system,
Analyzing the delay path information, outputting information for selecting a delay path, and accepting selection of a plurality of paths;
Processing for calculating the number of corresponding locations in the behavior level description corresponding to the plurality of selected routes appearing as nodes in the plurality of selected routes;
A process of displaying the calculated number of nodes in association with the corresponding part in the behavior level description;
For causing the circuit design support system to execute the program. A circuit that presents delay path information indicating a delay state of a path in the circuit to the user and outputs an RTL description corresponding to the delay path selected by the user, thereby prompting the behavior level description to be corrected or the behavioral synthesis method to be changed. A program to be executed by a design support system,
Analyzing the delay path information, outputting information for selecting a delay path, and accepting selection of a plurality of paths;
Processing for calculating the number of paths affected by the modification of the corresponding part in the behavior level description corresponding to the plurality of selected paths or the change of the behavioral synthesis method for the corresponding part;
A process of displaying the calculated number of paths in association with an RTL description corresponding to the corresponding part in the behavior level description;
For causing the circuit design support system to execute the program. A circuit that presents delay path information indicating a delay state of a path in the circuit to the user and outputs an RTL description corresponding to the delay path selected by the user, thereby prompting the behavior level description to be corrected or the behavioral synthesis method to be changed. A program to be executed by a design support system,
Analyzing the delay path information, outputting information for selecting a delay path, and accepting selection of a plurality of paths;
Processing for calculating the number of corresponding locations in the behavior level description corresponding to the plurality of selected routes appearing as nodes in the plurality of selected routes;
Processing for displaying the calculated number of nodes in association with the RTL description corresponding to the corresponding part in the behavior level description;
For causing the circuit design support system to execute the program. The delay level information indicating the delay state of the path in the circuit is presented to the user, and the behavior level description and the RTL description corresponding to the delay path selected by the user are output. A program to be executed by a circuit design support system that prompts changes,
Analyzing the delay path information, outputting information for selecting a delay path, and accepting selection of a plurality of paths;
Processing for calculating the number of paths affected by the modification of the corresponding part in the behavior level description corresponding to the plurality of selected paths or the change of the behavioral synthesis method for the corresponding part;
A process of displaying the calculated number of paths in association with the corresponding part in the behavior level description and the corresponding part of the RTL description corresponding to the corresponding part in the behavior level description;
For causing the circuit design support system to execute the program. The delay level information indicating the delay state of the path in the circuit is presented to the user, and the behavior level description and the RTL description corresponding to the delay path selected by the user are output. A program to be executed by a circuit design support system that prompts changes,
Analyzing the delay path information, outputting information for selecting a delay path, and accepting selection of a plurality of paths;
Processing for calculating the number of corresponding locations in the behavior level description corresponding to the plurality of selected routes appearing as nodes in the plurality of selected routes;
A process of displaying the calculated number of nodes in association with the corresponding part in the behavior level description and the corresponding part of the RTL description corresponding to the corresponding part in the behavior level description;
For causing the circuit design support system to execute the program. 25. The program according to claim 19, further causing the circuit design support system to execute processing for calculating delay path information from an RTL description (register transfer level description). The program according to any one of claims 19 to 25, further comprising a delay path list created by arranging all paths in order of delay values as information for selecting the delay path. 27. The program according to claim 19, further comprising displaying a histogram created using delay values of all paths as information for selecting the delay path.

Images